465 lines
13 KiB
C
465 lines
13 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2019 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Samsung S6E3HAB Panel driver.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/of_platform.h>
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#include <linux/module.h>
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#include "panel-samsung-drv.h"
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static unsigned char PPS_TABLE[][88] = {
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{
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/* PPS MODE0 : 1440x3200, Slice Info : 720x40 */
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0x11, 0x00, 0x00, 0x89, 0x30, 0x80, 0x0C, 0x80,
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0x05, 0xA0, 0x00, 0x28, 0x02, 0xD0, 0x02, 0xD0,
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0x02, 0x00, 0x02, 0x68, 0x00, 0x20, 0x04, 0x6C,
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0x00, 0x0A, 0x00, 0x0C, 0x02, 0x77, 0x01, 0xE9,
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0x18, 0x00, 0x10, 0xF0, 0x03, 0x0C, 0x20, 0x00,
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0x06, 0x0B, 0x0B, 0x33, 0x0E, 0x1C, 0x2A, 0x38,
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0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7B,
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0x7D, 0x7E, 0x01, 0x02, 0x01, 0x00, 0x09, 0x40,
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0x09, 0xBE, 0x19, 0xFC, 0x19, 0xFA, 0x19, 0xF8,
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0x1A, 0x38, 0x1A, 0x78, 0x1A, 0xB6, 0x2A, 0xF6,
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0x2B, 0x34, 0x2B, 0x74, 0x3B, 0x74, 0x6B, 0xF4
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},
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{
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/* PPS MODE1 : 1080x2400, Slice Info : 540x40 */
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0x11, 0x00, 0x00, 0x89, 0x30, 0x80, 0x09, 0x60,
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0x04, 0x38, 0x00, 0x28, 0x02, 0x1C, 0x02, 0x1C,
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0x02, 0x00, 0x02, 0x0E, 0x00, 0x20, 0x03, 0xDD,
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0x00, 0x07, 0x00, 0x0C, 0x02, 0x77, 0x02, 0x8B,
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0x18, 0x00, 0x10, 0xF0, 0x03, 0x0C, 0x20, 0x00,
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0x06, 0x0B, 0x0B, 0x33, 0x0E, 0x1C, 0x2A, 0x38,
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0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7B,
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0x7D, 0x7E, 0x01, 0x02, 0x01, 0x00, 0x09, 0x40,
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0x09, 0xBE, 0x19, 0xFC, 0x19, 0xFA, 0x19, 0xF8,
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0x1A, 0x38, 0x1A, 0x78, 0x1A, 0xB6, 0x2A, 0xF6,
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0x2B, 0x34, 0x2B, 0x74, 0x3B, 0x74, 0x6B, 0xF4
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},
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{
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/* PPS MODE2 : 720x1600, Slice Info : 360x80 */
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0x11, 0x00, 0x00, 0x89, 0x30, 0x80, 0x06, 0x40,
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0x02, 0xD0, 0x00, 0x50, 0x01, 0x68, 0x01, 0x68,
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0x02, 0x00, 0x01, 0xB4, 0x00, 0x20, 0x06, 0x2F,
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0x00, 0x05, 0x00, 0x0C, 0x01, 0x38, 0x01, 0xE9,
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0x18, 0x00, 0x10, 0xF0, 0x03, 0x0C, 0x20, 0x00,
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0x06, 0x0B, 0x0B, 0x33, 0x0E, 0x1C, 0x2A, 0x38,
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0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7B,
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0x7D, 0x7E, 0x01, 0x02, 0x01, 0x00, 0x09, 0x40,
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0x09, 0xBE, 0x19, 0xFC, 0x19, 0xFA, 0x19, 0xF8,
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0x1A, 0x38, 0x1A, 0x78, 0x1A, 0xB6, 0x2A, 0xF6,
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0x2B, 0x34, 0x2B, 0x74, 0x3B, 0x74, 0x6B, 0xF4
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},
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};
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static unsigned char SCALER_TABLE[][2] = {
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/* scaler off, 1440x3200 */
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{0xBA, 0x01},
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/* 1.78x scaler on, 1080x2400 */
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{0xBA, 0x02},
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/* 4x scaler on, 720x1600 */
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{0xBA, 0x00},
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};
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static unsigned char CASET_TABLE[][5] = {
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/* scaler off, 1440x3200 */
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{0x2A, 0x00, 0x00, 0x05, 0x9F},
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/* 1.78x scaler on, 1080x2400 */
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{0x2A, 0x00, 0x00, 0x04, 0x37},
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/* 4x scaler on, 720x1600 */
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{0x2A, 0x00, 0x00, 0x02, 0xCF},
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};
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static unsigned char PASET_TABLE[][5] = {
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/* scaler off, 1440x3200 */
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{0x2B, 0x00, 0x00, 0x0C, 0x7F},
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/* 1.78x scaler on, 1080x2400 */
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{0x2B, 0x00, 0x00, 0x09, 0x5F},
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/* 4x scaler on, 720x1600 */
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{0x2B, 0x00, 0x00, 0x06, 0x3F},
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};
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static u32 s6e3hab_find_table_index(const struct exynos_panel *ctx, u32 yres)
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{
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u32 i, val;
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u32 mres_count = ARRAY_SIZE(PPS_TABLE);
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for (i = 0; i < mres_count ; i++) {
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val = (PPS_TABLE[i][6] << 8) | (PPS_TABLE[i][7] << 0);
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if (yres == val)
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return i;
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}
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panel_err(ctx, "no match for yres(%d) -> forcing FHD+ mode\n", yres);
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/* FHD+ mode */
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return 1;
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}
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static int s6e3hab_disable(struct drm_panel *panel)
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{
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struct exynos_panel *ctx;
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ctx = container_of(panel, struct exynos_panel, panel);
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ctx->enabled = false;
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panel_info(ctx, "+\n");
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return 0;
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}
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static int s6e3hab_unprepare(struct drm_panel *panel)
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{
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struct exynos_panel *ctx;
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ctx = container_of(panel, struct exynos_panel, panel);
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panel_info(ctx, "+\n");
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exynos_panel_set_power(ctx, false);
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panel_info(ctx, "-\n");
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return 0;
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}
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static int s6e3hab_prepare(struct drm_panel *panel)
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{
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struct exynos_panel *ctx;
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ctx = container_of(panel, struct exynos_panel, panel);
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panel_info(ctx, "+\n");
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exynos_panel_set_power(ctx, true);
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panel_info(ctx, "-\n");
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return 0;
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}
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static int s6e3hab_set_brightness(struct exynos_panel *exynos_panel, u16 br)
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{
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u16 brightness;
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brightness = (br & 0xff) << 8 | br >> 8;
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return exynos_dcs_set_brightness(exynos_panel, brightness);
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}
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static void s6e3hab_set_resolution(struct exynos_panel *ctx,
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const struct exynos_panel_mode *pmode)
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{
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const struct exynos_display_mode *exynos_mode = &pmode->exynos_mode;
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u32 tab_idx = s6e3hab_find_table_index(ctx, pmode->mode.vdisplay);
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panel_info(ctx, "+\n");
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EXYNOS_DCS_WRITE_SEQ(ctx, 0x9F, 0xA5, 0xA5);
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/* DSC related configuration */
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if (exynos_mode->dsc.enabled) {
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exynos_dcs_compression_mode(ctx, true);
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EXYNOS_PPS_LONG_WRITE_TABLE(ctx, PPS_TABLE[tab_idx]);
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} else {
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exynos_dcs_compression_mode(ctx, false);
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}
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EXYNOS_DCS_WRITE_SEQ(ctx, 0x9F, 0x5A, 0x5A);
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/* partial update configuration */
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EXYNOS_DCS_WRITE_TABLE(ctx, CASET_TABLE[tab_idx]);
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EXYNOS_DCS_WRITE_TABLE(ctx, PASET_TABLE[tab_idx]);
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EXYNOS_DCS_WRITE_SEQ(ctx, 0xF0, 0x5A, 0x5A);
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/* DDI scaling configuration */
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EXYNOS_DCS_WRITE_TABLE(ctx, SCALER_TABLE[tab_idx]);
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EXYNOS_DCS_WRITE_SEQ(ctx, 0xF0, 0xA5, 0xA5);
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panel_info(ctx, "-\n");
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}
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static void s6e3hab_set_vrefresh(struct exynos_panel *ctx,
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const struct drm_display_mode *pmode)
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{
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int vrefresh = drm_mode_vrefresh(pmode);
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panel_info(ctx, "+\n");
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EXYNOS_DCS_WRITE_SEQ(ctx, 0xF0, 0x5A, 0x5A);
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#if defined(CONFIG_EXYNOS_CMD_SVSYNC)
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if (vrefresh == 120) {
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/* TE start timing is advanced by about 3msec due to SV-Sync
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* default value : 3199(active line) + 15(vbp+1) - 2 = 0xC8C
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* modified value : default value - 1200(modifying line) = 0x7DC
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*/
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EXYNOS_DCS_WRITE_SEQ(ctx, 0xB9, 0x01, 0x70, 0xDC, 0x09);
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} else {
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/* TE start timing is advanced by about 3msec due to SV-Sync
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* default value : 3199(active line) + 15(vbp+1) - 2 = 0xC8C
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* modified value : default value - 600(modifying line) = 0xA34
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*/
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EXYNOS_DCS_WRITE_SEQ(ctx, 0xB9, 0x01, 0xA0, 0x34, 0x09);
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}
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#endif
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if (vrefresh == 60) {
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EXYNOS_DCS_WRITE_SEQ(ctx, 0x9F, 0xA5, 0xA5);
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EXYNOS_DCS_WRITE_SEQ(ctx, 0x60, 0x00);
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EXYNOS_DCS_WRITE_SEQ(ctx, 0x9F, 0x5A, 0x5A);
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} else if (vrefresh == 120) {
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EXYNOS_DCS_WRITE_SEQ(ctx, 0x9F, 0xA5, 0xA5);
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EXYNOS_DCS_WRITE_SEQ(ctx, 0x60, 0x20);
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EXYNOS_DCS_WRITE_SEQ(ctx, 0x9F, 0x5A, 0x5A);
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} else if (vrefresh == 30) {
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// lp mode
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} else {
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panel_err(ctx, "not supported fps(%d)\n", vrefresh);
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goto end;
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}
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/* Panelupdate : gamma set, ltps set, transition control update */
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EXYNOS_DCS_WRITE_SEQ(ctx, 0xF7, 0x0F);
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end:
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EXYNOS_DCS_WRITE_SEQ(ctx, 0xF0, 0xA5, 0xA5);
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panel_info(ctx, "-\n");
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}
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static void s6e3hab_mode_set(struct exynos_panel *ctx,
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const struct exynos_panel_mode *pmode, unsigned int flags)
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{
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panel_info(ctx, "+\n");
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if (!ctx->enabled)
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return;
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if (SEAMLESS_MODESET_MRES & flags)
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s6e3hab_set_resolution(ctx, pmode);
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if (SEAMLESS_MODESET_VREF & flags)
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s6e3hab_set_vrefresh(ctx, &pmode->mode);
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panel_info(ctx, "-\n");
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}
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static void s6e3hab_lp_mode_set(struct exynos_panel *ctx,
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const struct exynos_panel_mode *pmode)
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{
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if (!ctx->enabled)
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return;
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panel_info(ctx, "enter %dhz LP mode\n", drm_mode_vrefresh(&pmode->mode));
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}
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static int s6e3hab_enable(struct drm_panel *panel)
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{
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struct exynos_panel *ctx = container_of(panel, struct exynos_panel, panel);
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const struct exynos_panel_mode *pmode = ctx->current_mode;
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const struct drm_display_mode *mode;
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u32 tab_idx;
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if (!pmode) {
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panel_err(ctx, "no current mode set\n");
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return -EINVAL;
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}
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mode = &pmode->mode;
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panel_info(ctx, "+\n");
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exynos_panel_reset(ctx);
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EXYNOS_DCS_WRITE_SEQ(ctx, 0xf0, 0x5a, 0x5a);
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EXYNOS_DCS_WRITE_SEQ(ctx, 0xfc, 0x5a, 0x5a);
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/* DSC related configuration */
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exynos_dcs_compression_mode(ctx, true);
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EXYNOS_PPS_LONG_WRITE_TABLE(ctx, PPS_TABLE[0]);
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/* sleep out: 200ms delay */
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EXYNOS_DCS_WRITE_SEQ_DELAY(ctx, 200, 0x11);
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EXYNOS_DCS_WRITE_SEQ(ctx, 0xB9, 0x00, 0xC0, 0x8C, 0x09, 0x00, 0x00,
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0x00, 0x11, 0x03);
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/* enable brightness control */
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EXYNOS_DCS_WRITE_SEQ(ctx, 0x53, 0x20);
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/* WRDISBV(51h) = 1st[7:0], 2nd[15:8] */
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EXYNOS_DCS_WRITE_SEQ(ctx, 0x51, 0xff, 0x7f);
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EXYNOS_DCS_WRITE_SEQ(ctx, 0x35); /* TE on */
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/* ESD flag: [2]=VLIN3, [6]=VLIN1 error check*/
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EXYNOS_DCS_WRITE_SEQ(ctx, 0xED, 0x04, 0x44);
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/* Typical high duration: 123.57 (122~125us) */
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EXYNOS_DCS_WRITE_SEQ(ctx, 0xB9, 0x00, 0xC0, 0x8C, 0x09);
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/* vrefresh rate configuration */
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s6e3hab_set_vrefresh(ctx, mode);
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EXYNOS_DCS_WRITE_SEQ(ctx, 0x9F, 0xA5, 0xA5);
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EXYNOS_DCS_WRITE_SEQ(ctx, 0x29); /* display on */
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EXYNOS_DCS_WRITE_SEQ(ctx, 0x9F, 0x5A, 0x5A);
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tab_idx = s6e3hab_find_table_index(ctx, mode->vdisplay);
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if (tab_idx)
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s6e3hab_set_resolution(ctx, pmode);
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ctx->enabled = true;
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if (pmode->exynos_mode.is_lp_mode)
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s6e3hab_lp_mode_set(ctx, pmode);
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|
panel_info(ctx, "-\n");
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* drm_display_mode
|
||
|
|
*
|
||
|
|
* @clock: vtotal * htotal * fps / 1000
|
||
|
|
* @hdisplay = horizon resolution
|
||
|
|
* @hsync_start = hdisplay + hfp
|
||
|
|
* @hsync_end = hdisplay + hfp + hsa
|
||
|
|
* @htotal = hdisplay + hfp + hsa + hbp
|
||
|
|
* @vdisplay = vertical resolution,
|
||
|
|
* @vsync_start = vdisplay + vfp
|
||
|
|
* @vsync_end = vdisplay + vfp + vsa
|
||
|
|
* @vtotal = vdisplay + vfp + vsa + + vbp
|
||
|
|
*/
|
||
|
|
#if IS_ENABLED(CONFIG_SOC_S5E8825)
|
||
|
|
static const struct exynos_panel_mode s6e3hab_mode[] = {
|
||
|
|
{
|
||
|
|
.mode = { DRM_MODE("1080x2400@60", DRM_MODE_TYPE_DRIVER, 157948,
|
||
|
|
1080, 1082, 1084, 1086, 0, 2400, 2408, 2409,
|
||
|
|
2424, 0, 0) },
|
||
|
|
.exynos_mode = { EXYNOS_MODE(MIPI_DSI_CLOCK_NON_CONTINUOUS,
|
||
|
|
8, false, true, 1, 2, 40)},
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.mode = { DRM_MODE("1080x2400@120", DRM_MODE_TYPE_DRIVER, 315896,
|
||
|
|
1080, 1082, 1084, 1086, 0, 2400, 2408, 2409,
|
||
|
|
2424, 0, 0) },
|
||
|
|
.exynos_mode = { EXYNOS_MODE(MIPI_DSI_CLOCK_NON_CONTINUOUS,
|
||
|
|
8, false, true, 1, 2, 40)},
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct exynos_panel_mode s6e3hab_lp_mode[] = {
|
||
|
|
{
|
||
|
|
.mode = { DRM_MODE("1080x2400@30", DRM_MODE_TYPE_DRIVER, 78974,
|
||
|
|
1080, 1082, 1084, 1086, 0, 2400, 2408, 2409,
|
||
|
|
2424, 0, 0) },
|
||
|
|
.exynos_mode = { EXYNOS_MODE(MIPI_DSI_CLOCK_NON_CONTINUOUS,
|
||
|
|
8, true, true, 1, 2, 40)},
|
||
|
|
},
|
||
|
|
};
|
||
|
|
#else
|
||
|
|
static const struct exynos_panel_mode s6e3hab_mode[] = {
|
||
|
|
{
|
||
|
|
.mode = { DRM_MODE("1440x3200@60", DRM_MODE_TYPE_DRIVER, 279714,
|
||
|
|
1440, 1442, 1444, 1446, 0, 3200, 3208, 3209,
|
||
|
|
3224, 0, 0)},
|
||
|
|
.exynos_mode = { EXYNOS_MODE(MIPI_DSI_CLOCK_NON_CONTINUOUS,
|
||
|
|
8, false, true, 2, 2, 40)},
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.mode = { DRM_MODE("1080x2400@60", DRM_MODE_TYPE_DRIVER, 157948,
|
||
|
|
1080, 1082, 1084, 1086, 0, 2400, 2408, 2409,
|
||
|
|
2424, 0, 0) },
|
||
|
|
.exynos_mode = { EXYNOS_MODE(MIPI_DSI_CLOCK_NON_CONTINUOUS,
|
||
|
|
8, false, true, 2, 2, 40)},
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.mode = { DRM_MODE("1080x2400@120", DRM_MODE_TYPE_DRIVER, 315896,
|
||
|
|
1080, 1082, 1084, 1086, 0, 2400, 2408, 2409,
|
||
|
|
2424, 0, 0) },
|
||
|
|
.exynos_mode = { EXYNOS_MODE(MIPI_DSI_CLOCK_NON_CONTINUOUS,
|
||
|
|
8, false, true, 2, 2, 40)},
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.mode = { DRM_MODE("720x1600@60", DRM_MODE_TYPE_DRIVER, 70741,
|
||
|
|
720, 722, 724, 726, 0, 1600, 1608, 1609,
|
||
|
|
1624, 0, 0) },
|
||
|
|
.exynos_mode = { EXYNOS_MODE(MIPI_DSI_CLOCK_NON_CONTINUOUS,
|
||
|
|
8, false, true, 2, 2, 80)},
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.mode = { DRM_MODE("720x1600@120", DRM_MODE_TYPE_DRIVER, 141483,
|
||
|
|
720, 722, 724, 726, 0, 1600, 1608, 1609,
|
||
|
|
1624, 0, 0) },
|
||
|
|
.exynos_mode = { EXYNOS_MODE(MIPI_DSI_CLOCK_NON_CONTINUOUS,
|
||
|
|
8, false, true, 2, 2, 80)},
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct exynos_panel_mode s6e3hab_lp_mode[] = {
|
||
|
|
{
|
||
|
|
.mode = { DRM_MODE("1440x3200@30", DRM_MODE_TYPE_DRIVER, 139857,
|
||
|
|
1440, 1442, 1444, 1446, 0, 3200, 3208, 3209,
|
||
|
|
3224, 0, 0)},
|
||
|
|
.exynos_mode = { EXYNOS_MODE(MIPI_DSI_CLOCK_NON_CONTINUOUS,
|
||
|
|
8, true, true, 2, 2, 40)},
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.mode = { DRM_MODE("1080x2400@30", DRM_MODE_TYPE_DRIVER, 78974,
|
||
|
|
1080, 1082, 1084, 1086, 0, 2400, 2408, 2409,
|
||
|
|
2424, 0, 0) },
|
||
|
|
.exynos_mode = { EXYNOS_MODE(MIPI_DSI_CLOCK_NON_CONTINUOUS,
|
||
|
|
8, true, true, 2, 2, 40)},
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.mode = { DRM_MODE("720x1600@30", DRM_MODE_TYPE_DRIVER, 35371,
|
||
|
|
720, 722, 724, 726, 0, 1600, 1608, 1609,
|
||
|
|
1624, 0, 0) },
|
||
|
|
.exynos_mode = { EXYNOS_MODE(MIPI_DSI_CLOCK_NON_CONTINUOUS,
|
||
|
|
8, true, true, 2, 2, 80)},
|
||
|
|
},
|
||
|
|
};
|
||
|
|
#endif
|
||
|
|
|
||
|
|
static const struct drm_panel_funcs s6e3hab_drm_funcs = {
|
||
|
|
.disable = s6e3hab_disable,
|
||
|
|
.unprepare = s6e3hab_unprepare,
|
||
|
|
.prepare = s6e3hab_prepare,
|
||
|
|
.enable = s6e3hab_enable,
|
||
|
|
.get_modes = exynos_panel_get_modes,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct exynos_panel_funcs s6e3hab_exynos_funcs = {
|
||
|
|
.set_brightness = s6e3hab_set_brightness,
|
||
|
|
.set_lp_mode = s6e3hab_lp_mode_set,
|
||
|
|
.mode_set = s6e3hab_mode_set,
|
||
|
|
};
|
||
|
|
|
||
|
|
const struct exynos_panel_desc samsung_s6e3hab = {
|
||
|
|
.data_lane_cnt = 4,
|
||
|
|
.max_brightness = 1023, /* TODO check */
|
||
|
|
.dft_brightness = 511, /* TODO check */
|
||
|
|
.modes = s6e3hab_mode,
|
||
|
|
.num_modes = ARRAY_SIZE(s6e3hab_mode),
|
||
|
|
.lp_modes = s6e3hab_lp_mode,
|
||
|
|
.num_lp_modes = ARRAY_SIZE(s6e3hab_lp_mode),
|
||
|
|
.panel_func = &s6e3hab_drm_funcs,
|
||
|
|
.exynos_panel_func = &s6e3hab_exynos_funcs,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct of_device_id exynos_panel_of_match[] = {
|
||
|
|
{ .compatible = "samsung,s6e3hab", .data = &samsung_s6e3hab },
|
||
|
|
{ }
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(of, exynos_panel_of_match);
|
||
|
|
|
||
|
|
static struct mipi_dsi_driver exynos_panel_driver = {
|
||
|
|
.probe = exynos_panel_probe,
|
||
|
|
.remove = exynos_panel_remove,
|
||
|
|
.driver = {
|
||
|
|
.name = "panel-samsung-s6e3hab",
|
||
|
|
.of_match_table = exynos_panel_of_match,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
module_mipi_dsi_driver(exynos_panel_driver);
|
||
|
|
|
||
|
|
MODULE_AUTHOR("Wonyoeng choi <won0.choi@samsung.com>");
|
||
|
|
MODULE_DESCRIPTION("MIPI-DSI based Samsung s6e3hab panel driver");
|
||
|
|
MODULE_LICENSE("GPL");
|