474 lines
9 KiB
Text
474 lines
9 KiB
Text
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/dts-v1/;
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/ {
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interrupt-parent = <0x01>;
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#address-cells = <0x02>;
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#size-cells = <0x02>;
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model = "Xiaomi Redmi Note 7";
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compatible = "xiaomi,lavender\0qcom,sdm660";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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clocks {
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xo_board {
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compatible = "fixed-clock";
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#clock-cells = <0x00>;
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clock-frequency = <0x124f800>;
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clock-output-names = "xo_board";
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phandle = <0x0f>;
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};
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sleep_clk {
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compatible = "fixed-clock";
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#clock-cells = <0x00>;
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clock-frequency = <0x7ffc>;
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clock-output-names = "sleep_clk";
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phandle = <0x10>;
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};
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};
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cpus {
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#address-cells = <0x02>;
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#size-cells = <0x00>;
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cpu@100 {
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device_type = "cpu";
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compatible = "qcom,kryo260";
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reg = <0x00 0x100>;
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enable-method = "psci";
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capacity-dmips-mhz = <0x400>;
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next-level-cache = <0x02>;
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phandle = <0x08>;
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l2-cache {
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compatible = "cache";
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cache-level = <0x02>;
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phandle = <0x02>;
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};
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l1-icache {
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compatible = "cache";
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phandle = <0x11>;
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};
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l1-dcache {
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compatible = "cache";
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phandle = <0x12>;
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};
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};
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cpu@101 {
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device_type = "cpu";
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compatible = "qcom,kryo260";
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reg = <0x00 0x101>;
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enable-method = "psci";
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capacity-dmips-mhz = <0x400>;
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next-level-cache = <0x02>;
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phandle = <0x09>;
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l1-icache {
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compatible = "cache";
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phandle = <0x13>;
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};
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l1-dcache {
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compatible = "cache";
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phandle = <0x14>;
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};
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};
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cpu@102 {
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device_type = "cpu";
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compatible = "qcom,kryo260";
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reg = <0x00 0x102>;
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enable-method = "psci";
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capacity-dmips-mhz = <0x400>;
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next-level-cache = <0x02>;
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phandle = <0x0a>;
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l1-icache {
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compatible = "cache";
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phandle = <0x15>;
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};
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l1-dcache {
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compatible = "cache";
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phandle = <0x16>;
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};
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};
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cpu@103 {
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device_type = "cpu";
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compatible = "qcom,kryo260";
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reg = <0x00 0x103>;
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enable-method = "psci";
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capacity-dmips-mhz = <0x400>;
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next-level-cache = <0x02>;
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phandle = <0x0b>;
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l1-icache {
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compatible = "cache";
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phandle = <0x17>;
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};
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l1-dcache {
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compatible = "cache";
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phandle = <0x18>;
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};
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};
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cpu@0 {
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device_type = "cpu";
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compatible = "qcom,kryo260";
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reg = <0x00 0x00>;
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enable-method = "psci";
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capacity-dmips-mhz = <0x280>;
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next-level-cache = <0x03>;
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phandle = <0x04>;
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l2-cache {
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compatible = "cache";
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cache-level = <0x02>;
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phandle = <0x03>;
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};
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l1-icache {
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compatible = "cache";
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phandle = <0x19>;
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};
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l1-dcache {
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compatible = "cache";
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phandle = <0x1a>;
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};
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "qcom,kryo260";
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reg = <0x00 0x01>;
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enable-method = "psci";
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capacity-dmips-mhz = <0x280>;
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next-level-cache = <0x03>;
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phandle = <0x05>;
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l1-icache {
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compatible = "cache";
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phandle = <0x1b>;
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};
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l1-dcache {
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compatible = "cache";
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phandle = <0x1c>;
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};
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "qcom,kryo260";
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reg = <0x00 0x02>;
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enable-method = "psci";
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capacity-dmips-mhz = <0x280>;
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next-level-cache = <0x03>;
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phandle = <0x06>;
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l1-icache {
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compatible = "cache";
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phandle = <0x1d>;
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};
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l1-dcache {
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compatible = "cache";
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phandle = <0x1e>;
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};
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "qcom,kryo260";
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reg = <0x00 0x03>;
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enable-method = "psci";
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capacity-dmips-mhz = <0x280>;
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next-level-cache = <0x03>;
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phandle = <0x07>;
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l1-icache {
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compatible = "cache";
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phandle = <0x1f>;
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};
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l1-dcache {
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compatible = "cache";
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phandle = <0x20>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <0x04>;
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};
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core1 {
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cpu = <0x05>;
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};
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core2 {
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cpu = <0x06>;
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};
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core3 {
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cpu = <0x07>;
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};
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};
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cluster1 {
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core0 {
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cpu = <0x08>;
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};
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core1 {
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cpu = <0x09>;
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};
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core2 {
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cpu = <0x0a>;
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};
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core3 {
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cpu = <0x0b>;
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};
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};
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};
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};
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firmware {
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scm {
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compatible = "qcom,scm";
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00 0x00 0x00 0x00>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <0x01 0x01 0x08 0x01 0x02 0x08 0x01 0x03 0x08 0x01 0x00 0x08>;
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};
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soc {
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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ranges = <0x00 0x00 0x00 0xffffffff>;
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compatible = "simple-bus";
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phandle = <0x21>;
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clock-controller@100000 {
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compatible = "qcom,gcc-sdm660";
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#clock-cells = <0x01>;
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#reset-cells = <0x01>;
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#power-domain-cells = <0x01>;
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reg = <0x100000 0x94000>;
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phandle = <0x0d>;
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};
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pinctrl@3100000 {
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compatible = "qcom,sdm660-pinctrl";
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reg = <0x3100000 0x400000 0x3500000 0x400000 0x3900000 0x400000>;
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reg-names = "south\0center\0north";
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interrupts = <0x00 0xd0 0x04>;
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gpio-controller;
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gpio-ranges = <0x0c 0x00 0x00 0x72>;
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#gpio-cells = <0x02>;
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interrupt-controller;
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#interrupt-cells = <0x02>;
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gpio-reserved-ranges = <0x08 0x04>;
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phandle = <0x0c>;
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uart_console_active {
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phandle = <0x0e>;
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pinmux {
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pins = "gpio4\0gpio5";
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function = "blsp_uart2";
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};
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pinconf {
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pins = "gpio4\0gpio5";
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drive-strength = <0x02>;
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bias-disable;
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};
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};
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};
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spmi@800f000 {
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compatible = "qcom,spmi-pmic-arb";
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reg = <0x800f000 0x1000 0x8400000 0x1000000 0x9400000 0x1000000 0xa400000 0x220000 0x800a000 0x3000>;
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reg-names = "core\0chnls\0obsrvr\0intr\0cnfg";
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interrupt-names = "periph_irq";
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interrupts = <0x00 0x146 0x04>;
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qcom,ee = <0x00>;
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qcom,channel = <0x00>;
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#address-cells = <0x02>;
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#size-cells = <0x00>;
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interrupt-controller;
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#interrupt-cells = <0x04>;
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cell-index = <0x00>;
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phandle = <0x22>;
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};
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serial@c170000 {
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compatible = "qcom,msm-uartdm-v1.4\0qcom,msm-uartdm";
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reg = <0xc170000 0x1000>;
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interrupts = <0x00 0x6c 0x04>;
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clocks = <0x0d 0x23 0x0d 0x19>;
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clock-names = "core\0iface";
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <0x0e>;
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phandle = <0x23>;
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};
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timer@17920000 {
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0x17920000 0x1000>;
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frame@17921000 {
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frame-number = <0x00>;
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interrupts = <0x00 0x08 0x04 0x00 0x07 0x04>;
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reg = <0x17921000 0x1000 0x17922000 0x1000>;
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};
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frame@17923000 {
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frame-number = <0x01>;
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interrupts = <0x00 0x09 0x04>;
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reg = <0x17923000 0x1000>;
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status = "disabled";
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};
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frame@17924000 {
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frame-number = <0x02>;
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interrupts = <0x00 0x0a 0x04>;
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reg = <0x17924000 0x1000>;
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status = "disabled";
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};
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frame@17925000 {
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frame-number = <0x03>;
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interrupts = <0x00 0x0b 0x04>;
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reg = <0x17925000 0x1000>;
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status = "disabled";
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};
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frame@17926000 {
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frame-number = <0x04>;
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interrupts = <0x00 0x0c 0x04>;
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reg = <0x17926000 0x1000>;
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status = "disabled";
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};
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frame@17927000 {
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frame-number = <0x05>;
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interrupts = <0x00 0x0d 0x04>;
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reg = <0x17927000 0x1000>;
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status = "disabled";
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};
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frame@17928000 {
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frame-number = <0x06>;
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interrupts = <0x00 0x0e 0x04>;
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reg = <0x17928000 0x1000>;
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status = "disabled";
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};
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};
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interrupt-controller@17a00000 {
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compatible = "arm,gic-v3";
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reg = <0x17a00000 0x10000 0x17b00000 0x100000>;
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#interrupt-cells = <0x03>;
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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ranges;
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interrupt-controller;
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||
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|
#redistributor-regions = <0x01>;
|
||
|
|
redistributor-stride = <0x00 0x20000>;
|
||
|
|
interrupts = <0x01 0x09 0x04>;
|
||
|
|
phandle = <0x01>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
aliases {
|
||
|
|
serial0 = "/soc/serial@c170000";
|
||
|
|
};
|
||
|
|
|
||
|
|
reserved-memory {
|
||
|
|
#address-cells = <0x02>;
|
||
|
|
#size-cells = <0x02>;
|
||
|
|
ranges;
|
||
|
|
|
||
|
|
ramoops@a0000000 {
|
||
|
|
compatible = "ramoops";
|
||
|
|
reg = <0x00 0xa0000000 0x00 0x400000>;
|
||
|
|
console-size = <0x20000>;
|
||
|
|
record-size = <0x20000>;
|
||
|
|
ftrace-size = <0x00>;
|
||
|
|
pmsg-size = <0x20000>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
__symbols__ {
|
||
|
|
xo_board = "/clocks/xo_board";
|
||
|
|
sleep_clk = "/clocks/sleep_clk";
|
||
|
|
CPU0 = "/cpus/cpu@100";
|
||
|
|
L2_1 = "/cpus/cpu@100/l2-cache";
|
||
|
|
L1_I_100 = "/cpus/cpu@100/l1-icache";
|
||
|
|
L1_D_100 = "/cpus/cpu@100/l1-dcache";
|
||
|
|
CPU1 = "/cpus/cpu@101";
|
||
|
|
L1_I_101 = "/cpus/cpu@101/l1-icache";
|
||
|
|
L1_D_101 = "/cpus/cpu@101/l1-dcache";
|
||
|
|
CPU2 = "/cpus/cpu@102";
|
||
|
|
L1_I_102 = "/cpus/cpu@102/l1-icache";
|
||
|
|
L1_D_102 = "/cpus/cpu@102/l1-dcache";
|
||
|
|
CPU3 = "/cpus/cpu@103";
|
||
|
|
L1_I_103 = "/cpus/cpu@103/l1-icache";
|
||
|
|
L1_D_103 = "/cpus/cpu@103/l1-dcache";
|
||
|
|
CPU4 = "/cpus/cpu@0";
|
||
|
|
L2_0 = "/cpus/cpu@0/l2-cache";
|
||
|
|
L1_I_0 = "/cpus/cpu@0/l1-icache";
|
||
|
|
L1_D_0 = "/cpus/cpu@0/l1-dcache";
|
||
|
|
CPU5 = "/cpus/cpu@1";
|
||
|
|
L1_I_1 = "/cpus/cpu@1/l1-icache";
|
||
|
|
L1_D_1 = "/cpus/cpu@1/l1-dcache";
|
||
|
|
CPU6 = "/cpus/cpu@2";
|
||
|
|
L1_I_2 = "/cpus/cpu@2/l1-icache";
|
||
|
|
L1_D_2 = "/cpus/cpu@2/l1-dcache";
|
||
|
|
CPU7 = "/cpus/cpu@3";
|
||
|
|
L1_I_3 = "/cpus/cpu@3/l1-icache";
|
||
|
|
L1_D_3 = "/cpus/cpu@3/l1-dcache";
|
||
|
|
soc = "/soc";
|
||
|
|
gcc = "/soc/clock-controller@100000";
|
||
|
|
tlmm = "/soc/pinctrl@3100000";
|
||
|
|
uart_console_active = "/soc/pinctrl@3100000/uart_console_active";
|
||
|
|
spmi_bus = "/soc/spmi@800f000";
|
||
|
|
blsp1_uart2 = "/soc/serial@c170000";
|
||
|
|
intc = "/soc/interrupt-controller@17a00000";
|
||
|
|
};
|
||
|
|
};
|