802 lines
18 KiB
Text
802 lines
18 KiB
Text
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/dts-v1/;
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/ {
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interrupt-parent = <0x01>;
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#address-cells = <0x02>;
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#size-cells = <0x02>;
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model = "Microsoft Lumia 950";
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compatible = "microsoft,talkman\0qcom,msm8992";
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chosen {
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bootargs = "earlycon=efifb console=efifb acpi=no";
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#address-cells = <0x02>;
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#size-cells = <0x02>;
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ranges;
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};
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cpus {
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#address-cells = <0x02>;
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#size-cells = <0x00>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x00 0x00>;
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next-level-cache = <0x02>;
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enable-method = "psci";
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phandle = <0x04>;
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l2-cache {
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compatible = "cache";
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cache-level = <0x02>;
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phandle = <0x02>;
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};
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x00 0x01>;
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next-level-cache = <0x02>;
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enable-method = "psci";
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phandle = <0x05>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x00 0x02>;
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next-level-cache = <0x02>;
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enable-method = "psci";
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phandle = <0x06>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x00 0x03>;
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next-level-cache = <0x02>;
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enable-method = "psci";
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phandle = <0x07>;
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};
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cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x00 0x100>;
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next-level-cache = <0x03>;
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enable-method = "psci";
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phandle = <0x08>;
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l2-cache {
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compatible = "cache";
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cache-level = <0x02>;
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phandle = <0x03>;
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};
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};
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cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x00 0x101>;
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next-level-cache = <0x03>;
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enable-method = "psci";
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phandle = <0x09>;
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <0x04>;
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};
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core1 {
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cpu = <0x05>;
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};
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core2 {
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cpu = <0x06>;
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};
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core3 {
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cpu = <0x07>;
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};
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};
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cluster1 {
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core0 {
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cpu = <0x08>;
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};
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core1 {
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cpu = <0x09>;
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};
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};
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};
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};
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clocks {
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xo_board {
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compatible = "fixed-clock";
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#clock-cells = <0x00>;
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clock-frequency = <0x124f800>;
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phandle = <0x0f>;
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};
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sleep_clk {
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compatible = "fixed-clock";
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#clock-cells = <0x00>;
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clock-frequency = <0x8000>;
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phandle = <0x29>;
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};
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};
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firmware {
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scm {
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compatible = "qcom,scm-msm8994\0qcom,scm";
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00 0x00 0x00 0x00>;
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};
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pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <0x01 0x07 0xf04>;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "hvc";
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};
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reserved-memory {
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#address-cells = <0x02>;
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#size-cells = <0x02>;
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ranges;
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smem@6a00000 {
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reg = <0x00 0x6a00000 0x00 0x200000>;
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no-map;
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phandle = <0x0b>;
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};
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};
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hwmutex {
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compatible = "qcom,sfpb-mutex";
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syscon = <0x0a 0x00 0x100>;
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#hwlock-cells = <0x01>;
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phandle = <0x0d>;
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};
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smem {
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compatible = "qcom,smem";
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memory-region = <0x0b>;
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qcom,rpm-msg-ram = <0x0c>;
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hwlocks = <0x0d 0x03>;
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};
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soc {
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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ranges = <0x00 0x00 0x00 0xffffffff>;
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compatible = "simple-bus";
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interrupt-controller@f9000000 {
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
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#interrupt-cells = <0x03>;
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reg = <0xf9000000 0x1000 0xf9002000 0x1000>;
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phandle = <0x01>;
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};
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mailbox@f900d000 {
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compatible = "qcom,msm8994-apcs-kpss-global\0syscon";
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reg = <0xf900d000 0x2000>;
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#mbox-cells = <0x01>;
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phandle = <0x28>;
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};
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timer@f9020000 {
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0xf9020000 0x1000>;
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frame@f9021000 {
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frame-number = <0x00>;
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interrupts = <0x00 0x09 0x04 0x00 0x08 0x04>;
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reg = <0xf9021000 0x1000 0xf9022000 0x1000>;
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};
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frame@f9023000 {
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frame-number = <0x01>;
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interrupts = <0x00 0x0a 0x04>;
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reg = <0xf9023000 0x1000>;
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status = "disabled";
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};
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frame@f9024000 {
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frame-number = <0x02>;
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interrupts = <0x00 0x0b 0x04>;
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reg = <0xf9024000 0x1000>;
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status = "disabled";
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};
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frame@f9025000 {
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frame-number = <0x03>;
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interrupts = <0x00 0x0c 0x04>;
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reg = <0xf9025000 0x1000>;
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status = "disabled";
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};
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frame@f9026000 {
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frame-number = <0x04>;
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interrupts = <0x00 0x0d 0x04>;
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reg = <0xf9026000 0x1000>;
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status = "disabled";
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};
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frame@f9027000 {
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frame-number = <0x05>;
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interrupts = <0x00 0x0e 0x04>;
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reg = <0xf9027000 0x1000>;
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status = "disabled";
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};
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frame@f9028000 {
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frame-number = <0x06>;
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interrupts = <0x00 0x0f 0x04>;
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reg = <0xf9028000 0x1000>;
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status = "disabled";
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};
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};
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sdhci@f9824900 {
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compatible = "qcom,sdhci-msm-v4";
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reg = <0xf9824900 0x1a0 0xf9824000 0x800>;
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reg-names = "hc_mem\0core_mem";
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interrupts = <0x00 0x7b 0x04 0x00 0x8a 0x04>;
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interrupt-names = "hc_irq\0pwr_irq";
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clocks = <0x0e 0x68 0x0e 0x76 0x0f>;
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clock-names = "core\0iface\0xo";
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pinctrl-names = "default\0sleep";
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pinctrl-0 = <0x10 0x11 0x12 0x13>;
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pinctrl-1 = <0x14 0x15 0x16 0x17>;
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regulator-always-on;
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bus-width = <0x08>;
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non-removable;
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status = "okay";
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mmc-hs200-1_8v;
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phandle = <0x2a>;
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};
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serial@f991e000 {
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compatible = "qcom,msm-uartdm-v1.4\0qcom,msm-uartdm";
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reg = <0xf991e000 0x1000>;
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interrupts = <0x00 0x6c 0x08>;
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clock-names = "core\0iface";
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clocks = <0x0e 0x48 0x0e 0x3a>;
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pinctrl-names = "default\0sleep";
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pinctrl-0 = <0x18>;
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pinctrl-1 = <0x19>;
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status = "disabled";
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phandle = <0x2b>;
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};
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i2c@f9924000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0xf9924000 0x500>;
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interrupts = <0x00 0x60 0x04>;
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clocks = <0x0e 0x3a 0x0e 0x3d>;
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clock-names = "iface\0core";
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clock-frequency = <0x61a80>;
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pinctrl-names = "default\0sleep";
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pinctrl-0 = <0x1a>;
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pinctrl-1 = <0x1b>;
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#address-cells = <0x01>;
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#size-cells = <0x00>;
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status = "disabled";
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phandle = <0x2c>;
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};
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i2c@f9927000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0xf9927000 0x500>;
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interrupts = <0x00 0x63 0x04>;
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clocks = <0x0e 0x3a 0x0e 0x43>;
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clock-names = "iface\0core";
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clock-frequency = <0x61a80>;
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pinctrl-names = "default\0sleep";
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pinctrl-0 = <0x1c>;
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pinctrl-1 = <0x1d>;
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#address-cells = <0x01>;
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#size-cells = <0x00>;
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status = "disabled";
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phandle = <0x2d>;
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};
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i2c@f9928000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0xf9928000 0x500>;
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interrupts = <0x00 0x64 0x04>;
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clocks = <0x0e 0x3a 0x0e 0x45>;
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clock-names = "iface\0core";
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clock-frequency = <0x61a80>;
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pinctrl-names = "default\0sleep";
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pinctrl-0 = <0x1e>;
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pinctrl-1 = <0x1f>;
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#address-cells = <0x01>;
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#size-cells = <0x00>;
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status = "disabled";
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phandle = <0x2e>;
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};
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serial@f995e000 {
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compatible = "qcom,msm-uartdm-v1.4\0qcom,msm-uartdm";
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reg = <0xf995e000 0x1000>;
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interrupts = <0x00 0x92 0x08>;
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clock-names = "core\0iface";
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clocks = <0x0e 0x5b 0x0e 0x4d>;
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pinctrl-names = "default\0sleep";
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pinctrl-0 = <0x20>;
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pinctrl-1 = <0x21>;
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status = "disabled";
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phandle = <0x2f>;
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};
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i2c@f9963000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0xf9963000 0x500>;
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interrupts = <0x00 0x65 0x04>;
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clocks = <0x0e 0x4d 0x0e 0x4e>;
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clock-names = "iface\0core";
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clock-frequency = <0x61a80>;
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pinctrl-names = "default\0sleep";
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pinctrl-0 = <0x22>;
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pinctrl-1 = <0x23>;
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#address-cells = <0x01>;
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#size-cells = <0x00>;
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status = "disabled";
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phandle = <0x30>;
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};
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i2c@f9967000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0xf9967000 0x500>;
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interrupts = <0x00 0x69 0x04>;
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clocks = <0x0e 0x4d 0x0e 0x56>;
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clock-names = "iface\0core";
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clock-frequency = <0x186a0>;
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pinctrl-names = "default\0sleep";
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pinctrl-0 = <0x24>;
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pinctrl-1 = <0x25>;
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|
#address-cells = <0x01>;
|
||
|
|
#size-cells = <0x00>;
|
||
|
|
status = "disabled";
|
||
|
|
phandle = <0x31>;
|
||
|
|
};
|
||
|
|
|
||
|
|
clock-controller@fc400000 {
|
||
|
|
compatible = "qcom,gcc-msm8994";
|
||
|
|
#clock-cells = <0x01>;
|
||
|
|
#reset-cells = <0x01>;
|
||
|
|
#power-domain-cells = <0x01>;
|
||
|
|
reg = <0xfc400000 0x2000>;
|
||
|
|
phandle = <0x0e>;
|
||
|
|
};
|
||
|
|
|
||
|
|
memory@fc428000 {
|
||
|
|
compatible = "qcom,rpm-msg-ram";
|
||
|
|
reg = <0xfc428000 0x4000>;
|
||
|
|
phandle = <0x0c>;
|
||
|
|
};
|
||
|
|
|
||
|
|
restart@fc4ab000 {
|
||
|
|
compatible = "qcom,pshold";
|
||
|
|
reg = <0xfc4ab000 0x04>;
|
||
|
|
};
|
||
|
|
|
||
|
|
spmi@fc4c0000 {
|
||
|
|
compatible = "qcom,spmi-pmic-arb";
|
||
|
|
reg = <0xfc4cf000 0x1000 0xfc4cb000 0x1000 0xfc4ca000 0x1000>;
|
||
|
|
reg-names = "core\0intr\0cnfg";
|
||
|
|
interrupt-names = "periph_irq";
|
||
|
|
interrupts = <0x00 0xbe 0x04>;
|
||
|
|
qcom,ee = <0x00>;
|
||
|
|
qcom,channel = <0x00>;
|
||
|
|
#address-cells = <0x02>;
|
||
|
|
#size-cells = <0x00>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <0x04>;
|
||
|
|
phandle = <0x32>;
|
||
|
|
|
||
|
|
pmic@0 {
|
||
|
|
compatible = "qcom,pm8994\0qcom,spmi-pmic";
|
||
|
|
reg = <0x00 0x00>;
|
||
|
|
#address-cells = <0x01>;
|
||
|
|
#size-cells = <0x00>;
|
||
|
|
|
||
|
|
rtc@6000 {
|
||
|
|
compatible = "qcom,pm8941-rtc";
|
||
|
|
reg = <0x6000 0x6100>;
|
||
|
|
reg-names = "rtc\0alarm";
|
||
|
|
interrupts = <0x00 0x61 0x01 0x01>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pon@800 {
|
||
|
|
compatible = "qcom,pm8916-pon";
|
||
|
|
reg = <0x800>;
|
||
|
|
mode-bootloader = <0x02>;
|
||
|
|
mode-recovery = <0x01>;
|
||
|
|
|
||
|
|
pwrkey {
|
||
|
|
compatible = "qcom,pm8941-pwrkey";
|
||
|
|
interrupts = <0x00 0x08 0x00 0x03>;
|
||
|
|
debounce = <0x3d09>;
|
||
|
|
bias-pull-up;
|
||
|
|
linux,code = <0x74>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
gpios@c000 {
|
||
|
|
compatible = "qcom,pm8994-gpio";
|
||
|
|
reg = <0xc000>;
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <0x02>;
|
||
|
|
interrupts = <0x00 0xc0 0x00 0x00 0x00 0xc1 0x00 0x00 0x00 0xc2 0x00 0x00 0x00 0xc3 0x00 0x00 0x00 0xc4 0x00 0x00 0x00 0xc5 0x00 0x00 0x00 0xc6 0x00 0x00 0x00 0xc7 0x00 0x00 0x00 0xc8 0x00 0x00 0x00 0xc9 0x00 0x00 0x00 0xca 0x00 0x00 0x00 0xcb 0x00 0x00 0x00 0xcc 0x00 0x00 0x00 0xcd 0x00 0x00 0x00 0xce 0x00 0x00 0x00 0xcf 0x00 0x00 0x00 0xd0 0x00 0x00 0x00 0xd1 0x00 0x00 0x00 0xd2 0x00 0x00 0x00 0xd3 0x00 0x00 0x00 0xd4 0x00 0x00 0x00 0xd5 0x00 0x00>;
|
||
|
|
phandle = <0x33>;
|
||
|
|
};
|
||
|
|
|
||
|
|
mpps@a000 {
|
||
|
|
compatible = "qcom,pm8994-mpp";
|
||
|
|
reg = <0xa000>;
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <0x02>;
|
||
|
|
interrupts = <0x00 0xa0 0x00 0x00 0x00 0xa1 0x00 0x00 0x00 0xa2 0x00 0x00 0x00 0xa3 0x00 0x00 0x00 0xa4 0x00 0x00 0x00 0xa5 0x00 0x00 0x00 0xa6 0x00 0x00 0x00 0xa7 0x00 0x00>;
|
||
|
|
phandle = <0x34>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
pmic@1 {
|
||
|
|
compatible = "qcom,pm8994\0qcom,spmi-pmic";
|
||
|
|
reg = <0x01 0x00>;
|
||
|
|
#address-cells = <0x01>;
|
||
|
|
#size-cells = <0x00>;
|
||
|
|
|
||
|
|
regulators {
|
||
|
|
compatible = "qcom,pm8994-regulators";
|
||
|
|
phandle = <0x35>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
pmic@2 {
|
||
|
|
compatible = "qcom,pmi8994\0qcom,spmi-pmic";
|
||
|
|
reg = <0x02 0x00>;
|
||
|
|
#address-cells = <0x01>;
|
||
|
|
#size-cells = <0x00>;
|
||
|
|
|
||
|
|
gpios@c000 {
|
||
|
|
compatible = "qcom,pmi8994-gpio\0qcom,spmi-gpio";
|
||
|
|
reg = <0xc000>;
|
||
|
|
gpio-controller;
|
||
|
|
gpio-ranges = <0x26 0x00 0x00 0x0a>;
|
||
|
|
#gpio-cells = <0x02>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <0x02>;
|
||
|
|
phandle = <0x26>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
pmic@3 {
|
||
|
|
compatible = "qcom,pmi8994\0qcom,spmi-pmic";
|
||
|
|
reg = <0x03 0x00>;
|
||
|
|
#address-cells = <0x01>;
|
||
|
|
#size-cells = <0x00>;
|
||
|
|
|
||
|
|
regulators {
|
||
|
|
compatible = "qcom,pmi8994-regulators";
|
||
|
|
#address-cells = <0x01>;
|
||
|
|
#size-cells = <0x01>;
|
||
|
|
phandle = <0x36>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
syscon@fd484000 {
|
||
|
|
#address-cells = <0x01>;
|
||
|
|
#size-cells = <0x01>;
|
||
|
|
compatible = "syscon";
|
||
|
|
reg = <0xfd484000 0x400>;
|
||
|
|
phandle = <0x0a>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl@fd510000 {
|
||
|
|
compatible = "qcom,msm8994-pinctrl";
|
||
|
|
reg = <0xfd510000 0x4000>;
|
||
|
|
interrupts = <0x00 0xd0 0x04>;
|
||
|
|
gpio-controller;
|
||
|
|
gpio-ranges = <0x27 0x00 0x00 0x92>;
|
||
|
|
#gpio-cells = <0x02>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <0x02>;
|
||
|
|
phandle = <0x27>;
|
||
|
|
|
||
|
|
blsp1-uart2-default {
|
||
|
|
function = "blsp_uart2";
|
||
|
|
pins = "gpio4\0gpio5";
|
||
|
|
drive-strength = <0x10>;
|
||
|
|
bias-disable;
|
||
|
|
phandle = <0x18>;
|
||
|
|
};
|
||
|
|
|
||
|
|
blsp1-uart2-sleep {
|
||
|
|
function = "gpio";
|
||
|
|
pins = "gpio4\0gpio5";
|
||
|
|
drive-strength = <0x02>;
|
||
|
|
bias-pull-down;
|
||
|
|
phandle = <0x19>;
|
||
|
|
};
|
||
|
|
|
||
|
|
blsp2-uart2-default {
|
||
|
|
function = "blsp_uart8";
|
||
|
|
pins = "gpio45\0gpio46\0gpio47\0gpio48";
|
||
|
|
drive-strength = <0x10>;
|
||
|
|
bias-disable;
|
||
|
|
phandle = <0x20>;
|
||
|
|
};
|
||
|
|
|
||
|
|
blsp2-uart2-sleep {
|
||
|
|
function = "gpio";
|
||
|
|
pins = "gpio45\0gpio46\0gpio47\0gpio48";
|
||
|
|
drive-strength = <0x02>;
|
||
|
|
bias-pull-down;
|
||
|
|
phandle = <0x21>;
|
||
|
|
};
|
||
|
|
|
||
|
|
clk-on {
|
||
|
|
pins = "sdc1_clk";
|
||
|
|
bias-disable;
|
||
|
|
drive-strength = <0x06>;
|
||
|
|
phandle = <0x10>;
|
||
|
|
};
|
||
|
|
|
||
|
|
clk-off {
|
||
|
|
pins = "sdc1_clk";
|
||
|
|
bias-disable;
|
||
|
|
drive-strength = <0x02>;
|
||
|
|
phandle = <0x14>;
|
||
|
|
};
|
||
|
|
|
||
|
|
cmd-on {
|
||
|
|
pins = "sdc1_cmd";
|
||
|
|
bias-pull-up;
|
||
|
|
drive-strength = <0x06>;
|
||
|
|
phandle = <0x11>;
|
||
|
|
};
|
||
|
|
|
||
|
|
cmd-off {
|
||
|
|
pins = "sdc1_cmd";
|
||
|
|
bias-pull-up;
|
||
|
|
drive-strength = <0x02>;
|
||
|
|
phandle = <0x15>;
|
||
|
|
};
|
||
|
|
|
||
|
|
data-on {
|
||
|
|
pins = "sdc1_data";
|
||
|
|
bias-pull-up;
|
||
|
|
drive-strength = <0x06>;
|
||
|
|
phandle = <0x12>;
|
||
|
|
};
|
||
|
|
|
||
|
|
data-off {
|
||
|
|
pins = "sdc1_data";
|
||
|
|
bias-pull-up;
|
||
|
|
drive-strength = <0x02>;
|
||
|
|
phandle = <0x16>;
|
||
|
|
};
|
||
|
|
|
||
|
|
rclk-on {
|
||
|
|
pins = "sdc1_rclk";
|
||
|
|
bias-pull-down;
|
||
|
|
phandle = <0x13>;
|
||
|
|
};
|
||
|
|
|
||
|
|
rclk-off {
|
||
|
|
pins = "sdc1_rclk";
|
||
|
|
bias-pull-down;
|
||
|
|
phandle = <0x17>;
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c2-default {
|
||
|
|
function = "blsp_i2c2";
|
||
|
|
pins = "gpio6\0gpio7";
|
||
|
|
drive-strength = <0x02>;
|
||
|
|
bias-disable;
|
||
|
|
phandle = <0x1a>;
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c2-sleep {
|
||
|
|
function = "gpio";
|
||
|
|
pins = "gpio6\0gpio7";
|
||
|
|
drive-strength = <0x02>;
|
||
|
|
bias-disable;
|
||
|
|
phandle = <0x1b>;
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c5-default {
|
||
|
|
function = "blsp_i2c11";
|
||
|
|
pins = "gpio83\0gpio84";
|
||
|
|
drive-strength = <0x02>;
|
||
|
|
bias-disable;
|
||
|
|
phandle = <0x24>;
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c5-sleep {
|
||
|
|
function = "gpio";
|
||
|
|
pins = "gpio83\0gpio84";
|
||
|
|
drive-strength = <0x02>;
|
||
|
|
bias-disable;
|
||
|
|
phandle = <0x25>;
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c6-default {
|
||
|
|
function = "blsp_i2c6";
|
||
|
|
pins = "gpio28\0gpio27";
|
||
|
|
drive-strength = <0x02>;
|
||
|
|
bias-disable;
|
||
|
|
phandle = <0x1e>;
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c6-sleep {
|
||
|
|
function = "gpio";
|
||
|
|
pins = "gpio28\0gpio27";
|
||
|
|
drive-strength = <0x02>;
|
||
|
|
bias-disable;
|
||
|
|
phandle = <0x1f>;
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c7-default {
|
||
|
|
function = "blsp_i2c7";
|
||
|
|
pins = "gpio43\0gpio44";
|
||
|
|
drive-strength = <0x02>;
|
||
|
|
bias-disable;
|
||
|
|
phandle = <0x22>;
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c7-sleep {
|
||
|
|
function = "gpio";
|
||
|
|
pins = "gpio43\0gpio44";
|
||
|
|
drive-strength = <0x02>;
|
||
|
|
bias-disable;
|
||
|
|
phandle = <0x23>;
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c13-default {
|
||
|
|
function = "blsp_i2c5";
|
||
|
|
pins = "gpio23\0gpio24";
|
||
|
|
drive-strength = <0x02>;
|
||
|
|
bias-disable;
|
||
|
|
phandle = <0x1c>;
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c13-sleep {
|
||
|
|
function = "gpio";
|
||
|
|
pins = "gpio23\0gpio24";
|
||
|
|
drive-strength = <0x02>;
|
||
|
|
bias-disable;
|
||
|
|
phandle = <0x1d>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
smd {
|
||
|
|
compatible = "qcom,smd";
|
||
|
|
phandle = <0x37>;
|
||
|
|
|
||
|
|
rpm {
|
||
|
|
interrupts = <0x00 0xa8 0x01>;
|
||
|
|
qcom,ipc = <0x28 0x08 0x00>;
|
||
|
|
qcom,smd-edge = <0x0f>;
|
||
|
|
qcom,local-pid = <0x00>;
|
||
|
|
qcom,remote-pid = <0x06>;
|
||
|
|
|
||
|
|
rpm-requests {
|
||
|
|
compatible = "qcom,rpm-msm8994";
|
||
|
|
qcom,smd-channels = "rpm_requests";
|
||
|
|
phandle = <0x38>;
|
||
|
|
|
||
|
|
rpmcc {
|
||
|
|
compatible = "qcom,rpmcc-msm8992";
|
||
|
|
#clock-cells = <0x01>;
|
||
|
|
phandle = <0x39>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
timer {
|
||
|
|
compatible = "arm,armv8-timer";
|
||
|
|
interrupts = <0x01 0x02 0xf08 0x01 0x03 0xf08 0x01 0x04 0xf08 0x01 0x01 0xf08>;
|
||
|
|
};
|
||
|
|
|
||
|
|
vreg-vph-pwr {
|
||
|
|
compatible = "regulator-fixed";
|
||
|
|
status = "okay";
|
||
|
|
regulator-name = "vph-pwr";
|
||
|
|
regulator-min-microvolt = <0x36ee80>;
|
||
|
|
regulator-max-microvolt = <0x36ee80>;
|
||
|
|
regulator-always-on;
|
||
|
|
phandle = <0x3a>;
|
||
|
|
};
|
||
|
|
|
||
|
|
__symbols__ {
|
||
|
|
CPU0 = "/cpus/cpu@0";
|
||
|
|
L2_0 = "/cpus/cpu@0/l2-cache";
|
||
|
|
CPU1 = "/cpus/cpu@1";
|
||
|
|
CPU2 = "/cpus/cpu@2";
|
||
|
|
CPU3 = "/cpus/cpu@3";
|
||
|
|
CPU4 = "/cpus/cpu@100";
|
||
|
|
L2_1 = "/cpus/cpu@100/l2-cache";
|
||
|
|
CPU5 = "/cpus/cpu@101";
|
||
|
|
xo_board = "/clocks/xo_board";
|
||
|
|
sleep_clk = "/clocks/sleep_clk";
|
||
|
|
smem_region = "/reserved-memory/smem@6a00000";
|
||
|
|
sfpb_mutex = "/hwmutex";
|
||
|
|
intc = "/soc/interrupt-controller@f9000000";
|
||
|
|
apcs = "/soc/mailbox@f900d000";
|
||
|
|
sdhc_1 = "/soc/sdhci@f9824900";
|
||
|
|
blsp1_uart2 = "/soc/serial@f991e000";
|
||
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blsp_i2c2 = "/soc/i2c@f9924000";
|
||
|
|
blsp_i2c13 = "/soc/i2c@f9927000";
|
||
|
|
blsp_i2c6 = "/soc/i2c@f9928000";
|
||
|
|
blsp2_uart2 = "/soc/serial@f995e000";
|
||
|
|
blsp_i2c7 = "/soc/i2c@f9963000";
|
||
|
|
blsp_i2c5 = "/soc/i2c@f9967000";
|
||
|
|
gcc = "/soc/clock-controller@fc400000";
|
||
|
|
rpm_msg_ram = "/soc/memory@fc428000";
|
||
|
|
spmi_bus = "/soc/spmi@fc4c0000";
|
||
|
|
pm8994_gpios = "/soc/spmi@fc4c0000/pmic@0/gpios@c000";
|
||
|
|
pm8994_mpps = "/soc/spmi@fc4c0000/pmic@0/mpps@a000";
|
||
|
|
pm8994_spmi_regulators = "/soc/spmi@fc4c0000/pmic@1/regulators";
|
||
|
|
pmi8994_gpios = "/soc/spmi@fc4c0000/pmic@2/gpios@c000";
|
||
|
|
pmi8994_spmi_regulators = "/soc/spmi@fc4c0000/pmic@3/regulators";
|
||
|
|
sfpb_mutex_regs = "/soc/syscon@fd484000";
|
||
|
|
tlmm = "/soc/pinctrl@fd510000";
|
||
|
|
blsp1_uart2_default = "/soc/pinctrl@fd510000/blsp1-uart2-default";
|
||
|
|
blsp1_uart2_sleep = "/soc/pinctrl@fd510000/blsp1-uart2-sleep";
|
||
|
|
blsp2_uart2_default = "/soc/pinctrl@fd510000/blsp2-uart2-default";
|
||
|
|
blsp2_uart2_sleep = "/soc/pinctrl@fd510000/blsp2-uart2-sleep";
|
||
|
|
sdc1_clk_on = "/soc/pinctrl@fd510000/clk-on";
|
||
|
|
sdc1_clk_off = "/soc/pinctrl@fd510000/clk-off";
|
||
|
|
sdc1_cmd_on = "/soc/pinctrl@fd510000/cmd-on";
|
||
|
|
sdc1_cmd_off = "/soc/pinctrl@fd510000/cmd-off";
|
||
|
|
sdc1_data_on = "/soc/pinctrl@fd510000/data-on";
|
||
|
|
sdc1_data_off = "/soc/pinctrl@fd510000/data-off";
|
||
|
|
sdc1_rclk_on = "/soc/pinctrl@fd510000/rclk-on";
|
||
|
|
sdc1_rclk_off = "/soc/pinctrl@fd510000/rclk-off";
|
||
|
|
i2c2_default = "/soc/pinctrl@fd510000/i2c2-default";
|
||
|
|
i2c2_sleep = "/soc/pinctrl@fd510000/i2c2-sleep";
|
||
|
|
i2c5_default = "/soc/pinctrl@fd510000/i2c5-default";
|
||
|
|
i2c5_sleep = "/soc/pinctrl@fd510000/i2c5-sleep";
|
||
|
|
i2c6_default = "/soc/pinctrl@fd510000/i2c6-default";
|
||
|
|
i2c6_sleep = "/soc/pinctrl@fd510000/i2c6-sleep";
|
||
|
|
i2c7_default = "/soc/pinctrl@fd510000/i2c7-default";
|
||
|
|
i2c7_sleep = "/soc/pinctrl@fd510000/i2c7-sleep";
|
||
|
|
i2c13_default = "/soc/pinctrl@fd510000/i2c13-default";
|
||
|
|
i2c13_sleep = "/soc/pinctrl@fd510000/i2c13-sleep";
|
||
|
|
smd_rpm = "/smd";
|
||
|
|
rpm_requests = "/smd/rpm/rpm-requests";
|
||
|
|
rpmcc = "/smd/rpm/rpm-requests/rpmcc";
|
||
|
|
vreg_vph_pwr = "/vreg-vph-pwr";
|
||
|
|
};
|
||
|
|
};
|