215 lines
6.8 KiB
C
215 lines
6.8 KiB
C
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#ifndef PMU_PRIVATE_H
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#define PMU_PRIVATE_H
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#ifdef FEEDIRAM_MODE
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#define PMU_RAMRP_BASE (0x0000000c)
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#else
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#define PMU_RAMRP_BASE (0x00000000)
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#endif
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/** RAMRP usage.
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*
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* RAMRP is divided into four main regions.
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*
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* Region 1: RAMRP Host interface.
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* Start address: RAMRP base (0x60000000)
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* This region provides buffers for communication
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* between the PCIe host and the various subsystems.
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* The size of this region can grow as more functionality
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* is added.
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*
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* Region 2: PMU API
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* Start address: RAMRP base + sizeof(Region 0)
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* This region is used to implement the internal PMU API
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* for sleep management purposes.
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*
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* Region 3: PMU code/data
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* Start address: RAMRP base + sizeof(Region 1)
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* This region contains the rest of the PMU runtime
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* code and data including the vector table.
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*
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* Region 4: Stack
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* Start address: RAMRP end - 1K
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* This region provides the stack space for
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* Cortex M0+ and is placed at end of the RAMRP.
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*/
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/* RAMRP host interface.
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*
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* These buffers are mapped into one of the PCIe BAR after
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* the second stage boot.
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*/
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/* Host IF buffer sizes are compile time configurable. */
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#ifndef RAMRP_PMU_HOSTIF_BUF_SIZE_WORDS
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#define RAMRP_PMU_HOSTIF_BUF_SIZE_WORDS (10)
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#endif
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#ifndef RAMRP_WPAN_HOSTIF_BUF_SIZE_WORDS
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#define RAMRP_WPAN_HOSTIF_BUF_SIZE_WORDS (1)
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#endif
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#ifndef RAMRP_WLAN_HOSTIF_BUF_SIZE_WORDS
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#define RAMRP_WLAN_HOSTIF_BUF_SIZE_WORDS (1)
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#endif
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/* Mailbox buffers between host and device for request/response
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* exchange.
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*/
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typedef struct {
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uint32_t from_host;
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uint32_t to_host;
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} __attribute__((packed, aligned(4))) ramrp_mbox_t;
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/* Host I/F buffers in RAMRP */
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typedef struct {
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uint32_t pmu_hif[RAMRP_PMU_HOSTIF_BUF_SIZE_WORDS];
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uint32_t wpan_hif[RAMRP_WPAN_HOSTIF_BUF_SIZE_WORDS];
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uint32_t wlan_hif[RAMRP_WLAN_HOSTIF_BUF_SIZE_WORDS];
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} __attribute__((packed, aligned(4))) ramrp_hostif_buf_t;
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typedef struct {
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ramrp_mbox_t pmu_mbox;
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ramrp_mbox_t wlan_mbox;
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ramrp_mbox_t wpan_mbox;
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ramrp_hostif_buf_t rhif_buf;
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} __attribute__((packed, aligned(4))) ramrp_hostif_t;
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#define RAMRP_HOSTIF_SIZE (sizeof(ramrp_hostif_t))
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#define RAMRP_HOSTIF_OFFSET(ofs) \
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((PMU_RAMRP_BASE + (offsetof(ramrp_hostif_t, ofs))))
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#define RAMRP_HOSTIF_PMU_MBOX_FROM_HOST_PTR \
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RAMRP_HOSTIF_OFFSET(pmu_mbox.from_host)
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#define RAMRP_HOSTIF_WLAN_MBOX_FROM_HOST_PTR \
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RAMRP_HOSTIF_OFFSET(wlan_mbox.from_host)
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#define RAMRP_HOSTIF_WPAN_MBOX_FROM_HOST_PTR \
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RAMRP_HOSTIF_OFFSET(wpan_mbox.from_host)
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#define RAMRP_HOSTIF_PMU_MBOX_TO_HOST_PTR RAMRP_HOSTIF_OFFSET(pmu_mbox.to_host)
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#define RAMRP_HOSTIF_WLAN_MBOX_TO_HOST_PTR \
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RAMRP_HOSTIF_OFFSET(wlan_mbox.to_host)
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#define RAMRP_HOSTIF_WPAN_MBOX_TO_HOST_PTR \
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RAMRP_HOSTIF_OFFSET(wpan_mbox.to_host)
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#define RAMRP_HOSTIF_PMU_BUF_PTR RAMRP_HOSTIF_OFFSET(rhif_buf.pmu_hif[0])
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#define RAMRP_HOSTIF_WPAN_BUF_PTR RAMRP_HOSTIF_OFFSET(rhif_buf.wpan_hif[0])
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#define RAMRP_HOSTIF_WLAN_BUF_PTR RAMRP_HOSTIF_OFFSET(rhif_buf.wlan_hif[0])
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/* 32 different interrupts can be supported
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* from host to PMU.
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*
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* Add any new PMU interrupts from host here.
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*/
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typedef enum {
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PMU_INT_FROM_HOST_SS_BOOT_START_MASK = 0x00000001,
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PMU_INT_FROM_HOST_MBOX_REQ_MASK = 0x00000002,
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PMU_INT_FROM_HOST_MAX_MASK
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} pmu_int_from_host_mask_t;
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/* Second Stage boot status sent back to PMU
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* via rhif.pmu_mbox.to_host
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*/
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typedef enum {
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PMU_SS_BOOT_STATUS_SUCCESS = 0x0,
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PMU_SS_BOOT_STATUS_FAILURE
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} pmu_ss_boot_status_t;
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/* Host requests sent in the PMU MBOX
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* along with PMU_INT_FROM_HOST_MBOX_REQ
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*/
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typedef enum {
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PMU_HOSTIF_MBOX_REQ_NULL = 0x0,
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PMU_HOSTIF_MBOX_REQ_START_WLAN,
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PMU_HOSTIF_MBOX_REQ_START_WPAN,
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PMU_HOSTIF_MBOX_REQ_START_WLAN_WPAN,
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PMU_HOSTIF_MBOX_REQ_RESET_WLAN,
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PMU_HOSTIF_MBOX_REQ_RESET_WPAN,
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PMU_HOSTIF_MBOX_REQ_PCIE_ATU_CONFIG,
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PMU_HOSTIF_MBOX_REQ_MAX
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} pmu_hostif_mbox_req_t;
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typedef enum {
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PMU_HOSTIF_MBOX_RESPONSE_SUCCESS = 0x0,
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PMU_HOSTIF_MBOX_RESPONSE_FAILURE
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} pmu_hostif_mbox_resp_t;
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/* PMU API: Internal interface for communication between subsystems
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* and PMU for sleep management purposes.
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*/
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typedef enum { PMU_NONE = 0, PMU_READY, PMU_START } pmu_ctrl_t;
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typedef struct {
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uint8_t pmu_wl_ctrl_req;
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uint8_t pmu_wl_ctrl_param1;
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uint8_t pmu_wl_ctrl_param2;
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uint8_t pmu_wl_ctrl_param3;
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uint32_t pmu_wl_wakeup_time_us;
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uint8_t pmu_wl_status;
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uint8_t pmu_wl_boot_ct;
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uint8_t pmu_wp_ctrl_req;
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uint8_t pmu_wp_ctrl_param1;
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uint8_t pmu_wp_ctrl_param2;
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uint8_t pmu_wp_ctrl_param3;
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uint32_t pmu_wp_wakeup_time_us;
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uint8_t pmu_wp_status;
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uint8_t pmu_wp_boot_ct;
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uint8_t pmu_ctrl_status;
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uint8_t pmu_wake_flags;
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uint8_t pmu_wake_cause0;
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uint8_t pmu_wake_cause1;
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uint32_t pmu_wl_scratch[5];
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uint32_t pmu_wp_scratch[5];
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} __attribute__((packed, aligned(4))) pmu_data_t;
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#define KRAM(ofs) \
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(*(volatile uint8_t *)(PMU_RAMRP_BASE + RAMRP_HOSTIF_SIZE + \
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(offsetof(pmu_data_t, ofs))))
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#define PMU_DATA_PTR ((volatile uint8_t *)(PMU_RAMRP_BASE + RAMRP_HOSTIF_SIZE))
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#define PMU_WL_CONTROL_REQUEST KRAM(pmu_wl_ctrl_req)
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#define PMU_WL_CONTROL_PARAM1 KRAM(pmu_wl_ctrl_param1)
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#define PMU_WL_CONTROL_PARAM2 KRAM(pmu_wl_ctrl_param2)
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#define PMU_WL_CONTROL_PARAM3 KRAM(pmu_wl_ctrl_param3)
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#define PMU_WL_WAKEUP_TIME_0_7 KRAM(pmu_wl_wakeup_time_0_7)
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#define PMU_WL_WAKEUP_TIME_8_15 KRAM(pmu_wl_wakeup_time_8_15)
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#define PMU_WL_WAKEUP_TIME_16_23 KRAM(pmu_wl_wakeup_time_16_23)
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#define PMU_WL_WAKEUP_TIME_24_31 KRAM(pmu_wl_wakeup_time_24_31)
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#define PMU_WL_STATUS KRAM(pmu_wl_status)
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#define PMU_WP_CONTROL_REQUEST KRAM(pmu_wp_ctrl_req)
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#define PMU_WP_CONTROL_PARAM1 KRAM(pmu_wp_ctrl_param1)
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#define PMU_WP_CONTROL_PARAM2 KRAM(pmu_wp_ctrl_param2)
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#define PMU_WP_CONTROL_PARAM3 KRAM(pmu_wp_ctrl_param3)
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#define PMU_WP_WAKEUP_TIME_0_7 KRAM(pmu_wp_wakeup_time_0_7)
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#define PMU_WP_WAKEUP_TIME_8_15 KRAM(pmu_wp_wakeup_time_8_15)
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#define PMU_WP_WAKEUP_TIME_16_23 KRAM(pmu_wp_wakeup_time_16_23)
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#define PMU_WP_WAKEUP_TIME_24_31 KRAM(pmu_wp_wakeup_time_24_31)
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#define PMU_WP_STATUS KRAM(pmu_wp_status)
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#define PMU_CONTROL_STATUS KRAM(pmu_ctrl_status)
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#define PMU_WAKE_FLAGS KRAM(pmu_wake_flags)
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#define PMU_WAKE_CAUSE0 KRAM(pmu_wake_cause0)
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#define PMU_WAKE_CAUSE1 KRAM(pmu_wake_cause1)
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#define PMU_ENTER_DEEP_SLEEP (0x1)
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#define PMU_CANCEL_DEEP_SLEEP (0x2)
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#define PMU_PIO_INT_REQ (0x3)
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#define PMU_PIO_INT_ACK (0x4)
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#define PMU_PING (0x5)
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#define PMU_SET_UART_STATIC (0x6)
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#define PMU_MIF_REQ (0x7)
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/* Wakeup enables */
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typedef enum {
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DEEP_SLEEP_WAKEUP_TIMER_MASK = 0x0001,
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DEEP_SLEEP_WAKEUP_MAX_MASK
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} deep_sleep_wakeups_t;
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typedef struct {
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uint64_t start_addr_0;
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uint64_t end_addr_0;
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uint64_t start_addr_1;
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uint64_t end_addr_1;
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} pcie_atu_config_t;
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#endif /* PMU_PRIVATE_H */
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