305 lines
8.1 KiB
C
305 lines
8.1 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2020 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Samsung S6E3FAB Panel driver.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/of_platform.h>
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#include <linux/module.h>
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#include "panel-samsung-drv.h"
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static unsigned char SEQ_PPS_SLICE[] = {
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/* 1080x2400, Slice Info : 540x120 */
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0x11, 0x00, 0x00, 0x89, 0x30, 0x80, 0x09, 0x60,
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0x04, 0x38, 0x00, 0x78, 0x02, 0x1C, 0x02, 0x1C,
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0x02, 0x00, 0x02, 0x0E, 0x00, 0x20, 0x0B, 0xAF,
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0x00, 0x07, 0x00, 0x0C, 0x00, 0xCF, 0x00, 0xD9,
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0x18, 0x00, 0x10, 0xF0, 0x03, 0x0C, 0x20, 0x00,
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0x06, 0x0B, 0x0B, 0x33, 0x0E, 0x1C, 0x2A, 0x38,
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0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7B,
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0x7D, 0x7E, 0x01, 0x02, 0x01, 0x00, 0x09, 0x40,
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0x09, 0xBE, 0x19, 0xFC, 0x19, 0xFA, 0x19, 0xF8,
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0x1A, 0x38, 0x1A, 0x78, 0x1A, 0xB6, 0x2A, 0xF6,
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0x2B, 0x34, 0x2B, 0x74, 0x3B, 0x74, 0x6B, 0xF4
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};
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static int s6e3fab_disable(struct drm_panel *panel)
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{
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struct exynos_panel *ctx;
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ctx = container_of(panel, struct exynos_panel, panel);
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ctx->enabled = false;
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panel_info(ctx, "+\n");
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return 0;
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}
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static int s6e3fab_unprepare(struct drm_panel *panel)
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{
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struct exynos_panel *ctx;
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ctx = container_of(panel, struct exynos_panel, panel);
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panel_info(ctx, "+\n");
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exynos_panel_set_power(ctx, false);
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panel_info(ctx, "-\n");
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return 0;
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}
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static int s6e3fab_prepare(struct drm_panel *panel)
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{
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struct exynos_panel *ctx;
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ctx = container_of(panel, struct exynos_panel, panel);
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panel_info(ctx, "+\n");
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exynos_panel_set_power(ctx, true);
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panel_info(ctx, "-\n");
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return 0;
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}
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static int s6e3fab_set_brightness(struct exynos_panel *exynos_panel, u16 br)
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{
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u16 brightness;
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brightness = (br & 0xff) << 8 | br >> 8;
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return exynos_dcs_set_brightness(exynos_panel, brightness);
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}
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static void s6e3fab_set_vrefresh(struct exynos_panel *ctx,
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const struct drm_display_mode *pmode)
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{
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int vrefresh = drm_mode_vrefresh(pmode);
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panel_info(ctx, "+\n");
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EXYNOS_DCS_WRITE_SEQ(ctx, 0xF0, 0x5A, 0x5A);
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#if defined(CONFIG_EXYNOS_CMD_SVSYNC)
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if (vrefresh == 120) {
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/* TE start timing is advanced by about 3msec due to SV-Sync
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* default value : 2399(active line) + 15(vbp+1) - 2 = 0x96C
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* modified value : default value - 900(modifying line) = 0x5E8
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*/
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EXYNOS_DCS_WRITE_SEQ(ctx, 0xB9, 0x01, 0x50, 0xE8, 0x09);
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} else {
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/* TE start timing is advanced by about 3msec due to SV-Sync
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* default value : 2399(active line) + 15(vbp+1) - 2 = 0x96C
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* modified value : default value - 450(modifying line) = 0x7AA
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*/
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EXYNOS_DCS_WRITE_SEQ(ctx, 0xB9, 0x01, 0x70, 0xAA, 0x09);
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}
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#endif
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if (vrefresh == 60) {
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EXYNOS_DCS_WRITE_SEQ(ctx, 0x9F, 0xA5, 0xA5);
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EXYNOS_DCS_WRITE_SEQ(ctx, 0x60, 0x00);
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EXYNOS_DCS_WRITE_SEQ(ctx, 0x9F, 0x5A, 0x5A);
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} else if (vrefresh == 120) {
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EXYNOS_DCS_WRITE_SEQ(ctx, 0x9F, 0xA5, 0xA5);
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EXYNOS_DCS_WRITE_SEQ(ctx, 0x60, 0x20);
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EXYNOS_DCS_WRITE_SEQ(ctx, 0x9F, 0x5A, 0x5A);
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} else if (vrefresh == 30) {
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// lp mode
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} else {
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panel_err(ctx, "not supported fps(%d)\n", vrefresh);
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goto end;
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}
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/* Panelupdate : gamma set, ltps set, transition control update */
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EXYNOS_DCS_WRITE_SEQ(ctx, 0xF7, 0x0F);
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end:
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EXYNOS_DCS_WRITE_SEQ(ctx, 0xF0, 0xA5, 0xA5);
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panel_info(ctx, "-\n");
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}
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static void s6e3fab_mode_set(struct exynos_panel *ctx,
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const struct exynos_panel_mode *pmode, unsigned int flags)
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{
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panel_info(ctx, "+\n");
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if (!ctx->enabled)
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return;
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if (SEAMLESS_MODESET_VREF & flags)
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s6e3fab_set_vrefresh(ctx, &pmode->mode);
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panel_info(ctx, "-\n");
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}
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static void s6e3fab_lp_mode_set(struct exynos_panel *ctx,
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const struct exynos_panel_mode *pmode)
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{
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if (!ctx->enabled)
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return;
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panel_info(ctx, "enter %dhz LP mode\n", drm_mode_vrefresh(&pmode->mode));
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}
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static int s6e3fab_enable(struct drm_panel *panel)
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{
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struct exynos_panel *ctx = container_of(panel, struct exynos_panel, panel);
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const struct exynos_panel_mode *pmode = ctx->current_mode;
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panel_info(ctx, "+\n");
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if (!pmode) {
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panel_err(ctx, "no current mode set\n");
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return -EINVAL;
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}
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exynos_panel_reset(ctx);
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/* DSC related configuration */
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exynos_dcs_compression_mode(ctx, true);
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EXYNOS_PPS_LONG_WRITE_TABLE(ctx, SEQ_PPS_SLICE);
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/* sleep out: 200ms delay */
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EXYNOS_DCS_WRITE_SEQ_DELAY(ctx, 10, 0x11);
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EXYNOS_DCS_WRITE_SEQ(ctx, 0xf0, 0x5a, 0x5a);
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EXYNOS_DCS_WRITE_SEQ(ctx, 0xfc, 0x5a, 0x5a);
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/* CASET */
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EXYNOS_DCS_WRITE_SEQ(ctx, 0x2a, 0x00, 0x00, 0x04, 0x37);
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/* PASET */
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EXYNOS_DCS_WRITE_SEQ(ctx, 0x2b, 0x00, 0x00, 0x09, 0x5f);
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/* ESD flag: [2]=VLIN3, [6]=VLIN1 error check*/
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EXYNOS_DCS_WRITE_SEQ(ctx, 0xED, 0x04, 0x40, 0x20);
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/* FAB_FFC_1362 */
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EXYNOS_DCS_WRITE_SEQ(ctx, 0xC5, 0x09, 0x10, 0x68, 0x22, 0x02, 0x22, 0x02);
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/* enable brightness control */
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EXYNOS_DCS_WRITE_SEQ(ctx, 0x53, 0x28);
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/* ACL on */
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EXYNOS_DCS_WRITE_SEQ(ctx, 0x55, 0x01);
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/* Default brightness aor40% */
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EXYNOS_DCS_WRITE_SEQ(ctx, 0x51, 0x02, 0xED);
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/* Panelupdate : gamma set, ltps set, transition control update */
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EXYNOS_DCS_WRITE_SEQ(ctx, 0xF7, 0x0F);
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/* TE on */
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EXYNOS_DCS_WRITE_SEQ(ctx, 0x35);
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/* TSP HSYNC */
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EXYNOS_DCS_WRITE_SEQ(ctx, 0xB9, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00,
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0x00, 0x11, 0x03);
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/* vrefresh rate configuration */
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s6e3fab_set_vrefresh(ctx, &pmode->mode);
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EXYNOS_DCS_WRITE_SEQ(ctx, 0xf0, 0xa5, 0xa5);
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EXYNOS_DCS_WRITE_SEQ(ctx, 0xfc, 0xa5, 0xa5);
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/* display on */
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EXYNOS_DCS_WRITE_SEQ(ctx, 0x9F, 0xA5, 0xA5);
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EXYNOS_DCS_WRITE_SEQ(ctx, 0x29);
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EXYNOS_DCS_WRITE_SEQ(ctx, 0x9F, 0x5A, 0x5A);
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ctx->enabled = true;
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if (pmode->exynos_mode.is_lp_mode)
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s6e3fab_lp_mode_set(ctx, pmode);
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panel_info(ctx, "-\n");
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return 0;
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}
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/* drm_display_mode
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*
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* @clock: vtotal * htotal * fps / 1000
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* @hdisplay = horizon resolution
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* @hsync_start = hdisplay + hfp
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* @hsync_end = hdisplay + hfp + hsa
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* @htotal = hdisplay + hfp + hsa + hbp
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* @vdisplay = vertical resolution,
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* @vsync_start = vdisplay + vfp
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* @vsync_end = vdisplay + vfp + vsa
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* @vtotal = vdisplay + vfp + vsa + + vbp
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*/
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static const struct exynos_panel_mode s6e3fab_mode[] = {
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{
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.mode = { DRM_MODE("1080x2400@60", DRM_MODE_TYPE_DRIVER, 157057,
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1080, 1081, 1082, 1083, 0, 2400, 2415, 2416,
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2417, 0, 0) },
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.exynos_mode = { EXYNOS_MODE(MIPI_DSI_CLOCK_NON_CONTINUOUS,
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8, false, true, 2, 2, 120)},
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},
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{
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.mode = { DRM_MODE("1080x2400@120", DRM_MODE_TYPE_DRIVER, 314113,
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1080, 1081, 1082, 1083, 0, 2400, 2415, 2416,
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2417, 0, 0) },
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.exynos_mode = { EXYNOS_MODE(MIPI_DSI_CLOCK_NON_CONTINUOUS,
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8, false, true, 2, 2, 120)},
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}
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};
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static const struct exynos_panel_mode s6e3fab_lp_mode[] = {
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{
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.mode = { DRM_MODE("1080x2400@30", DRM_MODE_TYPE_DRIVER, 78528,
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1080, 1081, 1082, 1083, 0, 2400, 2415, 2416,
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2417, 0, 0) },
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.exynos_mode = { EXYNOS_MODE(MIPI_DSI_CLOCK_NON_CONTINUOUS,
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8, true, true, 2, 2, 120)},
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},
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};
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static const struct drm_panel_funcs s6e3fab_drm_funcs = {
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.disable = s6e3fab_disable,
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.unprepare = s6e3fab_unprepare,
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.prepare = s6e3fab_prepare,
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.enable = s6e3fab_enable,
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.get_modes = exynos_panel_get_modes,
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};
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static const struct exynos_panel_funcs s6e3fab_exynos_funcs = {
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.set_brightness = s6e3fab_set_brightness,
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.set_lp_mode = s6e3fab_lp_mode_set,
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.mode_set = s6e3fab_mode_set,
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};
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const struct exynos_panel_desc samsung_s6e3fab = {
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.data_lane_cnt = 4,
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.max_brightness = 1023, /* TODO check */
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.dft_brightness = 511, /* TODO check */
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.modes = s6e3fab_mode,
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.num_modes = ARRAY_SIZE(s6e3fab_mode),
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.lp_modes = s6e3fab_lp_mode,
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.num_lp_modes = ARRAY_SIZE(s6e3fab_lp_mode),
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.panel_func = &s6e3fab_drm_funcs,
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.exynos_panel_func = &s6e3fab_exynos_funcs,
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};
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static const struct of_device_id exynos_panel_of_match[] = {
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{ .compatible = "samsung,s6e3fab", .data = &samsung_s6e3fab },
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{ }
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};
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MODULE_DEVICE_TABLE(of, exynos_panel_of_match);
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static struct mipi_dsi_driver exynos_panel_driver = {
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.probe = exynos_panel_probe,
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.remove = exynos_panel_remove,
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.driver = {
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.name = "panel-samsung-s6e3fab",
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.of_match_table = exynos_panel_of_match,
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},
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};
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module_mipi_dsi_driver(exynos_panel_driver);
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MODULE_AUTHOR("Wonyoeng choi <won0.choi@samsung.com>");
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MODULE_DESCRIPTION("MIPI-DSI based Samsung s6e3fab panel driver");
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MODULE_LICENSE("GPL");
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