1416 lines
220 KiB
C
1416 lines
220 KiB
C
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#include "../../cmucal.h"
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#include "cmucal-sfr.h"
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#include "cmucal-qch.h"
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unsigned int cmucal_qch_size = 1354;
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struct cmucal_qch cmucal_qch_list[] = {
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CLK_QCH(ALIVE_CMU_ALIVE_QCH, QCH_CON_ALIVE_CMU_ALIVE_QCH_ENABLE, QCH_CON_ALIVE_CMU_ALIVE_QCH_CLOCK_REQ, QCH_CON_ALIVE_CMU_ALIVE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(APBIF_GPIO_ALIVE_QCH, QCH_CON_APBIF_GPIO_ALIVE_QCH_ENABLE, QCH_CON_APBIF_GPIO_ALIVE_QCH_CLOCK_REQ, QCH_CON_APBIF_GPIO_ALIVE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(APBIF_INTCOMB_VGPIO2AP_QCH, QCH_CON_APBIF_INTCOMB_VGPIO2AP_QCH_ENABLE, QCH_CON_APBIF_INTCOMB_VGPIO2AP_QCH_CLOCK_REQ, QCH_CON_APBIF_INTCOMB_VGPIO2AP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(APBIF_INTCOMB_VGPIO2APM_QCH, QCH_CON_APBIF_INTCOMB_VGPIO2APM_QCH_ENABLE, QCH_CON_APBIF_INTCOMB_VGPIO2APM_QCH_CLOCK_REQ, QCH_CON_APBIF_INTCOMB_VGPIO2APM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(APBIF_INTCOMB_VGPIO2PMU_QCH, QCH_CON_APBIF_INTCOMB_VGPIO2PMU_QCH_ENABLE, QCH_CON_APBIF_INTCOMB_VGPIO2PMU_QCH_CLOCK_REQ, QCH_CON_APBIF_INTCOMB_VGPIO2PMU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(APBIF_PMU_ALIVE_QCH, QCH_CON_APBIF_PMU_ALIVE_QCH_ENABLE, QCH_CON_APBIF_PMU_ALIVE_QCH_CLOCK_REQ, QCH_CON_APBIF_PMU_ALIVE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(APM_DMA_QCH_APB, QCH_CON_APM_DMA_QCH_APB_ENABLE, QCH_CON_APM_DMA_QCH_APB_CLOCK_REQ, QCH_CON_APM_DMA_QCH_APB_IGNORE_FORCE_PM_EN),
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CLK_QCH(CHUB_RTC_QCH, QCH_CON_CHUB_RTC_QCH_ENABLE, QCH_CON_CHUB_RTC_QCH_CLOCK_REQ, QCH_CON_CHUB_RTC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CLKMON_QCH, QCH_CON_CLKMON_QCH_ENABLE, QCH_CON_CLKMON_QCH_CLOCK_REQ, QCH_CON_CLKMON_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DBGCORE_UART_QCH, QCH_CON_DBGCORE_UART_QCH_ENABLE, QCH_CON_DBGCORE_UART_QCH_CLOCK_REQ, QCH_CON_DBGCORE_UART_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(DTZPC_ALIVE_QCH, QCH_CON_DTZPC_ALIVE_QCH_ENABLE, QCH_CON_DTZPC_ALIVE_QCH_CLOCK_REQ, QCH_CON_DTZPC_ALIVE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(GREBEINTEGRATION_QCH_GREBE, QCH_CON_GREBEINTEGRATION_QCH_GREBE_ENABLE, QCH_CON_GREBEINTEGRATION_QCH_GREBE_CLOCK_REQ, QCH_CON_GREBEINTEGRATION_QCH_GREBE_IGNORE_FORCE_PM_EN),
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CLK_QCH(GREBEINTEGRATION_QCH_DBG, QCH_CON_GREBEINTEGRATION_QCH_DBG_ENABLE, QCH_CON_GREBEINTEGRATION_QCH_DBG_CLOCK_REQ, QCH_CON_GREBEINTEGRATION_QCH_DBG_IGNORE_FORCE_PM_EN),
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CLK_QCH(HW_SCANDUMP_CLKSTOP_CTRL_QCH, QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH_ENABLE, QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH_CLOCK_REQ, QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(INTMEM_QCH, QCH_CON_INTMEM_QCH_ENABLE, QCH_CON_INTMEM_QCH_CLOCK_REQ, QCH_CON_INTMEM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_SI_D_APM_QCH, QCH_CON_LH_AXI_SI_D_APM_QCH_ENABLE, QCH_CON_LH_AXI_SI_D_APM_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D_APM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_APM_AP_QCH, QCH_CON_MAILBOX_APM_AP_QCH_ENABLE, QCH_CON_MAILBOX_APM_AP_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM_AP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_APM_AUD_QCH, QCH_CON_MAILBOX_APM_AUD_QCH_ENABLE, QCH_CON_MAILBOX_APM_AUD_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM_AUD_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_APM_CHUB_QCH, QCH_CON_MAILBOX_APM_CHUB_QCH_ENABLE, QCH_CON_MAILBOX_APM_CHUB_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_APM_CP_QCH, QCH_CON_MAILBOX_APM_CP_QCH_ENABLE, QCH_CON_MAILBOX_APM_CP_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM_CP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_APM_CP_1_QCH, QCH_CON_MAILBOX_APM_CP_1_QCH_ENABLE, QCH_CON_MAILBOX_APM_CP_1_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM_CP_1_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_APM_GNSS_QCH, QCH_CON_MAILBOX_APM_GNSS_QCH_ENABLE, QCH_CON_MAILBOX_APM_GNSS_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM_GNSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_APM_VTS_QCH, QCH_CON_MAILBOX_APM_VTS_QCH_ENABLE, QCH_CON_MAILBOX_APM_VTS_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM_VTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_AP_CHUB_QCH, QCH_CON_MAILBOX_AP_CHUB_QCH_ENABLE, QCH_CON_MAILBOX_AP_CHUB_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_AP_CP_QCH, QCH_CON_MAILBOX_AP_CP_QCH_ENABLE, QCH_CON_MAILBOX_AP_CP_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP_CP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_AP_CP_S_QCH, QCH_CON_MAILBOX_AP_CP_S_QCH_ENABLE, QCH_CON_MAILBOX_AP_CP_S_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP_CP_S_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_AP_DBGCORE_QCH, QCH_CON_MAILBOX_AP_DBGCORE_QCH_ENABLE, QCH_CON_MAILBOX_AP_DBGCORE_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP_DBGCORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_AP_GNSS_QCH, QCH_CON_MAILBOX_AP_GNSS_QCH_ENABLE, QCH_CON_MAILBOX_AP_GNSS_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP_GNSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_CP_CHUB_QCH, QCH_CON_MAILBOX_CP_CHUB_QCH_ENABLE, QCH_CON_MAILBOX_CP_CHUB_QCH_CLOCK_REQ, QCH_CON_MAILBOX_CP_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_CP_GNSS_QCH, QCH_CON_MAILBOX_CP_GNSS_QCH_ENABLE, QCH_CON_MAILBOX_CP_GNSS_QCH_CLOCK_REQ, QCH_CON_MAILBOX_CP_GNSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_GNSS_CHUB_QCH, QCH_CON_MAILBOX_GNSS_CHUB_QCH_ENABLE, QCH_CON_MAILBOX_GNSS_CHUB_QCH_CLOCK_REQ, QCH_CON_MAILBOX_GNSS_CHUB_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MAILBOX_SHARED_SRAM_QCH, QCH_CON_MAILBOX_SHARED_SRAM_QCH_ENABLE, QCH_CON_MAILBOX_SHARED_SRAM_QCH_CLOCK_REQ, QCH_CON_MAILBOX_SHARED_SRAM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(MCT_ALIVE_QCH, QCH_CON_MCT_ALIVE_QCH_ENABLE, QCH_CON_MCT_ALIVE_QCH_CLOCK_REQ, QCH_CON_MCT_ALIVE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(PMU_QCH_PMU, QCH_CON_PMU_QCH_PMU_ENABLE, QCH_CON_PMU_QCH_PMU_CLOCK_REQ, QCH_CON_PMU_QCH_PMU_IGNORE_FORCE_PM_EN),
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CLK_QCH(PMU_QCH_PMLINK, QCH_CON_PMU_QCH_PMLINK_ENABLE, QCH_CON_PMU_QCH_PMLINK_CLOCK_REQ, QCH_CON_PMU_QCH_PMLINK_IGNORE_FORCE_PM_EN),
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CLK_QCH(PMU_INTR_GEN_QCH, QCH_CON_PMU_INTR_GEN_QCH_ENABLE, QCH_CON_PMU_INTR_GEN_QCH_CLOCK_REQ, QCH_CON_PMU_INTR_GEN_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RSTNSYNC_CLK_ALIVE_GREBE_QCH, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(RTC_QCH, QCH_CON_RTC_QCH_ENABLE, QCH_CON_RTC_QCH_CLOCK_REQ, QCH_CON_RTC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_ID_DBGCORE_QCH, QCH_CON_SLH_AXI_MI_ID_DBGCORE_QCH_ENABLE, QCH_CON_SLH_AXI_MI_ID_DBGCORE_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_ID_DBGCORE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_LD_CHUBVTS_QCH, QCH_CON_SLH_AXI_MI_LD_CHUBVTS_QCH_ENABLE, QCH_CON_SLH_AXI_MI_LD_CHUBVTS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_LD_CHUBVTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_LD_GNSS_QCH, QCH_CON_SLH_AXI_MI_LD_GNSS_QCH_ENABLE, QCH_CON_SLH_AXI_MI_LD_GNSS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_LD_GNSS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_LP_MODEM_QCH, QCH_CON_SLH_AXI_MI_LP_MODEM_QCH_ENABLE, QCH_CON_SLH_AXI_MI_LP_MODEM_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_LP_MODEM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_MI_P_APM_QCH, QCH_CON_SLH_AXI_MI_P_APM_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_APM_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_APM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_IP_APM_QCH, QCH_CON_SLH_AXI_SI_IP_APM_QCH_ENABLE, QCH_CON_SLH_AXI_SI_IP_APM_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_IP_APM_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_LP_ALIVEDNC_QCH, QCH_CON_SLH_AXI_SI_LP_ALIVEDNC_QCH_ENABLE, QCH_CON_SLH_AXI_SI_LP_ALIVEDNC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_LP_ALIVEDNC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_LP_CHUBVTS_QCH, QCH_CON_SLH_AXI_SI_LP_CHUBVTS_QCH_ENABLE, QCH_CON_SLH_AXI_SI_LP_CHUBVTS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_LP_CHUBVTS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_LP_CMGP_QCH, QCH_CON_SLH_AXI_SI_LP_CMGP_QCH_ENABLE, QCH_CON_SLH_AXI_SI_LP_CMGP_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_LP_CMGP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SLH_AXI_SI_LP_PPU_QCH, QCH_CON_SLH_AXI_SI_LP_PPU_QCH_ENABLE, QCH_CON_SLH_AXI_SI_LP_PPU_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_LP_PPU_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SPC_ALIVE_QCH, QCH_CON_SPC_ALIVE_QCH_ENABLE, QCH_CON_SPC_ALIVE_QCH_CLOCK_REQ, QCH_CON_SPC_ALIVE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SPMI_MASTER_PMIC_QCH_P, QCH_CON_SPMI_MASTER_PMIC_QCH_P_ENABLE, QCH_CON_SPMI_MASTER_PMIC_QCH_P_CLOCK_REQ, QCH_CON_SPMI_MASTER_PMIC_QCH_P_IGNORE_FORCE_PM_EN),
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CLK_QCH(SPMI_MASTER_PMIC_QCH_S, QCH_CON_SPMI_MASTER_PMIC_QCH_S_ENABLE, QCH_CON_SPMI_MASTER_PMIC_QCH_S_CLOCK_REQ, QCH_CON_SPMI_MASTER_PMIC_QCH_S_IGNORE_FORCE_PM_EN),
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CLK_QCH(SWEEPER_P_ALIVE_QCH, QCH_CON_SWEEPER_P_ALIVE_QCH_ENABLE, QCH_CON_SWEEPER_P_ALIVE_QCH_CLOCK_REQ, QCH_CON_SWEEPER_P_ALIVE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(SYSREG_ALIVE_QCH, QCH_CON_SYSREG_ALIVE_QCH_ENABLE, QCH_CON_SYSREG_ALIVE_QCH_CLOCK_REQ, QCH_CON_SYSREG_ALIVE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(TOP_RTC_QCH, QCH_CON_TOP_RTC_QCH_ENABLE, QCH_CON_TOP_RTC_QCH_CLOCK_REQ, QCH_CON_TOP_RTC_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(VGEN_LITE_ALIVE_QCH, QCH_CON_VGEN_LITE_ALIVE_QCH_ENABLE, QCH_CON_VGEN_LITE_ALIVE_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_ALIVE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(WDT_ALIVE_QCH, QCH_CON_WDT_ALIVE_QCH_ENABLE, QCH_CON_WDT_ALIVE_QCH_CLOCK_REQ, QCH_CON_WDT_ALIVE_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(ALLCSIS_CMU_ALLCSIS_QCH, QCH_CON_ALLCSIS_CMU_ALLCSIS_QCH_ENABLE, QCH_CON_ALLCSIS_CMU_ALLCSIS_QCH_CLOCK_REQ, QCH_CON_ALLCSIS_CMU_ALLCSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(CSIS_PDP_QCH_VOTF0, QCH_CON_CSIS_PDP_QCH_VOTF0_ENABLE, QCH_CON_CSIS_PDP_QCH_VOTF0_CLOCK_REQ, QCH_CON_CSIS_PDP_QCH_VOTF0_IGNORE_FORCE_PM_EN),
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CLK_QCH(CSIS_PDP_QCH_DMA, QCH_CON_CSIS_PDP_QCH_DMA_ENABLE, QCH_CON_CSIS_PDP_QCH_DMA_CLOCK_REQ, QCH_CON_CSIS_PDP_QCH_DMA_IGNORE_FORCE_PM_EN),
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CLK_QCH(CSIS_PDP_QCH_MCB, QCH_CON_CSIS_PDP_QCH_MCB_ENABLE, QCH_CON_CSIS_PDP_QCH_MCB_CLOCK_REQ, QCH_CON_CSIS_PDP_QCH_MCB_IGNORE_FORCE_PM_EN),
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CLK_QCH(CSIS_PDP_QCH_VOTF1, QCH_CON_CSIS_PDP_QCH_VOTF1_ENABLE, QCH_CON_CSIS_PDP_QCH_VOTF1_CLOCK_REQ, QCH_CON_CSIS_PDP_QCH_VOTF1_IGNORE_FORCE_PM_EN),
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CLK_QCH(CSIS_PDP_QCH_PDP, QCH_CON_CSIS_PDP_QCH_PDP_ENABLE, QCH_CON_CSIS_PDP_QCH_PDP_CLOCK_REQ, QCH_CON_CSIS_PDP_QCH_PDP_IGNORE_FORCE_PM_EN),
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CLK_QCH(CSIS_PDP_QCH_PDP_VOTF, QCH_CON_CSIS_PDP_QCH_PDP_VOTF_ENABLE, QCH_CON_CSIS_PDP_QCH_PDP_VOTF_CLOCK_REQ, QCH_CON_CSIS_PDP_QCH_PDP_VOTF_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AST_MI_OTF0_BRPCSIS_QCH, QCH_CON_LH_AST_MI_OTF0_BRPCSIS_QCH_ENABLE, QCH_CON_LH_AST_MI_OTF0_BRPCSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_OTF0_BRPCSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AST_MI_OTF1_BRPCSIS_QCH, QCH_CON_LH_AST_MI_OTF1_BRPCSIS_QCH_ENABLE, QCH_CON_LH_AST_MI_OTF1_BRPCSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_OTF1_BRPCSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AST_SI_OTF0_CSISCSTAT_QCH, QCH_CON_LH_AST_SI_OTF0_CSISCSTAT_QCH_ENABLE, QCH_CON_LH_AST_SI_OTF0_CSISCSTAT_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_OTF0_CSISCSTAT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AST_SI_OTF1_CSISCSTAT_QCH, QCH_CON_LH_AST_SI_OTF1_CSISCSTAT_QCH_ENABLE, QCH_CON_LH_AST_SI_OTF1_CSISCSTAT_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_OTF1_CSISCSTAT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AST_SI_OTF2_CSISCSTAT_QCH, QCH_CON_LH_AST_SI_OTF2_CSISCSTAT_QCH_ENABLE, QCH_CON_LH_AST_SI_OTF2_CSISCSTAT_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_OTF2_CSISCSTAT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AST_SI_OTF3_CSISCSTAT_QCH, QCH_CON_LH_AST_SI_OTF3_CSISCSTAT_QCH_ENABLE, QCH_CON_LH_AST_SI_OTF3_CSISCSTAT_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_OTF3_CSISCSTAT_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AST_SI_OTF_CSISBRP_QCH, QCH_CON_LH_AST_SI_OTF_CSISBRP_QCH_ENABLE, QCH_CON_LH_AST_SI_OTF_CSISBRP_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_OTF_CSISBRP_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_MI_LP_INT_P0OIS_CSIS_QCH, QCH_CON_LH_AXI_MI_LP_INT_P0OIS_CSIS_QCH_ENABLE, QCH_CON_LH_AXI_MI_LP_INT_P0OIS_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LP_INT_P0OIS_CSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_SI_D0_CSIS_QCH, QCH_CON_LH_AXI_SI_D0_CSIS_QCH_ENABLE, QCH_CON_LH_AXI_SI_D0_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D0_CSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_SI_D1_CSIS_QCH, QCH_CON_LH_AXI_SI_D1_CSIS_QCH_ENABLE, QCH_CON_LH_AXI_SI_D1_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D1_CSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_SI_D2_CSIS_QCH, QCH_CON_LH_AXI_SI_D2_CSIS_QCH_ENABLE, QCH_CON_LH_AXI_SI_D2_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D2_CSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_SI_LP_INT_P0OIS_CSIS_QCH, QCH_CON_LH_AXI_SI_LP_INT_P0OIS_CSIS_QCH_ENABLE, QCH_CON_LH_AXI_SI_LP_INT_P0OIS_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LP_INT_P0OIS_CSIS_QCH_IGNORE_FORCE_PM_EN),
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CLK_QCH(LH_AXI_SI_LP_INT_P0P1_CSIS_QCH, QCH_CON_LH_AXI_SI_LP_INT_P0P1_CSIS_QCH_ENABLE, QCH_CON_LH_AXI_SI_LP_INT_P0P1_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LP_INT_P0P1_CSIS_QCH_IGNORE_FORCE_PM_EN),
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|
|
CLK_QCH(OIS_MCU_TOP_QCH, QCH_CON_OIS_MCU_TOP_QCH_ENABLE, QCH_CON_OIS_MCU_TOP_QCH_CLOCK_REQ, QCH_CON_OIS_MCU_TOP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_D0_QCH, QCH_CON_PPMU_D0_QCH_ENABLE, QCH_CON_PPMU_D0_QCH_CLOCK_REQ, QCH_CON_PPMU_D0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_D1_QCH, QCH_CON_PPMU_D1_QCH_ENABLE, QCH_CON_PPMU_D1_QCH_CLOCK_REQ, QCH_CON_PPMU_D1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_D2_QCH, QCH_CON_PPMU_D2_QCH_ENABLE, QCH_CON_PPMU_D2_QCH_CLOCK_REQ, QCH_CON_PPMU_D2_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(QE_CSIS_WDMA0_QCH, QCH_CON_QE_CSIS_WDMA0_QCH_ENABLE, QCH_CON_QE_CSIS_WDMA0_QCH_CLOCK_REQ, QCH_CON_QE_CSIS_WDMA0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(QE_CSIS_WDMA1_QCH, QCH_CON_QE_CSIS_WDMA1_QCH_ENABLE, QCH_CON_QE_CSIS_WDMA1_QCH_CLOCK_REQ, QCH_CON_QE_CSIS_WDMA1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(QE_CSIS_WDMA2_QCH, QCH_CON_QE_CSIS_WDMA2_QCH_ENABLE, QCH_CON_QE_CSIS_WDMA2_QCH_CLOCK_REQ, QCH_CON_QE_CSIS_WDMA2_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(QE_CSIS_WDMA3_QCH, QCH_CON_QE_CSIS_WDMA3_QCH_ENABLE, QCH_CON_QE_CSIS_WDMA3_QCH_CLOCK_REQ, QCH_CON_QE_CSIS_WDMA3_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(QE_CSIS_WDMA4_QCH, QCH_CON_QE_CSIS_WDMA4_QCH_ENABLE, QCH_CON_QE_CSIS_WDMA4_QCH_CLOCK_REQ, QCH_CON_QE_CSIS_WDMA4_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(QE_PDP_D0_QCH, QCH_CON_QE_PDP_D0_QCH_ENABLE, QCH_CON_QE_PDP_D0_QCH_CLOCK_REQ, QCH_CON_QE_PDP_D0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_CLK_ALLCSIS_NOCD_QCH, QCH_CON_RSTNSYNC_CLK_ALLCSIS_NOCD_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_ALLCSIS_NOCD_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_ALLCSIS_NOCD_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_CLK_ALLCSIS_NOCP_QCH, QCH_CON_RSTNSYNC_CLK_ALLCSIS_NOCP_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_ALLCSIS_NOCP_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_ALLCSIS_NOCP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_CLK_ALLCSIS_OIS_MCU_QCH, QCH_CON_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_CLK_ALLCSIS_OIS_MCU_CPU_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_CPU_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_CPU_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_CPU_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_SR_CLK_ALLCSIS_NOCD_QCH, QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_NOCD_QCH_ENABLE, QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_NOCD_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_NOCD_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_SR_CLK_ALLCSIS_NOCP_QCH, QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_NOCP_QCH_ENABLE, QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_NOCP_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_NOCP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_SR_CLK_ALLCSIS_OIS_MCU_QCH, QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_OIS_MCU_QCH_ENABLE, QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_OIS_MCU_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_OIS_MCU_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SIU_G_PPMU_CSIS_QCH, QCH_CON_SIU_G_PPMU_CSIS_QCH_ENABLE, QCH_CON_SIU_G_PPMU_CSIS_QCH_CLOCK_REQ, QCH_CON_SIU_G_PPMU_CSIS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_SI_G_PPMU_CSIS_QCH, QCH_CON_SLH_AST_SI_G_PPMU_CSIS_QCH_ENABLE, QCH_CON_SLH_AST_SI_G_PPMU_CSIS_QCH_CLOCK_REQ, QCH_CON_SLH_AST_SI_G_PPMU_CSIS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_P_CSIS_QCH, QCH_CON_SLH_AXI_MI_P_CSIS_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_CSIS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_CSIS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_LP_CSISPERIC2_QCH, QCH_CON_SLH_AXI_SI_LP_CSISPERIC2_QCH_ENABLE, QCH_CON_SLH_AXI_SI_LP_CSISPERIC2_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_LP_CSISPERIC2_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D0_CSIS_QCH_S1, QCH_CON_SYSMMU_D0_CSIS_QCH_S1_ENABLE, QCH_CON_SYSMMU_D0_CSIS_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D0_CSIS_QCH_S1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D0_CSIS_QCH_S2, QCH_CON_SYSMMU_D0_CSIS_QCH_S2_ENABLE, QCH_CON_SYSMMU_D0_CSIS_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D0_CSIS_QCH_S2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D1_CSIS_QCH_S1, QCH_CON_SYSMMU_D1_CSIS_QCH_S1_ENABLE, QCH_CON_SYSMMU_D1_CSIS_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D1_CSIS_QCH_S1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D1_CSIS_QCH_S2, QCH_CON_SYSMMU_D1_CSIS_QCH_S2_ENABLE, QCH_CON_SYSMMU_D1_CSIS_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D1_CSIS_QCH_S2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D2_CSIS_QCH_S1, QCH_CON_SYSMMU_D2_CSIS_QCH_S1_ENABLE, QCH_CON_SYSMMU_D2_CSIS_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D2_CSIS_QCH_S1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D2_CSIS_QCH_S2, QCH_CON_SYSMMU_D2_CSIS_QCH_S2_ENABLE, QCH_CON_SYSMMU_D2_CSIS_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D2_CSIS_QCH_S2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(VGEN_LITE_D0_QCH, QCH_CON_VGEN_LITE_D0_QCH_ENABLE, QCH_CON_VGEN_LITE_D0_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_D0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(VGEN_LITE_D1_QCH, QCH_CON_VGEN_LITE_D1_QCH_ENABLE, QCH_CON_VGEN_LITE_D1_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_D1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ABOX_QCH_ACLK, QCH_CON_ABOX_QCH_ACLK_ENABLE, QCH_CON_ABOX_QCH_ACLK_CLOCK_REQ, QCH_CON_ABOX_QCH_ACLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ABOX_QCH_BCLK_DSIF, QCH_CON_ABOX_QCH_BCLK_DSIF_ENABLE, QCH_CON_ABOX_QCH_BCLK_DSIF_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK_DSIF_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ABOX_QCH_BCLK0, QCH_CON_ABOX_QCH_BCLK0_ENABLE, QCH_CON_ABOX_QCH_BCLK0_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK0_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ABOX_QCH_BCLK1, QCH_CON_ABOX_QCH_BCLK1_ENABLE, QCH_CON_ABOX_QCH_BCLK1_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ABOX_QCH_BCLK2, QCH_CON_ABOX_QCH_BCLK2_ENABLE, QCH_CON_ABOX_QCH_BCLK2_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ABOX_QCH_BCLK3, QCH_CON_ABOX_QCH_BCLK3_ENABLE, QCH_CON_ABOX_QCH_BCLK3_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK3_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ABOX_QCH_CPU, DMYQCH_CON_ABOX_QCH_CPU_ENABLE, DMYQCH_CON_ABOX_QCH_CPU_CLOCK_REQ, DMYQCH_CON_ABOX_QCH_CPU_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ABOX_QCH_BCLK4, QCH_CON_ABOX_QCH_BCLK4_ENABLE, QCH_CON_ABOX_QCH_BCLK4_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK4_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ABOX_QCH_CNT, QCH_CON_ABOX_QCH_CNT_ENABLE, QCH_CON_ABOX_QCH_CNT_CLOCK_REQ, QCH_CON_ABOX_QCH_CNT_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ABOX_QCH_BCLK5, QCH_CON_ABOX_QCH_BCLK5_ENABLE, QCH_CON_ABOX_QCH_BCLK5_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK5_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ABOX_QCH_CCLK_ASB, QCH_CON_ABOX_QCH_CCLK_ASB_ENABLE, QCH_CON_ABOX_QCH_CCLK_ASB_CLOCK_REQ, QCH_CON_ABOX_QCH_CCLK_ASB_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ABOX_QCH_BCLK6, QCH_CON_ABOX_QCH_BCLK6_ENABLE, QCH_CON_ABOX_QCH_BCLK6_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK6_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ABOX_QCH_XCLK0, QCH_CON_ABOX_QCH_XCLK0_ENABLE, QCH_CON_ABOX_QCH_XCLK0_CLOCK_REQ, QCH_CON_ABOX_QCH_XCLK0_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ABOX_QCH_PCMC_CLK, QCH_CON_ABOX_QCH_PCMC_CLK_ENABLE, QCH_CON_ABOX_QCH_PCMC_CLK_CLOCK_REQ, QCH_CON_ABOX_QCH_PCMC_CLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ABOX_QCH_C2A0, QCH_CON_ABOX_QCH_C2A0_ENABLE, QCH_CON_ABOX_QCH_C2A0_CLOCK_REQ, QCH_CON_ABOX_QCH_C2A0_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ABOX_QCH_C2A1, QCH_CON_ABOX_QCH_C2A1_ENABLE, QCH_CON_ABOX_QCH_C2A1_CLOCK_REQ, QCH_CON_ABOX_QCH_C2A1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ABOX_QCH_XCLK1, QCH_CON_ABOX_QCH_XCLK1_ENABLE, QCH_CON_ABOX_QCH_XCLK1_CLOCK_REQ, QCH_CON_ABOX_QCH_XCLK1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ABOX_QCH_XCLK2, QCH_CON_ABOX_QCH_XCLK2_ENABLE, QCH_CON_ABOX_QCH_XCLK2_CLOCK_REQ, QCH_CON_ABOX_QCH_XCLK2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ABOX_QCH_CPU0, QCH_CON_ABOX_QCH_CPU0_ENABLE, QCH_CON_ABOX_QCH_CPU0_CLOCK_REQ, QCH_CON_ABOX_QCH_CPU0_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ABOX_QCH_CPU1, QCH_CON_ABOX_QCH_CPU1_ENABLE, QCH_CON_ABOX_QCH_CPU1_CLOCK_REQ, QCH_CON_ABOX_QCH_CPU1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ABOX_QCH_CPU2, QCH_CON_ABOX_QCH_CPU2_ENABLE, QCH_CON_ABOX_QCH_CPU2_CLOCK_REQ, QCH_CON_ABOX_QCH_CPU2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ABOX_QCH_NEON0, QCH_CON_ABOX_QCH_NEON0_ENABLE, QCH_CON_ABOX_QCH_NEON0_CLOCK_REQ, QCH_CON_ABOX_QCH_NEON0_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ABOX_QCH_NEON1, QCH_CON_ABOX_QCH_NEON1_ENABLE, QCH_CON_ABOX_QCH_NEON1_CLOCK_REQ, QCH_CON_ABOX_QCH_NEON1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ABOX_QCH_NEON2, QCH_CON_ABOX_QCH_NEON2_ENABLE, QCH_CON_ABOX_QCH_NEON2_CLOCK_REQ, QCH_CON_ABOX_QCH_NEON2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ABOX_QCH_L2, QCH_CON_ABOX_QCH_L2_ENABLE, QCH_CON_ABOX_QCH_L2_CLOCK_REQ, QCH_CON_ABOX_QCH_L2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ABOX_QCH_CCLK_ACP, QCH_CON_ABOX_QCH_CCLK_ACP_ENABLE, QCH_CON_ABOX_QCH_CCLK_ACP_CLOCK_REQ, QCH_CON_ABOX_QCH_CCLK_ACP_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ABOX_QCH_ACLK_ACP, QCH_CON_ABOX_QCH_ACLK_ACP_ENABLE, QCH_CON_ABOX_QCH_ACLK_ACP_CLOCK_REQ, QCH_CON_ABOX_QCH_ACLK_ACP_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ABOX_QCH_ACLK_ASB, QCH_CON_ABOX_QCH_ACLK_ASB_ENABLE, QCH_CON_ABOX_QCH_ACLK_ASB_CLOCK_REQ, QCH_CON_ABOX_QCH_ACLK_ASB_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(AUD_CMU_AUD_QCH, QCH_CON_AUD_CMU_AUD_QCH_ENABLE, QCH_CON_AUD_CMU_AUD_QCH_CLOCK_REQ, QCH_CON_AUD_CMU_AUD_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(BAAW_D_AUDCHUBVTS_QCH, QCH_CON_BAAW_D_AUDCHUBVTS_QCH_ENABLE, QCH_CON_BAAW_D_AUDCHUBVTS_QCH_CLOCK_REQ, QCH_CON_BAAW_D_AUDCHUBVTS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DFTMUX_AUD_QCH, DMYQCH_CON_DFTMUX_AUD_QCH_ENABLE, DMYQCH_CON_DFTMUX_AUD_QCH_CLOCK_REQ, DMYQCH_CON_DFTMUX_AUD_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DMAILBOX_AUD_QCH_PCLK, QCH_CON_DMAILBOX_AUD_QCH_PCLK_ENABLE, QCH_CON_DMAILBOX_AUD_QCH_PCLK_CLOCK_REQ, QCH_CON_DMAILBOX_AUD_QCH_PCLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DMAILBOX_AUD_QCH_ACLK, QCH_CON_DMAILBOX_AUD_QCH_ACLK_ENABLE, QCH_CON_DMAILBOX_AUD_QCH_ACLK_CLOCK_REQ, QCH_CON_DMAILBOX_AUD_QCH_ACLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DMAILBOX_AUD_QCH_CCLK, QCH_CON_DMAILBOX_AUD_QCH_CCLK_ENABLE, QCH_CON_DMAILBOX_AUD_QCH_CCLK_CLOCK_REQ, QCH_CON_DMAILBOX_AUD_QCH_CCLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DMIC_AUD0_QCH_PCLK, QCH_CON_DMIC_AUD0_QCH_PCLK_ENABLE, QCH_CON_DMIC_AUD0_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_AUD0_QCH_PCLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DMIC_AUD0_QCH_DMIC, DMYQCH_CON_DMIC_AUD0_QCH_DMIC_ENABLE, DMYQCH_CON_DMIC_AUD0_QCH_DMIC_CLOCK_REQ, DMYQCH_CON_DMIC_AUD0_QCH_DMIC_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DMIC_AUD1_QCH_PCLK, QCH_CON_DMIC_AUD1_QCH_PCLK_ENABLE, QCH_CON_DMIC_AUD1_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_AUD1_QCH_PCLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DMIC_AUD1_QCH_DMIC, DMYQCH_CON_DMIC_AUD1_QCH_DMIC_ENABLE, DMYQCH_CON_DMIC_AUD1_QCH_DMIC_CLOCK_REQ, DMYQCH_CON_DMIC_AUD1_QCH_DMIC_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DMIC_AUD2_QCH_PCLK, QCH_CON_DMIC_AUD2_QCH_PCLK_ENABLE, QCH_CON_DMIC_AUD2_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_AUD2_QCH_PCLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DMIC_AUD2_QCH_DMIC, DMYQCH_CON_DMIC_AUD2_QCH_DMIC_ENABLE, DMYQCH_CON_DMIC_AUD2_QCH_DMIC_CLOCK_REQ, DMYQCH_CON_DMIC_AUD2_QCH_DMIC_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(D_TZPC_AUD_QCH, QCH_CON_D_TZPC_AUD_QCH_ENABLE, QCH_CON_D_TZPC_AUD_QCH_CLOCK_REQ, QCH_CON_D_TZPC_AUD_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_PERI_ASB_QCH, QCH_CON_LH_AXI_MI_PERI_ASB_QCH_ENABLE, QCH_CON_LH_AXI_MI_PERI_ASB_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_PERI_ASB_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_PERI_ASB_QCH, QCH_CON_LH_AXI_SI_PERI_ASB_QCH_ENABLE, QCH_CON_LH_AXI_SI_PERI_ASB_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_PERI_ASB_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_QDI_SI_D_AUD_QCH, QCH_CON_LH_QDI_SI_D_AUD_QCH_ENABLE, QCH_CON_LH_QDI_SI_D_AUD_QCH_CLOCK_REQ, QCH_CON_LH_QDI_SI_D_AUD_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(MAILBOX_AUD0_QCH, QCH_CON_MAILBOX_AUD0_QCH_ENABLE, QCH_CON_MAILBOX_AUD0_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AUD0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(MAILBOX_AUD1_QCH, QCH_CON_MAILBOX_AUD1_QCH_ENABLE, QCH_CON_MAILBOX_AUD1_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AUD1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(MAILBOX_AUD2_QCH, QCH_CON_MAILBOX_AUD2_QCH_ENABLE, QCH_CON_MAILBOX_AUD2_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AUD2_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(MAILBOX_AUD3_QCH, QCH_CON_MAILBOX_AUD3_QCH_ENABLE, QCH_CON_MAILBOX_AUD3_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AUD3_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_AUD_QCH, QCH_CON_PPMU_AUD_QCH_ENABLE, QCH_CON_PPMU_AUD_QCH_CLOCK_REQ, QCH_CON_PPMU_AUD_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_CLK_AUD_CPU2_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_AUD_CPU2_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_AUD_CPU2_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_AUD_CPU2_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH, QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SERIAL_LIF_QCH_PCLK, QCH_CON_SERIAL_LIF_QCH_PCLK_ENABLE, QCH_CON_SERIAL_LIF_QCH_PCLK_CLOCK_REQ, QCH_CON_SERIAL_LIF_QCH_PCLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SERIAL_LIF_QCH_BCLK, QCH_CON_SERIAL_LIF_QCH_BCLK_ENABLE, QCH_CON_SERIAL_LIF_QCH_BCLK_CLOCK_REQ, QCH_CON_SERIAL_LIF_QCH_BCLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SERIAL_LIF_QCH_ACLK, QCH_CON_SERIAL_LIF_QCH_ACLK_ENABLE, QCH_CON_SERIAL_LIF_QCH_ACLK_CLOCK_REQ, QCH_CON_SERIAL_LIF_QCH_ACLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SERIAL_LIF_QCH_CCLK, QCH_CON_SERIAL_LIF_QCH_CCLK_ENABLE, QCH_CON_SERIAL_LIF_QCH_CCLK_CLOCK_REQ, QCH_CON_SERIAL_LIF_QCH_CCLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_SI_G_PPMU_AUD_QCH, QCH_CON_SLH_AST_SI_G_PPMU_AUD_QCH_ENABLE, QCH_CON_SLH_AST_SI_G_PPMU_AUD_QCH_CLOCK_REQ, QCH_CON_SLH_AST_SI_G_PPMU_AUD_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_LD_HSI0AUD_QCH, QCH_CON_SLH_AXI_MI_LD_HSI0AUD_QCH_ENABLE, QCH_CON_SLH_AXI_MI_LD_HSI0AUD_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_LD_HSI0AUD_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_P_AUD_QCH, QCH_CON_SLH_AXI_MI_P_AUD_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_AUD_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_AUD_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_LD_AUDHSI0_QCH, QCH_CON_SLH_AXI_SI_LD_AUDHSI0_QCH_ENABLE, QCH_CON_SLH_AXI_SI_LD_AUDHSI0_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_LD_AUDHSI0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_LP_AUDCHUBVTS_QCH, QCH_CON_SLH_AXI_SI_LP_AUDCHUBVTS_QCH_ENABLE, QCH_CON_SLH_AXI_SI_LP_AUDCHUBVTS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_LP_AUDCHUBVTS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SMMU_AUD_QCH_S1, QCH_CON_SMMU_AUD_QCH_S1_ENABLE, QCH_CON_SMMU_AUD_QCH_S1_CLOCK_REQ, QCH_CON_SMMU_AUD_QCH_S1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SMMU_AUD_QCH_S2, QCH_CON_SMMU_AUD_QCH_S2_ENABLE, QCH_CON_SMMU_AUD_QCH_S2_CLOCK_REQ, QCH_CON_SMMU_AUD_QCH_S2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_AUD_QCH, QCH_CON_SYSREG_AUD_QCH_ENABLE, QCH_CON_SYSREG_AUD_QCH_CLOCK_REQ, QCH_CON_SYSREG_AUD_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(TREX_AUD_QCH, QCH_CON_TREX_AUD_QCH_ENABLE, QCH_CON_TREX_AUD_QCH_CLOCK_REQ, QCH_CON_TREX_AUD_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(VGEN_LITE_AUD_QCH, QCH_CON_VGEN_LITE_AUD_QCH_ENABLE, QCH_CON_VGEN_LITE_AUD_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_AUD_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(WDT_AUD_QCH, QCH_CON_WDT_AUD_QCH_ENABLE, QCH_CON_WDT_AUD_QCH_CLOCK_REQ, QCH_CON_WDT_AUD_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ADD_BRP_QCH, DMYQCH_CON_ADD_BRP_QCH_ENABLE, DMYQCH_CON_ADD_BRP_QCH_CLOCK_REQ, DMYQCH_CON_ADD_BRP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(BRP_CMU_BRP_QCH, QCH_CON_BRP_CMU_BRP_QCH_ENABLE, QCH_CON_BRP_CMU_BRP_QCH_CLOCK_REQ, QCH_CON_BRP_CMU_BRP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(BUSIF_ADD_BRP_QCH, QCH_CON_BUSIF_ADD_BRP_QCH_ENABLE, QCH_CON_BUSIF_ADD_BRP_QCH_CLOCK_REQ, QCH_CON_BUSIF_ADD_BRP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(BYRP_QCH, QCH_CON_BYRP_QCH_ENABLE, QCH_CON_BYRP_QCH_CLOCK_REQ, QCH_CON_BYRP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(BYRP_QCH_C2S_ZSL, QCH_CON_BYRP_QCH_C2S_ZSL_ENABLE, QCH_CON_BYRP_QCH_C2S_ZSL_CLOCK_REQ, QCH_CON_BYRP_QCH_C2S_ZSL_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(BYRP_QCH_C2S_BYR, QCH_CON_BYRP_QCH_C2S_BYR_ENABLE, QCH_CON_BYRP_QCH_C2S_BYR_CLOCK_REQ, QCH_CON_BYRP_QCH_C2S_BYR_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(D_TZPC_BRP_QCH, QCH_CON_D_TZPC_BRP_QCH_ENABLE, QCH_CON_D_TZPC_BRP_QCH_CLOCK_REQ, QCH_CON_D_TZPC_BRP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_MI_OTF_CSISBRP_QCH, QCH_CON_LH_AST_MI_OTF_CSISBRP_QCH_ENABLE, QCH_CON_LH_AST_MI_OTF_CSISBRP_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_OTF_CSISBRP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_SI_OTF0_BRPCSIS_QCH, QCH_CON_LH_AST_SI_OTF0_BRPCSIS_QCH_ENABLE, QCH_CON_LH_AST_SI_OTF0_BRPCSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_OTF0_BRPCSIS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_SI_OTF1_BRPCSIS_QCH, QCH_CON_LH_AST_SI_OTF1_BRPCSIS_QCH_ENABLE, QCH_CON_LH_AST_SI_OTF1_BRPCSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_OTF1_BRPCSIS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_SI_OTF_BRPMCSC_QCH, QCH_CON_LH_AST_SI_OTF_BRPMCSC_QCH_ENABLE, QCH_CON_LH_AST_SI_OTF_BRPMCSC_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_OTF_BRPMCSC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_D0_BRP_QCH, QCH_CON_LH_AXI_SI_D0_BRP_QCH_ENABLE, QCH_CON_LH_AXI_SI_D0_BRP_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D0_BRP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_D1_BRP_QCH, QCH_CON_LH_AXI_SI_D1_BRP_QCH_ENABLE, QCH_CON_LH_AXI_SI_D1_BRP_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D1_BRP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_D2_BRP_QCH, QCH_CON_LH_AXI_SI_D2_BRP_QCH_ENABLE, QCH_CON_LH_AXI_SI_D2_BRP_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D2_BRP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(L_SIU_BRP_QCH, QCH_CON_L_SIU_BRP_QCH_ENABLE, QCH_CON_L_SIU_BRP_QCH_CLOCK_REQ, QCH_CON_L_SIU_BRP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_D0_BRP_QCH, QCH_CON_PPMU_D0_BRP_QCH_ENABLE, QCH_CON_PPMU_D0_BRP_QCH_CLOCK_REQ, QCH_CON_PPMU_D0_BRP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_D1_BRP_QCH, QCH_CON_PPMU_D1_BRP_QCH_ENABLE, QCH_CON_PPMU_D1_BRP_QCH_CLOCK_REQ, QCH_CON_PPMU_D1_BRP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_D2_BRP_QCH, QCH_CON_PPMU_D2_BRP_QCH_ENABLE, QCH_CON_PPMU_D2_BRP_QCH_CLOCK_REQ, QCH_CON_PPMU_D2_BRP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RGBP_QCH, QCH_CON_RGBP_QCH_ENABLE, QCH_CON_RGBP_QCH_CLOCK_REQ, QCH_CON_RGBP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RGBP_QCH_VOTF0, QCH_CON_RGBP_QCH_VOTF0_ENABLE, QCH_CON_RGBP_QCH_VOTF0_CLOCK_REQ, QCH_CON_RGBP_QCH_VOTF0_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RGBP_QCH_VOTF1, QCH_CON_RGBP_QCH_VOTF1_ENABLE, QCH_CON_RGBP_QCH_VOTF1_CLOCK_REQ, QCH_CON_RGBP_QCH_VOTF1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_SI_G_PPMU_BRP_QCH, QCH_CON_SLH_AST_SI_G_PPMU_BRP_QCH_ENABLE, QCH_CON_SLH_AST_SI_G_PPMU_BRP_QCH_CLOCK_REQ, QCH_CON_SLH_AST_SI_G_PPMU_BRP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_P_BRP_QCH, QCH_CON_SLH_AXI_MI_P_BRP_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_BRP_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_BRP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D0_BRP_QCH_S1, QCH_CON_SYSMMU_D0_BRP_QCH_S1_ENABLE, QCH_CON_SYSMMU_D0_BRP_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D0_BRP_QCH_S1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D0_BRP_QCH_S2, QCH_CON_SYSMMU_D0_BRP_QCH_S2_ENABLE, QCH_CON_SYSMMU_D0_BRP_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D0_BRP_QCH_S2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D1_BRP_QCH_S1, QCH_CON_SYSMMU_D1_BRP_QCH_S1_ENABLE, QCH_CON_SYSMMU_D1_BRP_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D1_BRP_QCH_S1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D1_BRP_QCH_S2, QCH_CON_SYSMMU_D1_BRP_QCH_S2_ENABLE, QCH_CON_SYSMMU_D1_BRP_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D1_BRP_QCH_S2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D2_BRP_QCH_S1, QCH_CON_SYSMMU_D2_BRP_QCH_S1_ENABLE, QCH_CON_SYSMMU_D2_BRP_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D2_BRP_QCH_S1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D2_BRP_QCH_S2, QCH_CON_SYSMMU_D2_BRP_QCH_S2_ENABLE, QCH_CON_SYSMMU_D2_BRP_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D2_BRP_QCH_S2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_BRP_QCH, QCH_CON_SYSREG_BRP_QCH_ENABLE, QCH_CON_SYSREG_BRP_QCH_CLOCK_REQ, QCH_CON_SYSREG_BRP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(VGEN_LITE_BYRP_QCH, QCH_CON_VGEN_LITE_BYRP_QCH_ENABLE, QCH_CON_VGEN_LITE_BYRP_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_BYRP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(VGEN_LITE_RGBP_QCH, QCH_CON_VGEN_LITE_RGBP_QCH_ENABLE, QCH_CON_VGEN_LITE_RGBP_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_RGBP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(APBIF_CHUB_COMBINE_WAKEUP_SRC_QCH, QCH_CON_APBIF_CHUB_COMBINE_WAKEUP_SRC_QCH_ENABLE, QCH_CON_APBIF_CHUB_COMBINE_WAKEUP_SRC_QCH_CLOCK_REQ, QCH_CON_APBIF_CHUB_COMBINE_WAKEUP_SRC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(APBIF_GPIO_CHUB_QCH, QCH_CON_APBIF_GPIO_CHUB_QCH_ENABLE, QCH_CON_APBIF_GPIO_CHUB_QCH_CLOCK_REQ, QCH_CON_APBIF_GPIO_CHUB_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CHUB_CMU_CHUB_QCH, QCH_CON_CHUB_CMU_CHUB_QCH_ENABLE, QCH_CON_CHUB_CMU_CHUB_QCH_CLOCK_REQ, QCH_CON_CHUB_CMU_CHUB_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CM4_CHUB_QCH_CPU, QCH_CON_CM4_CHUB_QCH_CPU_ENABLE, QCH_CON_CM4_CHUB_QCH_CPU_CLOCK_REQ, QCH_CON_CM4_CHUB_QCH_CPU_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(I2C_CHUB_QCH, QCH_CON_I2C_CHUB_QCH_ENABLE, QCH_CON_I2C_CHUB_QCH_CLOCK_REQ, QCH_CON_I2C_CHUB_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(I3C_CHUB_QCH_S, QCH_CON_I3C_CHUB_QCH_S_ENABLE, QCH_CON_I3C_CHUB_QCH_S_CLOCK_REQ, QCH_CON_I3C_CHUB_QCH_S_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(I3C_CHUB_QCH_P, QCH_CON_I3C_CHUB_QCH_P_ENABLE, QCH_CON_I3C_CHUB_QCH_P_CLOCK_REQ, QCH_CON_I3C_CHUB_QCH_P_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_IP_VC2CHUB_QCH, QCH_CON_LH_AXI_MI_IP_VC2CHUB_QCH_ENABLE, QCH_CON_LH_AXI_MI_IP_VC2CHUB_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_IP_VC2CHUB_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_ID_CHUB2VC_QCH, QCH_CON_LH_AXI_SI_ID_CHUB2VC_QCH_ENABLE, QCH_CON_LH_AXI_SI_ID_CHUB2VC_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_ID_CHUB2VC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(MAILBOX_CHUB_ABOX_QCH, QCH_CON_MAILBOX_CHUB_ABOX_QCH_ENABLE, QCH_CON_MAILBOX_CHUB_ABOX_QCH_CLOCK_REQ, QCH_CON_MAILBOX_CHUB_ABOX_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(MAILBOX_CHUB_DNC_QCH, QCH_CON_MAILBOX_CHUB_DNC_QCH_ENABLE, QCH_CON_MAILBOX_CHUB_DNC_QCH_CLOCK_REQ, QCH_CON_MAILBOX_CHUB_DNC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PWM_CHUB_QCH, QCH_CON_PWM_CHUB_QCH_ENABLE, QCH_CON_PWM_CHUB_QCH_CLOCK_REQ, QCH_CON_PWM_CHUB_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SPI_I2C_CHUB0_QCH, QCH_CON_SPI_I2C_CHUB0_QCH_ENABLE, QCH_CON_SPI_I2C_CHUB0_QCH_CLOCK_REQ, QCH_CON_SPI_I2C_CHUB0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SPI_I2C_CHUB1_QCH, QCH_CON_SPI_I2C_CHUB1_QCH_ENABLE, QCH_CON_SPI_I2C_CHUB1_QCH_CLOCK_REQ, QCH_CON_SPI_I2C_CHUB1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SPI_MULTI_SLV_Q_CTRL_CHUB_QCH, QCH_CON_SPI_MULTI_SLV_Q_CTRL_CHUB_QCH_ENABLE, QCH_CON_SPI_MULTI_SLV_Q_CTRL_CHUB_QCH_CLOCK_REQ, QCH_CON_SPI_MULTI_SLV_Q_CTRL_CHUB_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_CHUB_QCH, QCH_CON_SYSREG_CHUB_QCH_ENABLE, QCH_CON_SYSREG_CHUB_QCH_CLOCK_REQ, QCH_CON_SYSREG_CHUB_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_COMBINE_CHUB2AP_QCH, QCH_CON_SYSREG_COMBINE_CHUB2AP_QCH_ENABLE, QCH_CON_SYSREG_COMBINE_CHUB2AP_QCH_CLOCK_REQ, QCH_CON_SYSREG_COMBINE_CHUB2AP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_COMBINE_CHUB2APM_QCH, QCH_CON_SYSREG_COMBINE_CHUB2APM_QCH_ENABLE, QCH_CON_SYSREG_COMBINE_CHUB2APM_QCH_CLOCK_REQ, QCH_CON_SYSREG_COMBINE_CHUB2APM_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(TIMER_CHUB_QCH, QCH_CON_TIMER_CHUB_QCH_ENABLE, QCH_CON_TIMER_CHUB_QCH_CLOCK_REQ, QCH_CON_TIMER_CHUB_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USI_CHUB0_QCH, QCH_CON_USI_CHUB0_QCH_ENABLE, QCH_CON_USI_CHUB0_QCH_CLOCK_REQ, QCH_CON_USI_CHUB0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USI_CHUB1_QCH, QCH_CON_USI_CHUB1_QCH_ENABLE, QCH_CON_USI_CHUB1_QCH_CLOCK_REQ, QCH_CON_USI_CHUB1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USI_CHUB2_QCH, QCH_CON_USI_CHUB2_QCH_ENABLE, QCH_CON_USI_CHUB2_QCH_CLOCK_REQ, QCH_CON_USI_CHUB2_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USI_CHUB3_QCH, QCH_CON_USI_CHUB3_QCH_ENABLE, QCH_CON_USI_CHUB3_QCH_CLOCK_REQ, QCH_CON_USI_CHUB3_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(WDT_CHUB_QCH, QCH_CON_WDT_CHUB_QCH_ENABLE, QCH_CON_WDT_CHUB_QCH_CLOCK_REQ, QCH_CON_WDT_CHUB_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(APBIF_UPMU_CHUB_QCH, QCH_CON_APBIF_UPMU_CHUB_QCH_ENABLE, QCH_CON_APBIF_UPMU_CHUB_QCH_CLOCK_REQ, QCH_CON_APBIF_UPMU_CHUB_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(APB_SEMA_DMAILBOX_QCH, QCH_CON_APB_SEMA_DMAILBOX_QCH_ENABLE, QCH_CON_APB_SEMA_DMAILBOX_QCH_CLOCK_REQ, QCH_CON_APB_SEMA_DMAILBOX_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(APB_SEMA_PDMA_QCH, QCH_CON_APB_SEMA_PDMA_QCH_ENABLE, QCH_CON_APB_SEMA_PDMA_QCH_CLOCK_REQ, QCH_CON_APB_SEMA_PDMA_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(BAAW_CHUB_QCH, QCH_CON_BAAW_CHUB_QCH_ENABLE, QCH_CON_BAAW_CHUB_QCH_CLOCK_REQ, QCH_CON_BAAW_CHUB_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(BAAW_LD_CHUBVTS_QCH, QCH_CON_BAAW_LD_CHUBVTS_QCH_ENABLE, QCH_CON_BAAW_LD_CHUBVTS_QCH_CLOCK_REQ, QCH_CON_BAAW_LD_CHUBVTS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CHUBVTS_CMU_CHUBVTS_QCH, QCH_CON_CHUBVTS_CMU_CHUBVTS_QCH_ENABLE, QCH_CON_CHUBVTS_CMU_CHUBVTS_QCH_CLOCK_REQ, QCH_CON_CHUBVTS_CMU_CHUBVTS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CHUB_ALV_QCH_PMU, QCH_CON_CHUB_ALV_QCH_PMU_ENABLE, QCH_CON_CHUB_ALV_QCH_PMU_CLOCK_REQ, QCH_CON_CHUB_ALV_QCH_PMU_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DMAILBOX_CHUBVTS_QCH_PCLK, QCH_CON_DMAILBOX_CHUBVTS_QCH_PCLK_ENABLE, QCH_CON_DMAILBOX_CHUBVTS_QCH_PCLK_CLOCK_REQ, QCH_CON_DMAILBOX_CHUBVTS_QCH_PCLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DMAILBOX_CHUBVTS_QCH_ACLK, QCH_CON_DMAILBOX_CHUBVTS_QCH_ACLK_ENABLE, QCH_CON_DMAILBOX_CHUBVTS_QCH_ACLK_CLOCK_REQ, QCH_CON_DMAILBOX_CHUBVTS_QCH_ACLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DMAILBOX_CHUBVTS_QCH_CCLK, QCH_CON_DMAILBOX_CHUBVTS_QCH_CCLK_ENABLE, QCH_CON_DMAILBOX_CHUBVTS_QCH_CCLK_CLOCK_REQ, QCH_CON_DMAILBOX_CHUBVTS_QCH_CCLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(D_TZPC_CHUBVTS_QCH, QCH_CON_D_TZPC_CHUBVTS_QCH_ENABLE, QCH_CON_D_TZPC_CHUBVTS_QCH_CLOCK_REQ, QCH_CON_D_TZPC_CHUBVTS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_ID_CHUB2VC_QCH, QCH_CON_LH_AXI_MI_ID_CHUB2VC_QCH_ENABLE, QCH_CON_LH_AXI_MI_ID_CHUB2VC_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_ID_CHUB2VC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_ID_VTS2VC_QCH, QCH_CON_LH_AXI_MI_ID_VTS2VC_QCH_ENABLE, QCH_CON_LH_AXI_MI_ID_VTS2VC_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_ID_VTS2VC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_IP_VC2CHUB_QCH, QCH_CON_LH_AXI_SI_IP_VC2CHUB_QCH_ENABLE, QCH_CON_LH_AXI_SI_IP_VC2CHUB_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_IP_VC2CHUB_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_IP_VC2VTS_QCH, QCH_CON_LH_AXI_SI_IP_VC2VTS_QCH_ENABLE, QCH_CON_LH_AXI_SI_IP_VC2VTS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_IP_VC2VTS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(MAILBOX_VTS_CHUB_QCH, QCH_CON_MAILBOX_VTS_CHUB_QCH_ENABLE, QCH_CON_MAILBOX_VTS_CHUB_QCH_CLOCK_REQ, QCH_CON_MAILBOX_VTS_CHUB_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PDMA_CHUBVTS_QCH, QCH_CON_PDMA_CHUBVTS_QCH_ENABLE, QCH_CON_PDMA_CHUBVTS_QCH_CLOCK_REQ, QCH_CON_PDMA_CHUBVTS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_LP_AUDCHUBVTS_QCH, QCH_CON_SLH_AXI_MI_LP_AUDCHUBVTS_QCH_ENABLE, QCH_CON_SLH_AXI_MI_LP_AUDCHUBVTS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_LP_AUDCHUBVTS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_LP_CHUBVTS_QCH, QCH_CON_SLH_AXI_MI_LP_CHUBVTS_QCH_ENABLE, QCH_CON_SLH_AXI_MI_LP_CHUBVTS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_LP_CHUBVTS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_LP_DNCCHUBVTS_QCH, QCH_CON_SLH_AXI_MI_LP_DNCCHUBVTS_QCH_ENABLE, QCH_CON_SLH_AXI_MI_LP_DNCCHUBVTS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_LP_DNCCHUBVTS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_LD_CHUBVTS_QCH, QCH_CON_SLH_AXI_SI_LD_CHUBVTS_QCH_ENABLE, QCH_CON_SLH_AXI_SI_LD_CHUBVTS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_LD_CHUBVTS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SWEEPER_LD_CHUBVTS_QCH, QCH_CON_SWEEPER_LD_CHUBVTS_QCH_ENABLE, QCH_CON_SWEEPER_LD_CHUBVTS_QCH_CLOCK_REQ, QCH_CON_SWEEPER_LD_CHUBVTS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_CHUBVTS_QCH, QCH_CON_SYSREG_CHUBVTS_QCH_ENABLE, QCH_CON_SYSREG_CHUBVTS_QCH_CLOCK_REQ, QCH_CON_SYSREG_CHUBVTS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(VGEN_LITE_CHUBVTS_QCH, QCH_CON_VGEN_LITE_CHUBVTS_QCH_ENABLE, QCH_CON_VGEN_LITE_CHUBVTS_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_CHUBVTS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(APBIF_GPIO_CMGP_QCH, QCH_CON_APBIF_GPIO_CMGP_QCH_ENABLE, QCH_CON_APBIF_GPIO_CMGP_QCH_CLOCK_REQ, QCH_CON_APBIF_GPIO_CMGP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CMGP_CMU_CMGP_QCH, QCH_CON_CMGP_CMU_CMGP_QCH_ENABLE, QCH_CON_CMGP_CMU_CMGP_QCH_CLOCK_REQ, QCH_CON_CMGP_CMU_CMGP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CMGP_I2C_QCH, QCH_CON_CMGP_I2C_QCH_ENABLE, QCH_CON_CMGP_I2C_QCH_CLOCK_REQ, QCH_CON_CMGP_I2C_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(D_TZPC_CMGP_QCH, QCH_CON_D_TZPC_CMGP_QCH_ENABLE, QCH_CON_D_TZPC_CMGP_QCH_CLOCK_REQ, QCH_CON_D_TZPC_CMGP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(I2C_CMGP2_QCH, QCH_CON_I2C_CMGP2_QCH_ENABLE, QCH_CON_I2C_CMGP2_QCH_CLOCK_REQ, QCH_CON_I2C_CMGP2_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(I2C_CMGP3_QCH, QCH_CON_I2C_CMGP3_QCH_ENABLE, QCH_CON_I2C_CMGP3_QCH_CLOCK_REQ, QCH_CON_I2C_CMGP3_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(I2C_CMGP4_QCH, QCH_CON_I2C_CMGP4_QCH_ENABLE, QCH_CON_I2C_CMGP4_QCH_CLOCK_REQ, QCH_CON_I2C_CMGP4_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(I2C_CMGP5_QCH, QCH_CON_I2C_CMGP5_QCH_ENABLE, QCH_CON_I2C_CMGP5_QCH_CLOCK_REQ, QCH_CON_I2C_CMGP5_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(I2C_CMGP6_QCH, QCH_CON_I2C_CMGP6_QCH_ENABLE, QCH_CON_I2C_CMGP6_QCH_CLOCK_REQ, QCH_CON_I2C_CMGP6_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_LP_CMGP_QCH, QCH_CON_SLH_AXI_MI_LP_CMGP_QCH_ENABLE, QCH_CON_SLH_AXI_MI_LP_CMGP_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_LP_CMGP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_LP_CMGPUFD_QCH, QCH_CON_SLH_AXI_SI_LP_CMGPUFD_QCH_ENABLE, QCH_CON_SLH_AXI_SI_LP_CMGPUFD_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_LP_CMGPUFD_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SPI_I2C_CMGP0_QCH, QCH_CON_SPI_I2C_CMGP0_QCH_ENABLE, QCH_CON_SPI_I2C_CMGP0_QCH_CLOCK_REQ, QCH_CON_SPI_I2C_CMGP0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SPI_I2C_CMGP1_QCH, QCH_CON_SPI_I2C_CMGP1_QCH_ENABLE, QCH_CON_SPI_I2C_CMGP1_QCH_CLOCK_REQ, QCH_CON_SPI_I2C_CMGP1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SPI_MULTI_SLV_Q_CTRL_CMGP_QCH, QCH_CON_SPI_MULTI_SLV_Q_CTRL_CMGP_QCH_ENABLE, QCH_CON_SPI_MULTI_SLV_Q_CTRL_CMGP_QCH_CLOCK_REQ, QCH_CON_SPI_MULTI_SLV_Q_CTRL_CMGP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_CMGP_QCH, QCH_CON_SYSREG_CMGP_QCH_ENABLE, QCH_CON_SYSREG_CMGP_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_CMGP2APM_QCH, QCH_CON_SYSREG_CMGP2APM_QCH_ENABLE, QCH_CON_SYSREG_CMGP2APM_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP2APM_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_CMGP2CHUB_QCH, QCH_CON_SYSREG_CMGP2CHUB_QCH_ENABLE, QCH_CON_SYSREG_CMGP2CHUB_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP2CHUB_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_CMGP2CP_QCH, QCH_CON_SYSREG_CMGP2CP_QCH_ENABLE, QCH_CON_SYSREG_CMGP2CP_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP2CP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_CMGP2GNSS_QCH, QCH_CON_SYSREG_CMGP2GNSS_QCH_ENABLE, QCH_CON_SYSREG_CMGP2GNSS_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP2GNSS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_CMGP2PMU_AP_QCH, QCH_CON_SYSREG_CMGP2PMU_AP_QCH_ENABLE, QCH_CON_SYSREG_CMGP2PMU_AP_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP2PMU_AP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USI_CMGP0_QCH, QCH_CON_USI_CMGP0_QCH_ENABLE, QCH_CON_USI_CMGP0_QCH_CLOCK_REQ, QCH_CON_USI_CMGP0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USI_CMGP1_QCH, QCH_CON_USI_CMGP1_QCH_ENABLE, QCH_CON_USI_CMGP1_QCH_CLOCK_REQ, QCH_CON_USI_CMGP1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USI_CMGP2_QCH, QCH_CON_USI_CMGP2_QCH_ENABLE, QCH_CON_USI_CMGP2_QCH_CLOCK_REQ, QCH_CON_USI_CMGP2_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USI_CMGP3_QCH, QCH_CON_USI_CMGP3_QCH_ENABLE, QCH_CON_USI_CMGP3_QCH_CLOCK_REQ, QCH_CON_USI_CMGP3_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USI_CMGP4_QCH, QCH_CON_USI_CMGP4_QCH_ENABLE, QCH_CON_USI_CMGP4_QCH_CLOCK_REQ, QCH_CON_USI_CMGP4_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USI_CMGP5_QCH, QCH_CON_USI_CMGP5_QCH_ENABLE, QCH_CON_USI_CMGP5_QCH_CLOCK_REQ, QCH_CON_USI_CMGP5_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USI_CMGP6_QCH, QCH_CON_USI_CMGP6_QCH_ENABLE, QCH_CON_USI_CMGP6_QCH_CLOCK_REQ, QCH_CON_USI_CMGP6_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CMU_TOP_CMUREF_QCH, DMYQCH_CON_CMU_TOP_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_TOP_CMUREF_QCH_CLOCK_REQ, DMYQCH_CON_CMU_TOP_CMUREF_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DFTMUX_CMU_QCH_CIS_CLK0, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0_ENABLE, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0_CLOCK_REQ, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DFTMUX_CMU_QCH_CIS_CLK1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1_ENABLE, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1_CLOCK_REQ, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DFTMUX_CMU_QCH_CIS_CLK2, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2_ENABLE, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2_CLOCK_REQ, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DFTMUX_CMU_QCH_CIS_CLK3, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3_ENABLE, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3_CLOCK_REQ, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DFTMUX_CMU_QCH_CIS_CLK4, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4_ENABLE, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4_CLOCK_REQ, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DFTMUX_CMU_QCH_CIS_CLK5, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5_ENABLE, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5_CLOCK_REQ, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DFTMUX_CMU_QCH_CIS_CLK6, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6_ENABLE, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6_CLOCK_REQ, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DFTMUX_CMU_QCH_CIS_CLK7, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7_ENABLE, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7_CLOCK_REQ, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ADD_CPUCL0_0_QCH, DMYQCH_CON_ADD_CPUCL0_0_QCH_ENABLE, DMYQCH_CON_ADD_CPUCL0_0_QCH_CLOCK_REQ, DMYQCH_CON_ADD_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(BUSIF_ADD_CPUCL0_0_QCH, QCH_CON_BUSIF_ADD_CPUCL0_0_QCH_ENABLE, QCH_CON_BUSIF_ADD_CPUCL0_0_QCH_CLOCK_REQ, QCH_CON_BUSIF_ADD_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(BUSIF_STR_CPUCL0_0_QCH, QCH_CON_BUSIF_STR_CPUCL0_0_QCH_ENABLE, QCH_CON_BUSIF_STR_CPUCL0_0_QCH_CLOCK_REQ, QCH_CON_BUSIF_STR_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(BUSIF_STR_CPUCL0_0_QCH_CORE, QCH_CON_BUSIF_STR_CPUCL0_0_QCH_CORE_ENABLE, QCH_CON_BUSIF_STR_CPUCL0_0_QCH_CORE_CLOCK_REQ, QCH_CON_BUSIF_STR_CPUCL0_0_QCH_CORE_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CMU_CPUCL0_CMUREF_QCH, DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH_CLOCK_REQ, DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CPUCL0_QCH_CORE0, QCH_CON_CPUCL0_QCH_CORE0_ENABLE, QCH_CON_CPUCL0_QCH_CORE0_CLOCK_REQ, QCH_CON_CPUCL0_QCH_CORE0_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CPUCL0_QCH_CORE1, QCH_CON_CPUCL0_QCH_CORE1_ENABLE, QCH_CON_CPUCL0_QCH_CORE1_CLOCK_REQ, QCH_CON_CPUCL0_QCH_CORE1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CPUCL0_QCH_CORE2, QCH_CON_CPUCL0_QCH_CORE2_ENABLE, QCH_CON_CPUCL0_QCH_CORE2_CLOCK_REQ, QCH_CON_CPUCL0_QCH_CORE2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CPUCL0_QCH_CORE3, QCH_CON_CPUCL0_QCH_CORE3_ENABLE, QCH_CON_CPUCL0_QCH_CORE3_CLOCK_REQ, QCH_CON_CPUCL0_QCH_CORE3_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CPUCL0_QCH_COMPLEX0, QCH_CON_CPUCL0_QCH_COMPLEX0_ENABLE, QCH_CON_CPUCL0_QCH_COMPLEX0_CLOCK_REQ, QCH_CON_CPUCL0_QCH_COMPLEX0_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CPUCL0_QCH_COMPLEX1, QCH_CON_CPUCL0_QCH_COMPLEX1_ENABLE, QCH_CON_CPUCL0_QCH_COMPLEX1_CLOCK_REQ, QCH_CON_CPUCL0_QCH_COMPLEX1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CPUCL0_CMU_CPUCL0_QCH, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_ENABLE, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_CLOCK_REQ, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(HTU_CPUCL0_QCH_PCLK, QCH_CON_HTU_CPUCL0_QCH_PCLK_ENABLE, QCH_CON_HTU_CPUCL0_QCH_PCLK_CLOCK_REQ, QCH_CON_HTU_CPUCL0_QCH_PCLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(HTU_CPUCL0_QCH_CLK, QCH_CON_HTU_CPUCL0_QCH_CLK_ENABLE, QCH_CON_HTU_CPUCL0_QCH_CLK_CLOCK_REQ, QCH_CON_HTU_CPUCL0_QCH_CLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_ATB_SI_IT_DDCLIT_QCH, QCH_CON_LH_ATB_SI_IT_DDCLIT_QCH_ENABLE, QCH_CON_LH_ATB_SI_IT_DDCLIT_QCH_CLOCK_REQ, QCH_CON_LH_ATB_SI_IT_DDCLIT_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_CLK_CPUCL0_POWERIP_QCH, QCH_CON_RSTNSYNC_CLK_CPUCL0_POWERIP_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_CPUCL0_POWERIP_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_CPUCL0_POWERIP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_SR_CLK_CPUCL0_HTU_QCH, QCH_CON_RSTNSYNC_SR_CLK_CPUCL0_HTU_QCH_ENABLE, QCH_CON_RSTNSYNC_SR_CLK_CPUCL0_HTU_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_SR_CLK_CPUCL0_HTU_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_SR_CLK_CPUCL0_POWERIP_QCH, QCH_CON_RSTNSYNC_SR_CLK_CPUCL0_POWERIP_QCH_ENABLE, QCH_CON_RSTNSYNC_SR_CLK_CPUCL0_POWERIP_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_SR_CLK_CPUCL0_POWERIP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(STR_CPUCL0_0_QCH, DMYQCH_CON_STR_CPUCL0_0_QCH_ENABLE, DMYQCH_CON_STR_CPUCL0_0_QCH_CLOCK_REQ, DMYQCH_CON_STR_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(U_DDD_CTRL_CORE__CPUCL0_QCH, QCH_CON_U_DDD_CTRL_CORE__CPUCL0_QCH_ENABLE, QCH_CON_U_DDD_CTRL_CORE__CPUCL0_QCH_CLOCK_REQ, QCH_CON_U_DDD_CTRL_CORE__CPUCL0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(BPS_CPUCL0_QCH, QCH_CON_BPS_CPUCL0_QCH_ENABLE, QCH_CON_BPS_CPUCL0_QCH_CLOCK_REQ, QCH_CON_BPS_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(BUSIF_DDC_CPUCL0_0_QCH, QCH_CON_BUSIF_DDC_CPUCL0_0_QCH_ENABLE, QCH_CON_BUSIF_DDC_CPUCL0_0_QCH_CLOCK_REQ, QCH_CON_BUSIF_DDC_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(BUSIF_DDC_CPUCL0_1_QCH, QCH_CON_BUSIF_DDC_CPUCL0_1_QCH_ENABLE, QCH_CON_BUSIF_DDC_CPUCL0_1_QCH_CLOCK_REQ, QCH_CON_BUSIF_DDC_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CFM_CPUCL0_QCH, QCH_CON_CFM_CPUCL0_QCH_ENABLE, QCH_CON_CFM_CPUCL0_QCH_CLOCK_REQ, QCH_CON_CFM_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CPUCL0_GLB_CMU_CPUCL0_GLB_QCH, QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH_ENABLE, QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH_CLOCK_REQ, QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CSSYS_QCH, QCH_CON_CSSYS_QCH_ENABLE, QCH_CON_CSSYS_QCH_CLOCK_REQ, QCH_CON_CSSYS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(D_TZPC_CPUCL0_QCH, QCH_CON_D_TZPC_CPUCL0_QCH_ENABLE, QCH_CON_D_TZPC_CPUCL0_QCH_CLOCK_REQ, QCH_CON_D_TZPC_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_ATB_MI_IT_CLUSTER0_QCH, QCH_CON_LH_ATB_MI_IT_CLUSTER0_QCH_ENABLE, QCH_CON_LH_ATB_MI_IT_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LH_ATB_MI_IT_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_ATB_MI_IT_DDCBIG_QCH, QCH_CON_LH_ATB_MI_IT_DDCBIG_QCH_ENABLE, QCH_CON_LH_ATB_MI_IT_DDCBIG_QCH_CLOCK_REQ, QCH_CON_LH_ATB_MI_IT_DDCBIG_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_ATB_MI_IT_DDCDSU_QCH, QCH_CON_LH_ATB_MI_IT_DDCDSU_QCH_ENABLE, QCH_CON_LH_ATB_MI_IT_DDCDSU_QCH_CLOCK_REQ, QCH_CON_LH_ATB_MI_IT_DDCDSU_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_ATB_MI_IT_DDCLIT_QCH, QCH_CON_LH_ATB_MI_IT_DDCLIT_QCH_ENABLE, QCH_CON_LH_ATB_MI_IT_DDCLIT_QCH_CLOCK_REQ, QCH_CON_LH_ATB_MI_IT_DDCLIT_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_ATB_MI_IT_DDCMID0_QCH, QCH_CON_LH_ATB_MI_IT_DDCMID0_QCH_ENABLE, QCH_CON_LH_ATB_MI_IT_DDCMID0_QCH_CLOCK_REQ, QCH_CON_LH_ATB_MI_IT_DDCMID0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_ATB_MI_IT_DDCMID1_QCH, QCH_CON_LH_ATB_MI_IT_DDCMID1_QCH_ENABLE, QCH_CON_LH_ATB_MI_IT_DDCMID1_QCH_CLOCK_REQ, QCH_CON_LH_ATB_MI_IT_DDCMID1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_ATB_MI_IT_DDCMID2_QCH, QCH_CON_LH_ATB_MI_IT_DDCMID2_QCH_ENABLE, QCH_CON_LH_ATB_MI_IT_DDCMID2_QCH_CLOCK_REQ, QCH_CON_LH_ATB_MI_IT_DDCMID2_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_ATB_MI_T_BDU_QCH, QCH_CON_LH_ATB_MI_T_BDU_QCH_ENABLE, QCH_CON_LH_ATB_MI_T_BDU_QCH_CLOCK_REQ, QCH_CON_LH_ATB_MI_T_BDU_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_ATB_MI_T_DDCG3D_QCH, QCH_CON_LH_ATB_MI_T_DDCG3D_QCH_ENABLE, QCH_CON_LH_ATB_MI_T_DDCG3D_QCH_CLOCK_REQ, QCH_CON_LH_ATB_MI_T_DDCG3D_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_G_CSSYS_QCH, QCH_CON_LH_AXI_SI_G_CSSYS_QCH_ENABLE, QCH_CON_LH_AXI_SI_G_CSSYS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_G_CSSYS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PMU_PCSM_PM_QCH, QCH_CON_PMU_PCSM_PM_QCH_ENABLE, QCH_CON_PMU_PCSM_PM_QCH_CLOCK_REQ, QCH_CON_PMU_PCSM_PM_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_QCH, QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_QCH, QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SECJTAG_QCH, QCH_CON_SECJTAG_QCH_ENABLE, QCH_CON_SECJTAG_QCH_CLOCK_REQ, QCH_CON_SECJTAG_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_G_DBGCORE_QCH, QCH_CON_SLH_AXI_MI_G_DBGCORE_QCH_ENABLE, QCH_CON_SLH_AXI_MI_G_DBGCORE_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_G_DBGCORE_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_IG_CSSYS_QCH, QCH_CON_SLH_AXI_MI_IG_CSSYS_QCH_ENABLE, QCH_CON_SLH_AXI_MI_IG_CSSYS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_IG_CSSYS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_IG_DBGCORE_QCH, QCH_CON_SLH_AXI_MI_IG_DBGCORE_QCH_ENABLE, QCH_CON_SLH_AXI_MI_IG_DBGCORE_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_IG_DBGCORE_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_IG_ETR_QCH, QCH_CON_SLH_AXI_MI_IG_ETR_QCH_ENABLE, QCH_CON_SLH_AXI_MI_IG_ETR_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_IG_ETR_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_IG_STM_QCH, QCH_CON_SLH_AXI_MI_IG_STM_QCH_ENABLE, QCH_CON_SLH_AXI_MI_IG_STM_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_IG_STM_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_P_CPUCL0_QCH, QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_IG_CSSYS_QCH, QCH_CON_SLH_AXI_SI_IG_CSSYS_QCH_ENABLE, QCH_CON_SLH_AXI_SI_IG_CSSYS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_IG_CSSYS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_IG_DBGCORE_QCH, QCH_CON_SLH_AXI_SI_IG_DBGCORE_QCH_ENABLE, QCH_CON_SLH_AXI_SI_IG_DBGCORE_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_IG_DBGCORE_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_IG_ETR_QCH, QCH_CON_SLH_AXI_SI_IG_ETR_QCH_ENABLE, QCH_CON_SLH_AXI_SI_IG_ETR_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_IG_ETR_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_IG_STM_QCH, QCH_CON_SLH_AXI_SI_IG_STM_QCH_ENABLE, QCH_CON_SLH_AXI_SI_IG_STM_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_IG_STM_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_CPUCL0_QCH, QCH_CON_SYSREG_CPUCL0_QCH_ENABLE, QCH_CON_SYSREG_CPUCL0_QCH_CLOCK_REQ, QCH_CON_SYSREG_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(TREX_CPUCL0_QCH, QCH_CON_TREX_CPUCL0_QCH_ENABLE, QCH_CON_TREX_CPUCL0_QCH_CLOCK_REQ, QCH_CON_TREX_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ADD_CPUCL0_1_QCH, DMYQCH_CON_ADD_CPUCL0_1_QCH_ENABLE, DMYQCH_CON_ADD_CPUCL0_1_QCH_CLOCK_REQ, DMYQCH_CON_ADD_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(BUSIF_ADD_CPUCL0_1_QCH, QCH_CON_BUSIF_ADD_CPUCL0_1_QCH_ENABLE, QCH_CON_BUSIF_ADD_CPUCL0_1_QCH_CLOCK_REQ, QCH_CON_BUSIF_ADD_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(BUSIF_STR_CPUCL0_1_QCH, QCH_CON_BUSIF_STR_CPUCL0_1_QCH_ENABLE, QCH_CON_BUSIF_STR_CPUCL0_1_QCH_CLOCK_REQ, QCH_CON_BUSIF_STR_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(BUSIF_STR_CPUCL0_1_QCH_CORE, QCH_CON_BUSIF_STR_CPUCL0_1_QCH_CORE_ENABLE, QCH_CON_BUSIF_STR_CPUCL0_1_QCH_CORE_CLOCK_REQ, QCH_CON_BUSIF_STR_CPUCL0_1_QCH_CORE_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CMU_CPUCL1_CMUREF_QCH, DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH_CLOCK_REQ, DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CPUCL1_QCH_CORE4, QCH_CON_CPUCL1_QCH_CORE4_ENABLE, QCH_CON_CPUCL1_QCH_CORE4_CLOCK_REQ, QCH_CON_CPUCL1_QCH_CORE4_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CPUCL1_QCH_CORE5, QCH_CON_CPUCL1_QCH_CORE5_ENABLE, QCH_CON_CPUCL1_QCH_CORE5_CLOCK_REQ, QCH_CON_CPUCL1_QCH_CORE5_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CPUCL1_QCH_CORE6, QCH_CON_CPUCL1_QCH_CORE6_ENABLE, QCH_CON_CPUCL1_QCH_CORE6_CLOCK_REQ, QCH_CON_CPUCL1_QCH_CORE6_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CPUCL1_CMU_CPUCL1_QCH, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_ENABLE, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_CLOCK_REQ, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(HTU_CPUCL1_0_QCH_PCLK, QCH_CON_HTU_CPUCL1_0_QCH_PCLK_ENABLE, QCH_CON_HTU_CPUCL1_0_QCH_PCLK_CLOCK_REQ, QCH_CON_HTU_CPUCL1_0_QCH_PCLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(HTU_CPUCL1_0_QCH_CLK, QCH_CON_HTU_CPUCL1_0_QCH_CLK_ENABLE, QCH_CON_HTU_CPUCL1_0_QCH_CLK_CLOCK_REQ, QCH_CON_HTU_CPUCL1_0_QCH_CLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(HTU_CPUCL1_1_QCH_PCLK, QCH_CON_HTU_CPUCL1_1_QCH_PCLK_ENABLE, QCH_CON_HTU_CPUCL1_1_QCH_PCLK_CLOCK_REQ, QCH_CON_HTU_CPUCL1_1_QCH_PCLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(HTU_CPUCL1_1_QCH_CLK, QCH_CON_HTU_CPUCL1_1_QCH_CLK_ENABLE, QCH_CON_HTU_CPUCL1_1_QCH_CLK_CLOCK_REQ, QCH_CON_HTU_CPUCL1_1_QCH_CLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(HTU_CPUCL1_2_QCH_CLK, QCH_CON_HTU_CPUCL1_2_QCH_CLK_ENABLE, QCH_CON_HTU_CPUCL1_2_QCH_CLK_CLOCK_REQ, QCH_CON_HTU_CPUCL1_2_QCH_CLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(HTU_CPUCL1_2_QCH_PCLK, QCH_CON_HTU_CPUCL1_2_QCH_PCLK_ENABLE, QCH_CON_HTU_CPUCL1_2_QCH_PCLK_CLOCK_REQ, QCH_CON_HTU_CPUCL1_2_QCH_PCLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_ATB_SI_IT_DDCMID0_QCH, QCH_CON_LH_ATB_SI_IT_DDCMID0_QCH_ENABLE, QCH_CON_LH_ATB_SI_IT_DDCMID0_QCH_CLOCK_REQ, QCH_CON_LH_ATB_SI_IT_DDCMID0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_ATB_SI_IT_DDCMID1_QCH, QCH_CON_LH_ATB_SI_IT_DDCMID1_QCH_ENABLE, QCH_CON_LH_ATB_SI_IT_DDCMID1_QCH_CLOCK_REQ, QCH_CON_LH_ATB_SI_IT_DDCMID1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_ATB_SI_IT_DDCMID2_QCH, QCH_CON_LH_ATB_SI_IT_DDCMID2_QCH_ENABLE, QCH_CON_LH_ATB_SI_IT_DDCMID2_QCH_CLOCK_REQ, QCH_CON_LH_ATB_SI_IT_DDCMID2_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_CLK_CPUCL1_POWERIP_QCH, QCH_CON_RSTNSYNC_CLK_CPUCL1_POWERIP_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_CPUCL1_POWERIP_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_CPUCL1_POWERIP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_SR_CLK_CPUCL1_HTU_QCH, QCH_CON_RSTNSYNC_SR_CLK_CPUCL1_HTU_QCH_ENABLE, QCH_CON_RSTNSYNC_SR_CLK_CPUCL1_HTU_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_SR_CLK_CPUCL1_HTU_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_SR_CLK_CPUCL1_POWERIP_QCH, QCH_CON_RSTNSYNC_SR_CLK_CPUCL1_POWERIP_QCH_ENABLE, QCH_CON_RSTNSYNC_SR_CLK_CPUCL1_POWERIP_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_SR_CLK_CPUCL1_POWERIP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(STR_CPUCL0_1_QCH, DMYQCH_CON_STR_CPUCL0_1_QCH_ENABLE, DMYQCH_CON_STR_CPUCL0_1_QCH_CLOCK_REQ, DMYQCH_CON_STR_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(U_DDD_CTRL_CORE__CPUCL1_0_QCH, QCH_CON_U_DDD_CTRL_CORE__CPUCL1_0_QCH_ENABLE, QCH_CON_U_DDD_CTRL_CORE__CPUCL1_0_QCH_CLOCK_REQ, QCH_CON_U_DDD_CTRL_CORE__CPUCL1_0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(U_DDD_CTRL_CORE__CPUCL1_1_QCH, QCH_CON_U_DDD_CTRL_CORE__CPUCL1_1_QCH_ENABLE, QCH_CON_U_DDD_CTRL_CORE__CPUCL1_1_QCH_CLOCK_REQ, QCH_CON_U_DDD_CTRL_CORE__CPUCL1_1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(U_DDD_CTRL_CORE__CPUCL1_2_QCH, QCH_CON_U_DDD_CTRL_CORE__CPUCL1_2_QCH_ENABLE, QCH_CON_U_DDD_CTRL_CORE__CPUCL1_2_QCH_CLOCK_REQ, QCH_CON_U_DDD_CTRL_CORE__CPUCL1_2_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ADD_CPUCL0_2_QCH, DMYQCH_CON_ADD_CPUCL0_2_QCH_ENABLE, DMYQCH_CON_ADD_CPUCL0_2_QCH_CLOCK_REQ, DMYQCH_CON_ADD_CPUCL0_2_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(BUSIF_ADD_CPUCL0_2_QCH, QCH_CON_BUSIF_ADD_CPUCL0_2_QCH_ENABLE, QCH_CON_BUSIF_ADD_CPUCL0_2_QCH_CLOCK_REQ, QCH_CON_BUSIF_ADD_CPUCL0_2_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(BUSIF_STR_CPUCL0_2_QCH, QCH_CON_BUSIF_STR_CPUCL0_2_QCH_ENABLE, QCH_CON_BUSIF_STR_CPUCL0_2_QCH_CLOCK_REQ, QCH_CON_BUSIF_STR_CPUCL0_2_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(BUSIF_STR_CPUCL0_2_QCH_CORE, QCH_CON_BUSIF_STR_CPUCL0_2_QCH_CORE_ENABLE, QCH_CON_BUSIF_STR_CPUCL0_2_QCH_CORE_CLOCK_REQ, QCH_CON_BUSIF_STR_CPUCL0_2_QCH_CORE_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CMU_CPUCL2_CMUREF_QCH, DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH_CLOCK_REQ, DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CPUCL2_QCH_CORE7, QCH_CON_CPUCL2_QCH_CORE7_ENABLE, QCH_CON_CPUCL2_QCH_CORE7_CLOCK_REQ, QCH_CON_CPUCL2_QCH_CORE7_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CPUCL2_CMU_CPUCL2_QCH, QCH_CON_CPUCL2_CMU_CPUCL2_QCH_ENABLE, QCH_CON_CPUCL2_CMU_CPUCL2_QCH_CLOCK_REQ, QCH_CON_CPUCL2_CMU_CPUCL2_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(HTU_CPUCL2_QCH_PCLK, QCH_CON_HTU_CPUCL2_QCH_PCLK_ENABLE, QCH_CON_HTU_CPUCL2_QCH_PCLK_CLOCK_REQ, QCH_CON_HTU_CPUCL2_QCH_PCLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(HTU_CPUCL2_QCH_CLK, QCH_CON_HTU_CPUCL2_QCH_CLK_ENABLE, QCH_CON_HTU_CPUCL2_QCH_CLK_CLOCK_REQ, QCH_CON_HTU_CPUCL2_QCH_CLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_ATB_SI_IT_DDCBIG_QCH, QCH_CON_LH_ATB_SI_IT_DDCBIG_QCH_ENABLE, QCH_CON_LH_ATB_SI_IT_DDCBIG_QCH_CLOCK_REQ, QCH_CON_LH_ATB_SI_IT_DDCBIG_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_CLK_CPUCL2_POWERIP_QCH, QCH_CON_RSTNSYNC_CLK_CPUCL2_POWERIP_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_CPUCL2_POWERIP_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_CPUCL2_POWERIP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_SR_CLK_CPUCL2_HTU_QCH, QCH_CON_RSTNSYNC_SR_CLK_CPUCL2_HTU_QCH_ENABLE, QCH_CON_RSTNSYNC_SR_CLK_CPUCL2_HTU_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_SR_CLK_CPUCL2_HTU_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_SR_CLK_CPUCL2_POWERIP_QCH, QCH_CON_RSTNSYNC_SR_CLK_CPUCL2_POWERIP_QCH_ENABLE, QCH_CON_RSTNSYNC_SR_CLK_CPUCL2_POWERIP_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_SR_CLK_CPUCL2_POWERIP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(STR_CPUCL0_2_QCH, DMYQCH_CON_STR_CPUCL0_2_QCH_ENABLE, DMYQCH_CON_STR_CPUCL0_2_QCH_CLOCK_REQ, DMYQCH_CON_STR_CPUCL0_2_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(U_DDD_CTRL_CORE__CPUCL2_QCH, QCH_CON_U_DDD_CTRL_CORE__CPUCL2_QCH_ENABLE, QCH_CON_U_DDD_CTRL_CORE__CPUCL2_QCH_CLOCK_REQ, QCH_CON_U_DDD_CTRL_CORE__CPUCL2_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CSIS_CMU_CSIS_QCH, QCH_CON_CSIS_CMU_CSIS_QCH_ENABLE, QCH_CON_CSIS_CMU_CSIS_QCH_CLOCK_REQ, QCH_CON_CSIS_CMU_CSIS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(D_TZPC_CSIS_QCH, QCH_CON_D_TZPC_CSIS_QCH_ENABLE, QCH_CON_D_TZPC_CSIS_QCH_CLOCK_REQ, QCH_CON_D_TZPC_CSIS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_LP_INT_P0P1_CSIS_QCH, QCH_CON_LH_AXI_MI_LP_INT_P0P1_CSIS_QCH_ENABLE, QCH_CON_LH_AXI_MI_LP_INT_P0P1_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LP_INT_P0P1_CSIS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(MIPI_PHY_LINK_WRAP_QCH_CSIS0, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0_ENABLE, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0_CLOCK_REQ, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(MIPI_PHY_LINK_WRAP_QCH_CSIS1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1_ENABLE, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1_CLOCK_REQ, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(MIPI_PHY_LINK_WRAP_QCH_CSIS2, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2_ENABLE, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2_CLOCK_REQ, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(MIPI_PHY_LINK_WRAP_QCH_CSIS3, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3_ENABLE, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3_CLOCK_REQ, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(MIPI_PHY_LINK_WRAP_QCH_CSIS4, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4_ENABLE, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4_CLOCK_REQ, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(MIPI_PHY_LINK_WRAP_QCH_CSIS5, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5_ENABLE, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5_CLOCK_REQ, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(MIPI_PHY_LINK_WRAP_QCH_CSIS6, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS6_ENABLE, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS6_CLOCK_REQ, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS6_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(MIPI_PHY_LINK_WRAP_QCH_UFD, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_UFD_ENABLE, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_UFD_CLOCK_REQ, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_UFD_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_SI_OTF_CSISUFD_QCH, QCH_CON_SLH_AST_SI_OTF_CSISUFD_QCH_ENABLE, QCH_CON_SLH_AST_SI_OTF_CSISUFD_QCH_CLOCK_REQ, QCH_CON_SLH_AST_SI_OTF_CSISUFD_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_LP_UFDCSIS_QCH, QCH_CON_SLH_AXI_MI_LP_UFDCSIS_QCH_ENABLE, QCH_CON_SLH_AXI_MI_LP_UFDCSIS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_LP_UFDCSIS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_CSIS_QCH, QCH_CON_SYSREG_CSIS_QCH_ENABLE, QCH_CON_SYSREG_CSIS_QCH_CLOCK_REQ, QCH_CON_SYSREG_CSIS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CSTAT_CMU_CSTAT_QCH, QCH_CON_CSTAT_CMU_CSTAT_QCH_ENABLE, QCH_CON_CSTAT_CMU_CSTAT_QCH_CLOCK_REQ, QCH_CON_CSTAT_CMU_CSTAT_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(D_TZPC_CSTAT_QCH, QCH_CON_D_TZPC_CSTAT_QCH_ENABLE, QCH_CON_D_TZPC_CSTAT_QCH_CLOCK_REQ, QCH_CON_D_TZPC_CSTAT_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_MI_OTF0_CSISCSTAT_QCH, QCH_CON_LH_AST_MI_OTF0_CSISCSTAT_QCH_ENABLE, QCH_CON_LH_AST_MI_OTF0_CSISCSTAT_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_OTF0_CSISCSTAT_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_MI_OTF1_CSISCSTAT_QCH, QCH_CON_LH_AST_MI_OTF1_CSISCSTAT_QCH_ENABLE, QCH_CON_LH_AST_MI_OTF1_CSISCSTAT_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_OTF1_CSISCSTAT_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_MI_OTF2_CSISCSTAT_QCH, QCH_CON_LH_AST_MI_OTF2_CSISCSTAT_QCH_ENABLE, QCH_CON_LH_AST_MI_OTF2_CSISCSTAT_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_OTF2_CSISCSTAT_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_MI_OTF3_CSISCSTAT_QCH, QCH_CON_LH_AST_MI_OTF3_CSISCSTAT_QCH_ENABLE, QCH_CON_LH_AST_MI_OTF3_CSISCSTAT_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_OTF3_CSISCSTAT_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_D_CSTAT_QCH, QCH_CON_LH_AXI_SI_D_CSTAT_QCH_ENABLE, QCH_CON_LH_AXI_SI_D_CSTAT_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D_CSTAT_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_CSTAT_QCH, QCH_CON_PPMU_CSTAT_QCH_ENABLE, QCH_CON_PPMU_CSTAT_QCH_CLOCK_REQ, QCH_CON_PPMU_CSTAT_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SIPU_CSTAT_QCH, QCH_CON_SIPU_CSTAT_QCH_ENABLE, QCH_CON_SIPU_CSTAT_QCH_CLOCK_REQ, QCH_CON_SIPU_CSTAT_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SIPU_CSTAT_QCH_C2RD, QCH_CON_SIPU_CSTAT_QCH_C2RD_ENABLE, QCH_CON_SIPU_CSTAT_QCH_C2RD_CLOCK_REQ, QCH_CON_SIPU_CSTAT_QCH_C2RD_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SIPU_CSTAT_QCH_C2DS, QCH_CON_SIPU_CSTAT_QCH_C2DS_ENABLE, QCH_CON_SIPU_CSTAT_QCH_C2DS_CLOCK_REQ, QCH_CON_SIPU_CSTAT_QCH_C2DS_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_SI_G_PPMU_CSTAT_QCH, QCH_CON_SLH_AST_SI_G_PPMU_CSTAT_QCH_ENABLE, QCH_CON_SLH_AST_SI_G_PPMU_CSTAT_QCH_CLOCK_REQ, QCH_CON_SLH_AST_SI_G_PPMU_CSTAT_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_P_CSTAT_QCH, QCH_CON_SLH_AXI_MI_P_CSTAT_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_CSTAT_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_CSTAT_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D_CSTAT_QCH_S1, QCH_CON_SYSMMU_D_CSTAT_QCH_S1_ENABLE, QCH_CON_SYSMMU_D_CSTAT_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D_CSTAT_QCH_S1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D_CSTAT_QCH_S2, QCH_CON_SYSMMU_D_CSTAT_QCH_S2_ENABLE, QCH_CON_SYSMMU_D_CSTAT_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D_CSTAT_QCH_S2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_CSTAT_QCH, QCH_CON_SYSREG_CSTAT_QCH_ENABLE, QCH_CON_SYSREG_CSTAT_QCH_CLOCK_REQ, QCH_CON_SYSREG_CSTAT_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(VGEN_LITE_CSTAT0_QCH, QCH_CON_VGEN_LITE_CSTAT0_QCH_ENABLE, QCH_CON_VGEN_LITE_CSTAT0_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_CSTAT0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(VGEN_LITE_CSTAT1_QCH, QCH_CON_VGEN_LITE_CSTAT1_QCH_ENABLE, QCH_CON_VGEN_LITE_CSTAT1_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_CSTAT1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(APBIF_S2D_DBGCORE_QCH, QCH_CON_APBIF_S2D_DBGCORE_QCH_ENABLE, QCH_CON_APBIF_S2D_DBGCORE_QCH_CLOCK_REQ, QCH_CON_APBIF_S2D_DBGCORE_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ASYNCAHBMASTER_DBGCORE_QCH, QCH_CON_ASYNCAHBMASTER_DBGCORE_QCH_ENABLE, QCH_CON_ASYNCAHBMASTER_DBGCORE_QCH_CLOCK_REQ, QCH_CON_ASYNCAHBMASTER_DBGCORE_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DBGCORE_CMU_DBGCORE_QCH, QCH_CON_DBGCORE_CMU_DBGCORE_QCH_ENABLE, QCH_CON_DBGCORE_CMU_DBGCORE_QCH_CLOCK_REQ, QCH_CON_DBGCORE_CMU_DBGCORE_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(D_TZPC_DBGCORE_QCH, QCH_CON_D_TZPC_DBGCORE_QCH_ENABLE, QCH_CON_D_TZPC_DBGCORE_QCH_CLOCK_REQ, QCH_CON_D_TZPC_DBGCORE_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(GREBEINTEGRATION_DBGCORE_QCH_DBG, QCH_CON_GREBEINTEGRATION_DBGCORE_QCH_DBG_ENABLE, QCH_CON_GREBEINTEGRATION_DBGCORE_QCH_DBG_CLOCK_REQ, QCH_CON_GREBEINTEGRATION_DBGCORE_QCH_DBG_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(GREBEINTEGRATION_DBGCORE_QCH_GREBE, QCH_CON_GREBEINTEGRATION_DBGCORE_QCH_GREBE_ENABLE, QCH_CON_GREBEINTEGRATION_DBGCORE_QCH_GREBE_CLOCK_REQ, QCH_CON_GREBEINTEGRATION_DBGCORE_QCH_GREBE_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(MDIS_DBGCORE_QCH, QCH_CON_MDIS_DBGCORE_QCH_ENABLE, QCH_CON_MDIS_DBGCORE_QCH_CLOCK_REQ, QCH_CON_MDIS_DBGCORE_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(MDIS_DBGCORE_QCH_OSC, QCH_CON_MDIS_DBGCORE_QCH_OSC_ENABLE, QCH_CON_MDIS_DBGCORE_QCH_OSC_CLOCK_REQ, QCH_CON_MDIS_DBGCORE_QCH_OSC_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_CLK_DBGCORE_GREBE_QCH, QCH_CON_RSTNSYNC_CLK_DBGCORE_GREBE_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_DBGCORE_GREBE_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_DBGCORE_GREBE_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_IP_APM_QCH, QCH_CON_SLH_AXI_MI_IP_APM_QCH_ENABLE, QCH_CON_SLH_AXI_MI_IP_APM_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_IP_APM_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_G_DBGCORE_QCH, QCH_CON_SLH_AXI_SI_G_DBGCORE_QCH_ENABLE, QCH_CON_SLH_AXI_SI_G_DBGCORE_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_G_DBGCORE_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_G_SCAN2DRAM_QCH, QCH_CON_SLH_AXI_SI_G_SCAN2DRAM_QCH_ENABLE, QCH_CON_SLH_AXI_SI_G_SCAN2DRAM_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_G_SCAN2DRAM_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_ID_DBGCORE_QCH, QCH_CON_SLH_AXI_SI_ID_DBGCORE_QCH_ENABLE, QCH_CON_SLH_AXI_SI_ID_DBGCORE_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_ID_DBGCORE_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_DBGCORE_QCH, QCH_CON_SYSREG_DBGCORE_QCH_ENABLE, QCH_CON_SYSREG_DBGCORE_QCH_CLOCK_REQ, QCH_CON_SYSREG_DBGCORE_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_DBGCORE_CORE_QCH, QCH_CON_SYSREG_DBGCORE_CORE_QCH_ENABLE, QCH_CON_SYSREG_DBGCORE_CORE_QCH_CLOCK_REQ, QCH_CON_SYSREG_DBGCORE_CORE_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(WDT_DBGCORE_QCH, QCH_CON_WDT_DBGCORE_QCH_ENABLE, QCH_CON_WDT_DBGCORE_QCH_CLOCK_REQ, QCH_CON_WDT_DBGCORE_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ADD_DNC_QCH, DMYQCH_CON_ADD_DNC_QCH_ENABLE, DMYQCH_CON_ADD_DNC_QCH_CLOCK_REQ, DMYQCH_CON_ADD_DNC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ADM_DAP_DNC_QCH, DMYQCH_CON_ADM_DAP_DNC_QCH_ENABLE, DMYQCH_CON_ADM_DAP_DNC_QCH_CLOCK_REQ, DMYQCH_CON_ADM_DAP_DNC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(BAAW_DNCCHUBVTS_QCH, QCH_CON_BAAW_DNCCHUBVTS_QCH_ENABLE, QCH_CON_BAAW_DNCCHUBVTS_QCH_CLOCK_REQ, QCH_CON_BAAW_DNCCHUBVTS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(BUSIF_ADD_DNC_QCH, QCH_CON_BUSIF_ADD_DNC_QCH_ENABLE, QCH_CON_BUSIF_ADD_DNC_QCH_CLOCK_REQ, QCH_CON_BUSIF_ADD_DNC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(BUSIF_DDD_DNC_QCH, QCH_CON_BUSIF_DDD_DNC_QCH_ENABLE, QCH_CON_BUSIF_DDD_DNC_QCH_CLOCK_REQ, QCH_CON_BUSIF_DDD_DNC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DNC_CMU_DNC_QCH, QCH_CON_DNC_CMU_DNC_QCH_ENABLE, QCH_CON_DNC_CMU_DNC_QCH_CLOCK_REQ, QCH_CON_DNC_CMU_DNC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(D_TZPC_DNC_QCH, QCH_CON_D_TZPC_DNC_QCH_ENABLE, QCH_CON_D_TZPC_DNC_QCH_CLOCK_REQ, QCH_CON_D_TZPC_DNC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(HTU_DNC_QCH_PCLK, QCH_CON_HTU_DNC_QCH_PCLK_ENABLE, QCH_CON_HTU_DNC_QCH_PCLK_CLOCK_REQ, QCH_CON_HTU_DNC_QCH_PCLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(HTU_DNC_QCH_CLK, QCH_CON_HTU_DNC_QCH_CLK_ENABLE, QCH_CON_HTU_DNC_QCH_CLK_CLOCK_REQ, QCH_CON_HTU_DNC_QCH_CLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(IP_DNC_QCH, QCH_CON_IP_DNC_QCH_ENABLE, QCH_CON_IP_DNC_QCH_CLOCK_REQ, QCH_CON_IP_DNC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_MI_OTF_UFDDNC_QCH, QCH_CON_LH_AST_MI_OTF_UFDDNC_QCH_ENABLE, QCH_CON_LH_AST_MI_OTF_UFDDNC_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_OTF_UFDDNC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_LD_DSP0DNC_SFR_QCH, QCH_CON_LH_AXI_MI_LD_DSP0DNC_SFR_QCH_ENABLE, QCH_CON_LH_AXI_MI_LD_DSP0DNC_SFR_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LD_DSP0DNC_SFR_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_LD_DSP0DNC_SHMEM_QCH, QCH_CON_LH_AXI_MI_LD_DSP0DNC_SHMEM_QCH_ENABLE, QCH_CON_LH_AXI_MI_LD_DSP0DNC_SHMEM_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LD_DSP0DNC_SHMEM_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_LD_GNPU0DNC_SHMEM_QCH, QCH_CON_LH_AXI_MI_LD_GNPU0DNC_SHMEM_QCH_ENABLE, QCH_CON_LH_AXI_MI_LD_GNPU0DNC_SHMEM_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LD_GNPU0DNC_SHMEM_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_LD_GNPU1DNC_SHMEM_QCH, QCH_CON_LH_AXI_MI_LD_GNPU1DNC_SHMEM_QCH_ENABLE, QCH_CON_LH_AXI_MI_LD_GNPU1DNC_SHMEM_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LD_GNPU1DNC_SHMEM_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_LD_RQ_GNPU0_QCH, QCH_CON_LH_AXI_MI_LD_RQ_GNPU0_QCH_ENABLE, QCH_CON_LH_AXI_MI_LD_RQ_GNPU0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LD_RQ_GNPU0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_LD_RQ_GNPU1_QCH, QCH_CON_LH_AXI_MI_LD_RQ_GNPU1_QCH_ENABLE, QCH_CON_LH_AXI_MI_LD_RQ_GNPU1_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LD_RQ_GNPU1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_LD_SDMADNC_DATA0_QCH, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA0_QCH_ENABLE, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_LD_SDMADNC_DATA1_QCH, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA1_QCH_ENABLE, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA1_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_LD_SDMADNC_DATA2_QCH, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA2_QCH_ENABLE, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA2_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA2_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_LD_SDMADNC_DATA3_QCH, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA3_QCH_ENABLE, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA3_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA3_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_LD_SDMADNC_DATA4_QCH, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA4_QCH_ENABLE, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA4_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA4_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_LD_SDMADNC_DATA5_QCH, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA5_QCH_ENABLE, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA5_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA5_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_LD_SDMADNC_DATA6_QCH, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA6_QCH_ENABLE, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA6_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA6_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_LD_SDMADNC_DATA7_QCH, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA7_QCH_ENABLE, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA7_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA7_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_LD_SDMADNC_MMU0_QCH, QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU0_QCH_ENABLE, QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_LD_SDMADNC_MMU1_QCH, QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU1_QCH_ENABLE, QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU1_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_LD_SDMADNC_MMU2_QCH, QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU2_QCH_ENABLE, QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU2_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU2_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_LD_SDMADNC_MMU3_QCH, QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU3_QCH_ENABLE, QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU3_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU3_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_LP_IPDNC_QCH, QCH_CON_LH_AXI_MI_LP_IPDNC_QCH_ENABLE, QCH_CON_LH_AXI_MI_LP_IPDNC_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LP_IPDNC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_LD0_GNPU0_QCH, QCH_CON_LH_AXI_SI_LD0_GNPU0_QCH_ENABLE, QCH_CON_LH_AXI_SI_LD0_GNPU0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LD0_GNPU0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_LD0_GNPU1_QCH, QCH_CON_LH_AXI_SI_LD0_GNPU1_QCH_ENABLE, QCH_CON_LH_AXI_SI_LD0_GNPU1_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LD0_GNPU1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_LD1_GNPU0_QCH, QCH_CON_LH_AXI_SI_LD1_GNPU0_QCH_ENABLE, QCH_CON_LH_AXI_SI_LD1_GNPU0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LD1_GNPU0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_LD1_GNPU1_QCH, QCH_CON_LH_AXI_SI_LD1_GNPU1_QCH_ENABLE, QCH_CON_LH_AXI_SI_LD1_GNPU1_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LD1_GNPU1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_LD_CTRL_GNPU0_QCH, QCH_CON_LH_AXI_SI_LD_CTRL_GNPU0_QCH_ENABLE, QCH_CON_LH_AXI_SI_LD_CTRL_GNPU0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LD_CTRL_GNPU0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_LD_CTRL_GNPU1_QCH, QCH_CON_LH_AXI_SI_LD_CTRL_GNPU1_QCH_ENABLE, QCH_CON_LH_AXI_SI_LD_CTRL_GNPU1_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LD_CTRL_GNPU1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_LD_DNCDSP0_DMA_QCH, QCH_CON_LH_AXI_SI_LD_DNCDSP0_DMA_QCH_ENABLE, QCH_CON_LH_AXI_SI_LD_DNCDSP0_DMA_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LD_DNCDSP0_DMA_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_LD_DNCDSP0_SFR_QCH, QCH_CON_LH_AXI_SI_LD_DNCDSP0_SFR_QCH_ENABLE, QCH_CON_LH_AXI_SI_LD_DNCDSP0_SFR_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LD_DNCDSP0_SFR_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_LP_DNCSDMA_QCH, QCH_CON_LH_AXI_SI_LP_DNCSDMA_QCH_ENABLE, QCH_CON_LH_AXI_SI_LP_DNCSDMA_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LP_DNCSDMA_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_LP_IPDNC_QCH, QCH_CON_LH_AXI_SI_LP_IPDNC_QCH_ENABLE, QCH_CON_LH_AXI_SI_LP_IPDNC_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LP_IPDNC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_IPDNC_QCH, QCH_CON_PPMU_IPDNC_QCH_ENABLE, QCH_CON_PPMU_IPDNC_QCH_CLOCK_REQ, QCH_CON_PPMU_IPDNC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_SDMA0_QCH, QCH_CON_PPMU_SDMA0_QCH_ENABLE, QCH_CON_PPMU_SDMA0_QCH_CLOCK_REQ, QCH_CON_PPMU_SDMA0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_SDMA1_QCH, QCH_CON_PPMU_SDMA1_QCH_ENABLE, QCH_CON_PPMU_SDMA1_QCH_CLOCK_REQ, QCH_CON_PPMU_SDMA1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_SDMA2_QCH, QCH_CON_PPMU_SDMA2_QCH_ENABLE, QCH_CON_PPMU_SDMA2_QCH_CLOCK_REQ, QCH_CON_PPMU_SDMA2_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_SDMA3_QCH, QCH_CON_PPMU_SDMA3_QCH_ENABLE, QCH_CON_PPMU_SDMA3_QCH_CLOCK_REQ, QCH_CON_PPMU_SDMA3_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SIU_G_PPMU_DNC_QCH, QCH_CON_SIU_G_PPMU_DNC_QCH_ENABLE, QCH_CON_SIU_G_PPMU_DNC_QCH_CLOCK_REQ, QCH_CON_SIU_G_PPMU_DNC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_SI_G_PPMU_DNC_QCH, QCH_CON_SLH_AST_SI_G_PPMU_DNC_QCH_ENABLE, QCH_CON_SLH_AST_SI_G_PPMU_DNC_QCH_CLOCK_REQ, QCH_CON_SLH_AST_SI_G_PPMU_DNC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_LD_CMDQ_GNPU0_QCH, QCH_CON_SLH_AXI_MI_LD_CMDQ_GNPU0_QCH_ENABLE, QCH_CON_SLH_AXI_MI_LD_CMDQ_GNPU0_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_LD_CMDQ_GNPU0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_LD_CMDQ_GNPU1_QCH, QCH_CON_SLH_AXI_MI_LD_CMDQ_GNPU1_QCH_ENABLE, QCH_CON_SLH_AXI_MI_LD_CMDQ_GNPU1_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_LD_CMDQ_GNPU1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_LD_DSP0DNC_CACHE_QCH, QCH_CON_SLH_AXI_MI_LD_DSP0DNC_CACHE_QCH_ENABLE, QCH_CON_SLH_AXI_MI_LD_DSP0DNC_CACHE_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_LD_DSP0DNC_CACHE_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_LD_UFDDNC_QCH, QCH_CON_SLH_AXI_MI_LD_UFDDNC_QCH_ENABLE, QCH_CON_SLH_AXI_MI_LD_UFDDNC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_LD_UFDDNC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_LP_ALIVEDNC_QCH, QCH_CON_SLH_AXI_MI_LP_ALIVEDNC_QCH_ENABLE, QCH_CON_SLH_AXI_MI_LP_ALIVEDNC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_LP_ALIVEDNC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_P_DNC_QCH, QCH_CON_SLH_AXI_MI_P_DNC_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_DNC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_DNC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_LP_DNCCHUBVTS_QCH, QCH_CON_SLH_AXI_SI_LP_DNCCHUBVTS_QCH_ENABLE, QCH_CON_SLH_AXI_SI_LP_DNCCHUBVTS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_LP_DNCCHUBVTS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_LP_DSP0_QCH, QCH_CON_SLH_AXI_SI_LP_DSP0_QCH_ENABLE, QCH_CON_SLH_AXI_SI_LP_DSP0_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_LP_DSP0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_LP_GNPU0_QCH, QCH_CON_SLH_AXI_SI_LP_GNPU0_QCH_ENABLE, QCH_CON_SLH_AXI_SI_LP_GNPU0_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_LP_GNPU0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_LP_GNPU1_QCH, QCH_CON_SLH_AXI_SI_LP_GNPU1_QCH_ENABLE, QCH_CON_SLH_AXI_SI_LP_GNPU1_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_LP_GNPU1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_LP_SDMA_QCH, QCH_CON_SLH_AXI_SI_LP_SDMA_QCH_ENABLE, QCH_CON_SLH_AXI_SI_LP_SDMA_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_LP_SDMA_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_IPDNC_QCH_S1, QCH_CON_SYSMMU_IPDNC_QCH_S1_ENABLE, QCH_CON_SYSMMU_IPDNC_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_IPDNC_QCH_S1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_IPDNC_QCH_S2, QCH_CON_SYSMMU_IPDNC_QCH_S2_ENABLE, QCH_CON_SYSMMU_IPDNC_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_IPDNC_QCH_S2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_SDMA0_QCH_S1, QCH_CON_SYSMMU_SDMA0_QCH_S1_ENABLE, QCH_CON_SYSMMU_SDMA0_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_SDMA0_QCH_S1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_SDMA0_QCH_S2, QCH_CON_SYSMMU_SDMA0_QCH_S2_ENABLE, QCH_CON_SYSMMU_SDMA0_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_SDMA0_QCH_S2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_SDMA1_QCH_S1, QCH_CON_SYSMMU_SDMA1_QCH_S1_ENABLE, QCH_CON_SYSMMU_SDMA1_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_SDMA1_QCH_S1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_SDMA1_QCH_S2, QCH_CON_SYSMMU_SDMA1_QCH_S2_ENABLE, QCH_CON_SYSMMU_SDMA1_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_SDMA1_QCH_S2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_SDMA2_QCH_S1, QCH_CON_SYSMMU_SDMA2_QCH_S1_ENABLE, QCH_CON_SYSMMU_SDMA2_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_SDMA2_QCH_S1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_SDMA2_QCH_S2, QCH_CON_SYSMMU_SDMA2_QCH_S2_ENABLE, QCH_CON_SYSMMU_SDMA2_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_SDMA2_QCH_S2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_SDMA3_QCH_S1, QCH_CON_SYSMMU_SDMA3_QCH_S1_ENABLE, QCH_CON_SYSMMU_SDMA3_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_SDMA3_QCH_S1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_SDMA3_QCH_S2, QCH_CON_SYSMMU_SDMA3_QCH_S2_ENABLE, QCH_CON_SYSMMU_SDMA3_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_SDMA3_QCH_S2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_DNC_QCH, QCH_CON_SYSREG_DNC_QCH_ENABLE, QCH_CON_SYSREG_DNC_QCH_CLOCK_REQ, QCH_CON_SYSREG_DNC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(TREX_D_DNC_QCH, QCH_CON_TREX_D_DNC_QCH_ENABLE, QCH_CON_TREX_D_DNC_QCH_CLOCK_REQ, QCH_CON_TREX_D_DNC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(VGEN_DNC_QCH, QCH_CON_VGEN_DNC_QCH_ENABLE, QCH_CON_VGEN_DNC_QCH_CLOCK_REQ, QCH_CON_VGEN_DNC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(VGEN_LITE_DNC_QCH, QCH_CON_VGEN_LITE_DNC_QCH_ENABLE, QCH_CON_VGEN_LITE_DNC_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_DNC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DPUB_QCH_DECON, QCH_CON_DPUB_QCH_DECON_ENABLE, QCH_CON_DPUB_QCH_DECON_CLOCK_REQ, QCH_CON_DPUB_QCH_DECON_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DPUB_QCH_ALV_DSIM0, QCH_CON_DPUB_QCH_ALV_DSIM0_ENABLE, QCH_CON_DPUB_QCH_ALV_DSIM0_CLOCK_REQ, QCH_CON_DPUB_QCH_ALV_DSIM0_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DPUB_QCH_ALV_DSIM1, QCH_CON_DPUB_QCH_ALV_DSIM1_ENABLE, QCH_CON_DPUB_QCH_ALV_DSIM1_CLOCK_REQ, QCH_CON_DPUB_QCH_ALV_DSIM1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DPUB_QCH_ALV_DSIM2, QCH_CON_DPUB_QCH_ALV_DSIM2_ENABLE, QCH_CON_DPUB_QCH_ALV_DSIM2_CLOCK_REQ, QCH_CON_DPUB_QCH_ALV_DSIM2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DPUB_QCH_OSC_DSIM0, QCH_CON_DPUB_QCH_OSC_DSIM0_ENABLE, QCH_CON_DPUB_QCH_OSC_DSIM0_CLOCK_REQ, QCH_CON_DPUB_QCH_OSC_DSIM0_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DPUB_QCH_OSC_DSIM1, QCH_CON_DPUB_QCH_OSC_DSIM1_ENABLE, QCH_CON_DPUB_QCH_OSC_DSIM1_CLOCK_REQ, QCH_CON_DPUB_QCH_OSC_DSIM1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DPUB_QCH_OSC_DSIM2, QCH_CON_DPUB_QCH_OSC_DSIM2_ENABLE, QCH_CON_DPUB_QCH_OSC_DSIM2_CLOCK_REQ, QCH_CON_DPUB_QCH_OSC_DSIM2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DPUB_CMU_DPUB_QCH, QCH_CON_DPUB_CMU_DPUB_QCH_ENABLE, QCH_CON_DPUB_CMU_DPUB_QCH_CLOCK_REQ, QCH_CON_DPUB_CMU_DPUB_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(D_TZPC_DPUB_QCH, QCH_CON_D_TZPC_DPUB_QCH_ENABLE, QCH_CON_D_TZPC_DPUB_QCH_CLOCK_REQ, QCH_CON_D_TZPC_DPUB_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_P_DPUB_QCH, QCH_CON_SLH_AXI_MI_P_DPUB_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_DPUB_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_DPUB_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_DPUB_QCH, QCH_CON_SYSREG_DPUB_QCH_ENABLE, QCH_CON_SYSREG_DPUB_QCH_CLOCK_REQ, QCH_CON_SYSREG_DPUB_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(UPI_M0_QCH, QCH_CON_UPI_M0_QCH_ENABLE, QCH_CON_UPI_M0_QCH_CLOCK_REQ, QCH_CON_UPI_M0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DPUF_QCH_DPUF0, QCH_CON_DPUF_QCH_DPUF0_ENABLE, QCH_CON_DPUF_QCH_DPUF0_CLOCK_REQ, QCH_CON_DPUF_QCH_DPUF0_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DPUF_QCH_VOTF0, QCH_CON_DPUF_QCH_VOTF0_ENABLE, QCH_CON_DPUF_QCH_VOTF0_CLOCK_REQ, QCH_CON_DPUF_QCH_VOTF0_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DPUF_QCH_DPUF1, QCH_CON_DPUF_QCH_DPUF1_ENABLE, QCH_CON_DPUF_QCH_DPUF1_CLOCK_REQ, QCH_CON_DPUF_QCH_DPUF1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DPUF_QCH_VOTF1, QCH_CON_DPUF_QCH_VOTF1_ENABLE, QCH_CON_DPUF_QCH_VOTF1_CLOCK_REQ, QCH_CON_DPUF_QCH_VOTF1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DPUF_QCH_SRAMC, QCH_CON_DPUF_QCH_SRAMC_ENABLE, QCH_CON_DPUF_QCH_SRAMC_CLOCK_REQ, QCH_CON_DPUF_QCH_SRAMC_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DPUF_CMU_DPUF_QCH, QCH_CON_DPUF_CMU_DPUF_QCH_ENABLE, QCH_CON_DPUF_CMU_DPUF_QCH_CLOCK_REQ, QCH_CON_DPUF_CMU_DPUF_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(D_TZPC_DPUF_QCH, QCH_CON_D_TZPC_DPUF_QCH_ENABLE, QCH_CON_D_TZPC_DPUF_QCH_CLOCK_REQ, QCH_CON_D_TZPC_DPUF_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(D_TZPC_DPUF1_QCH, QCH_CON_D_TZPC_DPUF1_QCH_ENABLE, QCH_CON_D_TZPC_DPUF1_QCH_CLOCK_REQ, QCH_CON_D_TZPC_DPUF1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_D1_DPUF_QCH, QCH_CON_LH_AXI_SI_D1_DPUF_QCH_ENABLE, QCH_CON_LH_AXI_SI_D1_DPUF_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D1_DPUF_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_D0_DPUF0_QCH, QCH_CON_PPMU_D0_DPUF0_QCH_ENABLE, QCH_CON_PPMU_D0_DPUF0_QCH_CLOCK_REQ, QCH_CON_PPMU_D0_DPUF0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_D0_DPUF1_QCH, QCH_CON_PPMU_D0_DPUF1_QCH_ENABLE, QCH_CON_PPMU_D0_DPUF1_QCH_CLOCK_REQ, QCH_CON_PPMU_D0_DPUF1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_D1_DPUF0_QCH, QCH_CON_PPMU_D1_DPUF0_QCH_ENABLE, QCH_CON_PPMU_D1_DPUF0_QCH_CLOCK_REQ, QCH_CON_PPMU_D1_DPUF0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_D1_DPUF1_QCH, QCH_CON_PPMU_D1_DPUF1_QCH_ENABLE, QCH_CON_PPMU_D1_DPUF1_QCH_CLOCK_REQ, QCH_CON_PPMU_D1_DPUF1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SIU_DPUF_QCH, QCH_CON_SIU_DPUF_QCH_ENABLE, QCH_CON_SIU_DPUF_QCH_CLOCK_REQ, QCH_CON_SIU_DPUF_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_SI_G_PPMU_DPUF_QCH, QCH_CON_SLH_AST_SI_G_PPMU_DPUF_QCH_ENABLE, QCH_CON_SLH_AST_SI_G_PPMU_DPUF_QCH_CLOCK_REQ, QCH_CON_SLH_AST_SI_G_PPMU_DPUF_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_P_DPUF_QCH, QCH_CON_SLH_AXI_MI_P_DPUF_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_DPUF_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_DPUF_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_D0_DPUF_QCH, QCH_CON_SLH_AXI_SI_D0_DPUF_QCH_ENABLE, QCH_CON_SLH_AXI_SI_D0_DPUF_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_D0_DPUF_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D0_DPUF0_QCH_S1, QCH_CON_SYSMMU_D0_DPUF0_QCH_S1_ENABLE, QCH_CON_SYSMMU_D0_DPUF0_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D0_DPUF0_QCH_S1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D0_DPUF0_QCH_S2, QCH_CON_SYSMMU_D0_DPUF0_QCH_S2_ENABLE, QCH_CON_SYSMMU_D0_DPUF0_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D0_DPUF0_QCH_S2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D0_DPUF1_QCH_S1, QCH_CON_SYSMMU_D0_DPUF1_QCH_S1_ENABLE, QCH_CON_SYSMMU_D0_DPUF1_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D0_DPUF1_QCH_S1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D0_DPUF1_QCH_S2, QCH_CON_SYSMMU_D0_DPUF1_QCH_S2_ENABLE, QCH_CON_SYSMMU_D0_DPUF1_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D0_DPUF1_QCH_S2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D1_DPUF0_QCH_S1, QCH_CON_SYSMMU_D1_DPUF0_QCH_S1_ENABLE, QCH_CON_SYSMMU_D1_DPUF0_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D1_DPUF0_QCH_S1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D1_DPUF0_QCH_S2, QCH_CON_SYSMMU_D1_DPUF0_QCH_S2_ENABLE, QCH_CON_SYSMMU_D1_DPUF0_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D1_DPUF0_QCH_S2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D1_DPUF1_QCH_S1, QCH_CON_SYSMMU_D1_DPUF1_QCH_S1_ENABLE, QCH_CON_SYSMMU_D1_DPUF1_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D1_DPUF1_QCH_S1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D1_DPUF1_QCH_S2, QCH_CON_SYSMMU_D1_DPUF1_QCH_S2_ENABLE, QCH_CON_SYSMMU_D1_DPUF1_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D1_DPUF1_QCH_S2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_DPUF_QCH, QCH_CON_SYSREG_DPUF_QCH_ENABLE, QCH_CON_SYSREG_DPUF_QCH_CLOCK_REQ, QCH_CON_SYSREG_DPUF_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DPUF1_QCH_DPUF, QCH_CON_DPUF1_QCH_DPUF_ENABLE, QCH_CON_DPUF1_QCH_DPUF_CLOCK_REQ, QCH_CON_DPUF1_QCH_DPUF_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DPUF1_QCH_VOTF, QCH_CON_DPUF1_QCH_VOTF_ENABLE, QCH_CON_DPUF1_QCH_VOTF_CLOCK_REQ, QCH_CON_DPUF1_QCH_VOTF_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DPUF1_CMU_DPUF1_QCH, QCH_CON_DPUF1_CMU_DPUF1_QCH_ENABLE, QCH_CON_DPUF1_CMU_DPUF1_QCH_CLOCK_REQ, QCH_CON_DPUF1_CMU_DPUF1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_D0_DPUF1DPUF0_QCH, QCH_CON_LH_AXI_SI_D0_DPUF1DPUF0_QCH_ENABLE, QCH_CON_LH_AXI_SI_D0_DPUF1DPUF0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D0_DPUF1DPUF0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_D1_DPUF1DPUF0_QCH, QCH_CON_LH_AXI_SI_D1_DPUF1DPUF0_QCH_ENABLE, QCH_CON_LH_AXI_SI_D1_DPUF1DPUF0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D1_DPUF1DPUF0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_DPUF1D0_QCH, QCH_CON_PPMU_DPUF1D0_QCH_ENABLE, QCH_CON_PPMU_DPUF1D0_QCH_CLOCK_REQ, QCH_CON_PPMU_DPUF1D0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_DPUF1D1_QCH, QCH_CON_PPMU_DPUF1D1_QCH_ENABLE, QCH_CON_PPMU_DPUF1D1_QCH_CLOCK_REQ, QCH_CON_PPMU_DPUF1D1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SIU_DPUF1_QCH, QCH_CON_SIU_DPUF1_QCH_ENABLE, QCH_CON_SIU_DPUF1_QCH_CLOCK_REQ, QCH_CON_SIU_DPUF1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_ASTL_SI_G_PPMU_DPUF1_QCH, QCH_CON_SLH_ASTL_SI_G_PPMU_DPUF1_QCH_ENABLE, QCH_CON_SLH_ASTL_SI_G_PPMU_DPUF1_QCH_CLOCK_REQ, QCH_CON_SLH_ASTL_SI_G_PPMU_DPUF1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_P_DPUF1_QCH, QCH_CON_SLH_AXI_MI_P_DPUF1_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_DPUF1_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_DPUF1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_DPUF1D0_QCH_S1, QCH_CON_SYSMMU_DPUF1D0_QCH_S1_ENABLE, QCH_CON_SYSMMU_DPUF1D0_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_DPUF1D0_QCH_S1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_DPUF1D0_QCH_S2, QCH_CON_SYSMMU_DPUF1D0_QCH_S2_ENABLE, QCH_CON_SYSMMU_DPUF1D0_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_DPUF1D0_QCH_S2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_DPUF1D1_QCH_S1, QCH_CON_SYSMMU_DPUF1D1_QCH_S1_ENABLE, QCH_CON_SYSMMU_DPUF1D1_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_DPUF1D1_QCH_S1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_DPUF1D1_QCH_S2, QCH_CON_SYSMMU_DPUF1D1_QCH_S2_ENABLE, QCH_CON_SYSMMU_DPUF1D1_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_DPUF1D1_QCH_S2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_DPUF1_QCH, QCH_CON_SYSREG_DPUF1_QCH_ENABLE, QCH_CON_SYSREG_DPUF1_QCH_CLOCK_REQ, QCH_CON_SYSREG_DPUF1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DRCP_QCH, QCH_CON_DRCP_QCH_ENABLE, QCH_CON_DRCP_QCH_CLOCK_REQ, QCH_CON_DRCP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DRCP_CMU_DRCP_QCH, QCH_CON_DRCP_CMU_DRCP_QCH_ENABLE, QCH_CON_DRCP_CMU_DRCP_QCH_CLOCK_REQ, QCH_CON_DRCP_CMU_DRCP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(D_TZPC_DRCP_QCH, QCH_CON_D_TZPC_DRCP_QCH_ENABLE, QCH_CON_D_TZPC_DRCP_QCH_CLOCK_REQ, QCH_CON_D_TZPC_DRCP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_MI_OTF_YUVPDRCP_QCH, QCH_CON_LH_AST_MI_OTF_YUVPDRCP_QCH_ENABLE, QCH_CON_LH_AST_MI_OTF_YUVPDRCP_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_OTF_YUVPDRCP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_SI_OTF_DRCPMCSC_QCH, QCH_CON_LH_AST_SI_OTF_DRCPMCSC_QCH_ENABLE, QCH_CON_LH_AST_SI_OTF_DRCPMCSC_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_OTF_DRCPMCSC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_D_DRCP_QCH, QCH_CON_LH_AXI_SI_D_DRCP_QCH_ENABLE, QCH_CON_LH_AXI_SI_D_DRCP_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D_DRCP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_D_DRCP_QCH, QCH_CON_PPMU_D_DRCP_QCH_ENABLE, QCH_CON_PPMU_D_DRCP_QCH_CLOCK_REQ, QCH_CON_PPMU_D_DRCP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_ASTL_SI_G_PPMU_DRCP_QCH, QCH_CON_SLH_ASTL_SI_G_PPMU_DRCP_QCH_ENABLE, QCH_CON_SLH_ASTL_SI_G_PPMU_DRCP_QCH_CLOCK_REQ, QCH_CON_SLH_ASTL_SI_G_PPMU_DRCP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_P_DRCP_QCH, QCH_CON_SLH_AXI_MI_P_DRCP_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_DRCP_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_DRCP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D_DRCP_QCH_S2, QCH_CON_SYSMMU_D_DRCP_QCH_S2_ENABLE, QCH_CON_SYSMMU_D_DRCP_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D_DRCP_QCH_S2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D_DRCP_QCH_S1, QCH_CON_SYSMMU_D_DRCP_QCH_S1_ENABLE, QCH_CON_SYSMMU_D_DRCP_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D_DRCP_QCH_S1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_DRCP_QCH, QCH_CON_SYSREG_DRCP_QCH_ENABLE, QCH_CON_SYSREG_DRCP_QCH_CLOCK_REQ, QCH_CON_SYSREG_DRCP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(VGEN_LITE_D_DRCP_QCH, QCH_CON_VGEN_LITE_D_DRCP_QCH_ENABLE, QCH_CON_VGEN_LITE_D_DRCP_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_D_DRCP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DSP_CMU_DSP_QCH, QCH_CON_DSP_CMU_DSP_QCH_ENABLE, QCH_CON_DSP_CMU_DSP_QCH_CLOCK_REQ, QCH_CON_DSP_CMU_DSP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(D_TZPC_DSP_QCH, QCH_CON_D_TZPC_DSP_QCH_ENABLE, QCH_CON_D_TZPC_DSP_QCH_CLOCK_REQ, QCH_CON_D_TZPC_DSP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(IP_DSP_QCH, QCH_CON_IP_DSP_QCH_ENABLE, QCH_CON_IP_DSP_QCH_CLOCK_REQ, QCH_CON_IP_DSP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_MI_LD_STRM_SDMADSP_QCH, QCH_CON_LH_AST_MI_LD_STRM_SDMADSP_QCH_ENABLE, QCH_CON_LH_AST_MI_LD_STRM_SDMADSP_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_LD_STRM_SDMADSP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_LD_DNCDSP_DMA_QCH, QCH_CON_LH_AXI_MI_LD_DNCDSP_DMA_QCH_ENABLE, QCH_CON_LH_AXI_MI_LD_DNCDSP_DMA_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LD_DNCDSP_DMA_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_LD_DNCDSP_SFR_QCH, QCH_CON_LH_AXI_MI_LD_DNCDSP_SFR_QCH_ENABLE, QCH_CON_LH_AXI_MI_LD_DNCDSP_SFR_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LD_DNCDSP_SFR_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_LD_DSPDNC_SFR_QCH, QCH_CON_LH_AXI_SI_LD_DSPDNC_SFR_QCH_ENABLE, QCH_CON_LH_AXI_SI_LD_DSPDNC_SFR_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LD_DSPDNC_SFR_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_LD_DSPDNC_SHMEM_QCH, QCH_CON_LH_AXI_SI_LD_DSPDNC_SHMEM_QCH_ENABLE, QCH_CON_LH_AXI_SI_LD_DSPDNC_SHMEM_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LD_DSPDNC_SHMEM_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_LP_DSP_QCH, QCH_CON_SLH_AXI_MI_LP_DSP_QCH_ENABLE, QCH_CON_SLH_AXI_MI_LP_DSP_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_LP_DSP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_LD_DSPDNC_CACHE_QCH, QCH_CON_SLH_AXI_SI_LD_DSPDNC_CACHE_QCH_ENABLE, QCH_CON_SLH_AXI_SI_LD_DSPDNC_CACHE_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_LD_DSPDNC_CACHE_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_DSP_QCH, QCH_CON_SYSREG_DSP_QCH_ENABLE, QCH_CON_SYSREG_DSP_QCH_CLOCK_REQ, QCH_CON_SYSREG_DSP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(BUSIF_STR_CPUCL0_3_QCH, QCH_CON_BUSIF_STR_CPUCL0_3_QCH_ENABLE, QCH_CON_BUSIF_STR_CPUCL0_3_QCH_CLOCK_REQ, QCH_CON_BUSIF_STR_CPUCL0_3_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(BUSIF_STR_CPUCL0_3_QCH_CORE, QCH_CON_BUSIF_STR_CPUCL0_3_QCH_CORE_ENABLE, QCH_CON_BUSIF_STR_CPUCL0_3_QCH_CORE_CLOCK_REQ, QCH_CON_BUSIF_STR_CPUCL0_3_QCH_CORE_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CLUSTER0_QCH_SCLK, QCH_CON_CLUSTER0_QCH_SCLK_ENABLE, QCH_CON_CLUSTER0_QCH_SCLK_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_SCLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CLUSTER0_QCH_ATCLK, QCH_CON_CLUSTER0_QCH_ATCLK_ENABLE, QCH_CON_CLUSTER0_QCH_ATCLK_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_ATCLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CLUSTER0_QCH_PDBGCLK, QCH_CON_CLUSTER0_QCH_PDBGCLK_ENABLE, QCH_CON_CLUSTER0_QCH_PDBGCLK_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_PDBGCLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CLUSTER0_QCH_PCLK, QCH_CON_CLUSTER0_QCH_PCLK_ENABLE, QCH_CON_CLUSTER0_QCH_PCLK_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_PCLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CLUSTER0_QCH_PERIPHCLK, QCH_CON_CLUSTER0_QCH_PERIPHCLK_ENABLE, QCH_CON_CLUSTER0_QCH_PERIPHCLK_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_PERIPHCLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CLUSTER0_QCH_PPUCLK, QCH_CON_CLUSTER0_QCH_PPUCLK_ENABLE, QCH_CON_CLUSTER0_QCH_PPUCLK_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_PPUCLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CLUSTER0_QCH_GIC, QCH_CON_CLUSTER0_QCH_GIC_ENABLE, QCH_CON_CLUSTER0_QCH_GIC_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_GIC_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CMU_DSU_CMUREF_QCH, DMYQCH_CON_CMU_DSU_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_DSU_CMUREF_QCH_CLOCK_REQ, DMYQCH_CON_CMU_DSU_CMUREF_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DSU_CMU_DSU_QCH, QCH_CON_DSU_CMU_DSU_QCH_ENABLE, QCH_CON_DSU_CMU_DSU_QCH_CLOCK_REQ, QCH_CON_DSU_CMU_DSU_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(HTU_DSU_QCH_PCLK, QCH_CON_HTU_DSU_QCH_PCLK_ENABLE, QCH_CON_HTU_DSU_QCH_PCLK_CLOCK_REQ, QCH_CON_HTU_DSU_QCH_PCLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(HTU_DSU_QCH_CLK, QCH_CON_HTU_DSU_QCH_CLK_ENABLE, QCH_CON_HTU_DSU_QCH_CLK_CLOCK_REQ, QCH_CON_HTU_DSU_QCH_CLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_ACEL_MI_D0_ACP_QCH, QCH_CON_LH_ACEL_MI_D0_ACP_QCH_ENABLE, QCH_CON_LH_ACEL_MI_D0_ACP_QCH_CLOCK_REQ, QCH_CON_LH_ACEL_MI_D0_ACP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_ACEL_MI_D1_ACP_QCH, QCH_CON_LH_ACEL_MI_D1_ACP_QCH_ENABLE, QCH_CON_LH_ACEL_MI_D1_ACP_QCH_CLOCK_REQ, QCH_CON_LH_ACEL_MI_D1_ACP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_MI_LD_IRI_GICCPU_CLUSTER0_QCH, QCH_CON_LH_AST_MI_LD_IRI_GICCPU_CLUSTER0_QCH_ENABLE, QCH_CON_LH_AST_MI_LD_IRI_GICCPU_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_LD_IRI_GICCPU_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_SI_LD_ICC_CPUGIC_CLUSTER0_QCH, QCH_CON_LH_AST_SI_LD_ICC_CPUGIC_CLUSTER0_QCH_ENABLE, QCH_CON_LH_AST_SI_LD_ICC_CPUGIC_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_LD_ICC_CPUGIC_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_ATB_SI_IT_CLUSTER0_QCH, QCH_CON_LH_ATB_SI_IT_CLUSTER0_QCH_ENABLE, QCH_CON_LH_ATB_SI_IT_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LH_ATB_SI_IT_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_ATB_SI_IT_DDCDSU_QCH, QCH_CON_LH_ATB_SI_IT_DDCDSU_QCH_ENABLE, QCH_CON_LH_ATB_SI_IT_DDCDSU_QCH_CLOCK_REQ, QCH_CON_LH_ATB_SI_IT_DDCDSU_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_CHI_SI_D0_CLUSTER0_QCH, QCH_CON_LH_CHI_SI_D0_CLUSTER0_QCH_ENABLE, QCH_CON_LH_CHI_SI_D0_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LH_CHI_SI_D0_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_CHI_SI_D1_CLUSTER0_QCH, QCH_CON_LH_CHI_SI_D1_CLUSTER0_QCH_ENABLE, QCH_CON_LH_CHI_SI_D1_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LH_CHI_SI_D1_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPC_INSTRRET_CLUSTER0_0_QCH, QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH_ENABLE, QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH_CLOCK_REQ, QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPC_INSTRRET_CLUSTER0_1_QCH, QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH_ENABLE, QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH_CLOCK_REQ, QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPC_INSTRRUN_CLUSTER0_0_QCH, QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH_ENABLE, QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH_CLOCK_REQ, QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPC_INSTRRUN_CLUSTER0_1_QCH, QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH_ENABLE, QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH_CLOCK_REQ, QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_CLK_CLUSTER_ACLK_QCH, QCH_CON_RSTNSYNC_CLK_CLUSTER_ACLK_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_CLUSTER_ACLK_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_CLUSTER_ACLK_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_CLK_CLUSTER_ATCLK_QCH, QCH_CON_RSTNSYNC_CLK_CLUSTER_ATCLK_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_CLUSTER_ATCLK_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_CLUSTER_ATCLK_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_CLK_CLUSTER_GICCLK_QCH, QCH_CON_RSTNSYNC_CLK_CLUSTER_GICCLK_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_CLUSTER_GICCLK_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_CLUSTER_GICCLK_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_CLK_CLUSTER_MPACTCLK_QCH, QCH_CON_RSTNSYNC_CLK_CLUSTER_MPACTCLK_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_CLUSTER_MPACTCLK_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_CLUSTER_MPACTCLK_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_CLK_CLUSTER_PCLK_QCH, QCH_CON_RSTNSYNC_CLK_CLUSTER_PCLK_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_CLUSTER_PCLK_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_CLUSTER_PCLK_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_CLK_CLUSTER_PERIPHCLK_QCH, QCH_CON_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_CLK_CLUSTER_PPUCLK_QCH, QCH_CON_RSTNSYNC_CLK_CLUSTER_PPUCLK_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_CLUSTER_PPUCLK_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_CLUSTER_PPUCLK_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_CLK_CLUSTER_SCLK_QCH, QCH_CON_RSTNSYNC_CLK_CLUSTER_SCLK_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_CLUSTER_SCLK_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_CLUSTER_SCLK_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_CLK_DSU_POWERIP_QCH, QCH_CON_RSTNSYNC_CLK_DSU_POWERIP_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_DSU_POWERIP_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_DSU_POWERIP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_SR_CLK_DSU_HTU_QCH, QCH_CON_RSTNSYNC_SR_CLK_DSU_HTU_QCH_ENABLE, QCH_CON_RSTNSYNC_SR_CLK_DSU_HTU_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_SR_CLK_DSU_HTU_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_SR_CLK_DSU_POWERIP_QCH, QCH_CON_RSTNSYNC_SR_CLK_DSU_POWERIP_QCH_ENABLE, QCH_CON_RSTNSYNC_SR_CLK_DSU_POWERIP_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_SR_CLK_DSU_POWERIP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_IP_UTILITY_QCH, QCH_CON_SLH_AXI_MI_IP_UTILITY_QCH_ENABLE, QCH_CON_SLH_AXI_MI_IP_UTILITY_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_IP_UTILITY_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_LP_PPU_QCH, QCH_CON_SLH_AXI_MI_LP_PPU_QCH_ENABLE, QCH_CON_SLH_AXI_MI_LP_PPU_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_LP_PPU_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_IP_UTILITY_QCH, QCH_CON_SLH_AXI_SI_IP_UTILITY_QCH_ENABLE, QCH_CON_SLH_AXI_SI_IP_UTILITY_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_IP_UTILITY_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_P_CLUSTER0_NOCL0_QCH, QCH_CON_SLH_AXI_SI_P_CLUSTER0_NOCL0_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_CLUSTER0_NOCL0_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_CLUSTER0_NOCL0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(STR_CPUCL0_3_QCH, DMYQCH_CON_STR_CPUCL0_3_QCH_ENABLE, DMYQCH_CON_STR_CPUCL0_3_QCH_CLOCK_REQ, DMYQCH_CON_STR_CPUCL0_3_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(U_DDD_CTRL_CORE__DSU_QCH, QCH_CON_U_DDD_CTRL_CORE__DSU_QCH_ENABLE, QCH_CON_U_DDD_CTRL_CORE__DSU_QCH_CLOCK_REQ, QCH_CON_U_DDD_CTRL_CORE__DSU_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(BG3D_PWRCTL_QCH, DMYQCH_CON_BG3D_PWRCTL_QCH_ENABLE, DMYQCH_CON_BG3D_PWRCTL_QCH_CLOCK_REQ, DMYQCH_CON_BG3D_PWRCTL_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CFM_G3D_QCH, QCH_CON_CFM_G3D_QCH_ENABLE, QCH_CON_CFM_G3D_QCH_CLOCK_REQ, QCH_CON_CFM_G3D_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(D_TZPC_G3D_QCH, QCH_CON_D_TZPC_G3D_QCH_ENABLE, QCH_CON_D_TZPC_G3D_QCH_CLOCK_REQ, QCH_CON_D_TZPC_G3D_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(G3D_CMU_G3D_QCH, QCH_CON_G3D_CMU_G3D_QCH_ENABLE, QCH_CON_G3D_CMU_G3D_QCH_CLOCK_REQ, QCH_CON_G3D_CMU_G3D_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_P_G3D_QCH, QCH_CON_SLH_AXI_MI_P_G3D_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_G3D_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_G3D_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_P_INT_G3D_QCH, QCH_CON_SLH_AXI_SI_P_INT_G3D_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_INT_G3D_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_INT_G3D_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_G3D_QCH, QCH_CON_SYSREG_G3D_QCH_ENABLE, QCH_CON_SYSREG_G3D_QCH_CLOCK_REQ, QCH_CON_SYSREG_G3D_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ADD_APBIF_G3D_QCH, QCH_CON_ADD_APBIF_G3D_QCH_ENABLE, QCH_CON_ADD_APBIF_G3D_QCH_CLOCK_REQ, QCH_CON_ADD_APBIF_G3D_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ADD_G3D_QCH, DMYQCH_CON_ADD_G3D_QCH_ENABLE, DMYQCH_CON_ADD_G3D_QCH_CLOCK_REQ, DMYQCH_CON_ADD_G3D_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ADM_DAP_G_G3D_QCH, DMYQCH_CON_ADM_DAP_G_G3D_QCH_ENABLE, DMYQCH_CON_ADM_DAP_G_G3D_QCH_CLOCK_REQ, DMYQCH_CON_ADM_DAP_G_G3D_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ASB_G3D_QCH_LH_D0_G3D, QCH_CON_ASB_G3D_QCH_LH_D0_G3D_ENABLE, QCH_CON_ASB_G3D_QCH_LH_D0_G3D_CLOCK_REQ, QCH_CON_ASB_G3D_QCH_LH_D0_G3D_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ASB_G3D_QCH_LH_D1_G3D, QCH_CON_ASB_G3D_QCH_LH_D1_G3D_ENABLE, QCH_CON_ASB_G3D_QCH_LH_D1_G3D_CLOCK_REQ, QCH_CON_ASB_G3D_QCH_LH_D1_G3D_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ASB_G3D_QCH_LH_D2_G3D, QCH_CON_ASB_G3D_QCH_LH_D2_G3D_ENABLE, QCH_CON_ASB_G3D_QCH_LH_D2_G3D_CLOCK_REQ, QCH_CON_ASB_G3D_QCH_LH_D2_G3D_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ASB_G3D_QCH_LH_D3_G3D, QCH_CON_ASB_G3D_QCH_LH_D3_G3D_ENABLE, QCH_CON_ASB_G3D_QCH_LH_D3_G3D_CLOCK_REQ, QCH_CON_ASB_G3D_QCH_LH_D3_G3D_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ASB_G3D_QCH_S_LH_P_G3D, QCH_CON_ASB_G3D_QCH_S_LH_P_G3D_ENABLE, QCH_CON_ASB_G3D_QCH_S_LH_P_G3D_CLOCK_REQ, QCH_CON_ASB_G3D_QCH_S_LH_P_G3D_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(BUSIF_DDC_G3D_QCH, QCH_CON_BUSIF_DDC_G3D_QCH_ENABLE, QCH_CON_BUSIF_DDC_G3D_QCH_CLOCK_REQ, QCH_CON_BUSIF_DDC_G3D_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(G3DCORE_CMU_G3DCORE_QCH, QCH_CON_G3DCORE_CMU_G3DCORE_QCH_ENABLE, QCH_CON_G3DCORE_CMU_G3DCORE_QCH_CLOCK_REQ, QCH_CON_G3DCORE_CMU_G3DCORE_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(GPU_QCH_CLK, DMYQCH_CON_GPU_QCH_CLK_ENABLE, DMYQCH_CON_GPU_QCH_CLK_CLOCK_REQ, DMYQCH_CON_GPU_QCH_CLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(GPU_QCH_PCLK, DMYQCH_CON_GPU_QCH_PCLK_ENABLE, DMYQCH_CON_GPU_QCH_PCLK_CLOCK_REQ, DMYQCH_CON_GPU_QCH_PCLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(HTU_G3D_QCH_PCLK, QCH_CON_HTU_G3D_QCH_PCLK_ENABLE, QCH_CON_HTU_G3D_QCH_PCLK_CLOCK_REQ, QCH_CON_HTU_G3D_QCH_PCLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(HTU_G3D_QCH_CLK, QCH_CON_HTU_G3D_QCH_CLK_ENABLE, QCH_CON_HTU_G3D_QCH_CLK_CLOCK_REQ, QCH_CON_HTU_G3D_QCH_CLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_ATB_SI_T_DDCG3D_QCH, QCH_CON_LH_ATB_SI_T_DDCG3D_QCH_ENABLE, QCH_CON_LH_ATB_SI_T_DDCG3D_QCH_CLOCK_REQ, QCH_CON_LH_ATB_SI_T_DDCG3D_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_CLK_G3DCORE_FREE_OSCCLK_QCH, QCH_CON_RSTNSYNC_CLK_G3DCORE_FREE_OSCCLK_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_G3DCORE_FREE_OSCCLK_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_G3DCORE_FREE_OSCCLK_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_CLK_G3DCORE_NOCP_QCH, QCH_CON_RSTNSYNC_CLK_G3DCORE_NOCP_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_G3DCORE_NOCP_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_G3DCORE_NOCP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_CLK_G3D_POWERIP_QCH, QCH_CON_RSTNSYNC_CLK_G3D_POWERIP_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_G3D_POWERIP_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_G3D_POWERIP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_SR_CLK_G3DCORE_FREE_OSCCLK_QCH, QCH_CON_RSTNSYNC_SR_CLK_G3DCORE_FREE_OSCCLK_QCH_ENABLE, QCH_CON_RSTNSYNC_SR_CLK_G3DCORE_FREE_OSCCLK_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_SR_CLK_G3DCORE_FREE_OSCCLK_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_SR_CLK_G3DCORE_NOCP_QCH, QCH_CON_RSTNSYNC_SR_CLK_G3DCORE_NOCP_QCH_ENABLE, QCH_CON_RSTNSYNC_SR_CLK_G3DCORE_NOCP_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_SR_CLK_G3DCORE_NOCP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_SR_CLK_G3D_POWERIP_QCH, QCH_CON_RSTNSYNC_SR_CLK_G3D_POWERIP_QCH_ENABLE, QCH_CON_RSTNSYNC_SR_CLK_G3D_POWERIP_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_SR_CLK_G3D_POWERIP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(STR_MUX_G3D_QCH_PCLK, QCH_CON_STR_MUX_G3D_QCH_PCLK_ENABLE, QCH_CON_STR_MUX_G3D_QCH_PCLK_CLOCK_REQ, QCH_CON_STR_MUX_G3D_QCH_PCLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(STR_MUX_G3D_QCH_CORE, QCH_CON_STR_MUX_G3D_QCH_CORE_ENABLE, QCH_CON_STR_MUX_G3D_QCH_CORE_CLOCK_REQ, QCH_CON_STR_MUX_G3D_QCH_CORE_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(U_DDD_CTRL_CORE__G3D_QCH, QCH_CON_U_DDD_CTRL_CORE__G3D_QCH_ENABLE, QCH_CON_U_DDD_CTRL_CORE__G3D_QCH_CLOCK_REQ, QCH_CON_U_DDD_CTRL_CORE__G3D_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(D_TZPC_GNPU_QCH, QCH_CON_D_TZPC_GNPU_QCH_ENABLE, QCH_CON_D_TZPC_GNPU_QCH_CLOCK_REQ, QCH_CON_D_TZPC_GNPU_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(GNPU_CMU_GNPU_QCH, QCH_CON_GNPU_CMU_GNPU_QCH_ENABLE, QCH_CON_GNPU_CMU_GNPU_QCH_CLOCK_REQ, QCH_CON_GNPU_CMU_GNPU_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(IP_NPUCORE_QCH_CORE, QCH_CON_IP_NPUCORE_QCH_CORE_ENABLE, QCH_CON_IP_NPUCORE_QCH_CORE_CLOCK_REQ, QCH_CON_IP_NPUCORE_QCH_CORE_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(IP_NPUCORE_QCH_SRAM, QCH_CON_IP_NPUCORE_QCH_SRAM_ENABLE, QCH_CON_IP_NPUCORE_QCH_SRAM_CLOCK_REQ, QCH_CON_IP_NPUCORE_QCH_SRAM_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_LD0_GNPU_QCH, QCH_CON_LH_AXI_MI_LD0_GNPU_QCH_ENABLE, QCH_CON_LH_AXI_MI_LD0_GNPU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LD0_GNPU_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_LD1_GNPU_QCH, QCH_CON_LH_AXI_MI_LD1_GNPU_QCH_ENABLE, QCH_CON_LH_AXI_MI_LD1_GNPU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LD1_GNPU_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_LD_CTRL_GNPU_QCH, QCH_CON_LH_AXI_MI_LD_CTRL_GNPU_QCH_ENABLE, QCH_CON_LH_AXI_MI_LD_CTRL_GNPU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LD_CTRL_GNPU_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_LD_GNPUDNC_SHMEM_QCH, QCH_CON_LH_AXI_SI_LD_GNPUDNC_SHMEM_QCH_ENABLE, QCH_CON_LH_AXI_SI_LD_GNPUDNC_SHMEM_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LD_GNPUDNC_SHMEM_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_LD_RQ_GNPU_QCH, QCH_CON_LH_AXI_SI_LD_RQ_GNPU_QCH_ENABLE, QCH_CON_LH_AXI_SI_LD_RQ_GNPU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LD_RQ_GNPU_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_LP_GNPU_QCH, QCH_CON_SLH_AXI_MI_LP_GNPU_QCH_ENABLE, QCH_CON_SLH_AXI_MI_LP_GNPU_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_LP_GNPU_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_LD_CMDQ_GNPU_QCH, QCH_CON_SLH_AXI_SI_LD_CMDQ_GNPU_QCH_ENABLE, QCH_CON_SLH_AXI_SI_LD_CMDQ_GNPU_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_LD_CMDQ_GNPU_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_GNPU_QCH, QCH_CON_SYSREG_GNPU_QCH_ENABLE, QCH_CON_SYSREG_GNPU_QCH_CLOCK_REQ, QCH_CON_SYSREG_GNPU_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(GNSS_CMU_GNSS_QCH, QCH_CON_GNSS_CMU_GNSS_QCH_ENABLE, QCH_CON_GNSS_CMU_GNSS_QCH_CLOCK_REQ, QCH_CON_GNSS_CMU_GNSS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DP_LINK_QCH_OSC_CLK, QCH_CON_DP_LINK_QCH_OSC_CLK_ENABLE, QCH_CON_DP_LINK_QCH_OSC_CLK_CLOCK_REQ, QCH_CON_DP_LINK_QCH_OSC_CLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DP_LINK_QCH_PCLK, QCH_CON_DP_LINK_QCH_PCLK_ENABLE, QCH_CON_DP_LINK_QCH_PCLK_CLOCK_REQ, QCH_CON_DP_LINK_QCH_PCLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DP_LINK_QCH_GTC_CLK, QCH_CON_DP_LINK_QCH_GTC_CLK_ENABLE, QCH_CON_DP_LINK_QCH_GTC_CLK_CLOCK_REQ, QCH_CON_DP_LINK_QCH_GTC_CLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(D_TZPC_HSI0_QCH, QCH_CON_D_TZPC_HSI0_QCH_ENABLE, QCH_CON_D_TZPC_HSI0_QCH_CLOCK_REQ, QCH_CON_D_TZPC_HSI0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(HSI0_CMU_HSI0_QCH, QCH_CON_HSI0_CMU_HSI0_QCH_ENABLE, QCH_CON_HSI0_CMU_HSI0_QCH_CLOCK_REQ, QCH_CON_HSI0_CMU_HSI0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_HSI0_BUS1_QCH, QCH_CON_PPMU_HSI0_BUS1_QCH_ENABLE, QCH_CON_PPMU_HSI0_BUS1_QCH_CLOCK_REQ, QCH_CON_PPMU_HSI0_BUS1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_ACEL_SI_D_HSI0_QCH, QCH_CON_SLH_ACEL_SI_D_HSI0_QCH_ENABLE, QCH_CON_SLH_ACEL_SI_D_HSI0_QCH_CLOCK_REQ, QCH_CON_SLH_ACEL_SI_D_HSI0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_SI_G_PPMU_HSI0_QCH, QCH_CON_SLH_AST_SI_G_PPMU_HSI0_QCH_ENABLE, QCH_CON_SLH_AST_SI_G_PPMU_HSI0_QCH_CLOCK_REQ, QCH_CON_SLH_AST_SI_G_PPMU_HSI0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_LD_AUDHSI0_QCH, QCH_CON_SLH_AXI_MI_LD_AUDHSI0_QCH_ENABLE, QCH_CON_SLH_AXI_MI_LD_AUDHSI0_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_LD_AUDHSI0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_P_HSI0_QCH, QCH_CON_SLH_AXI_MI_P_HSI0_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_HSI0_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_HSI0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_LD_HSI0AUD_QCH, QCH_CON_SLH_AXI_SI_LD_HSI0AUD_QCH_ENABLE, QCH_CON_SLH_AXI_SI_LD_HSI0AUD_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_LD_HSI0AUD_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SPC_HSI0_QCH, QCH_CON_SPC_HSI0_QCH_ENABLE, QCH_CON_SPC_HSI0_QCH_CLOCK_REQ, QCH_CON_SPC_HSI0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D_HSI0_QCH, QCH_CON_SYSMMU_D_HSI0_QCH_ENABLE, QCH_CON_SYSMMU_D_HSI0_QCH_CLOCK_REQ, QCH_CON_SYSMMU_D_HSI0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_HSI0_QCH, QCH_CON_SYSREG_HSI0_QCH_ENABLE, QCH_CON_SYSREG_HSI0_QCH_CLOCK_REQ, QCH_CON_SYSREG_HSI0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USB32DRD_QCH_S_SUBCTRL, QCH_CON_USB32DRD_QCH_S_SUBCTRL_ENABLE, QCH_CON_USB32DRD_QCH_S_SUBCTRL_CLOCK_REQ, QCH_CON_USB32DRD_QCH_S_SUBCTRL_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USB32DRD_QCH_S_LINK, QCH_CON_USB32DRD_QCH_S_LINK_ENABLE, QCH_CON_USB32DRD_QCH_S_LINK_CLOCK_REQ, QCH_CON_USB32DRD_QCH_S_LINK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USB32DRD_QCH_S_CTRL, QCH_CON_USB32DRD_QCH_S_CTRL_ENABLE, QCH_CON_USB32DRD_QCH_S_CTRL_CLOCK_REQ, QCH_CON_USB32DRD_QCH_S_CTRL_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USB32DRD_QCH_S_TCA, QCH_CON_USB32DRD_QCH_S_TCA_ENABLE, QCH_CON_USB32DRD_QCH_S_TCA_CLOCK_REQ, QCH_CON_USB32DRD_QCH_S_TCA_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USB32DRD_QCH_S_EUSBCTL, QCH_CON_USB32DRD_QCH_S_EUSBCTL_ENABLE, QCH_CON_USB32DRD_QCH_S_EUSBCTL_CLOCK_REQ, QCH_CON_USB32DRD_QCH_S_EUSBCTL_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USB32DRD_QCH_S_EUSBPHY, QCH_CON_USB32DRD_QCH_S_EUSBPHY_ENABLE, QCH_CON_USB32DRD_QCH_S_EUSBPHY_CLOCK_REQ, QCH_CON_USB32DRD_QCH_S_EUSBPHY_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(VGEN_LITE_HSI0_QCH, QCH_CON_VGEN_LITE_HSI0_QCH_ENABLE, QCH_CON_VGEN_LITE_HSI0_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_HSI0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(D_TZPC_HSI1_QCH, QCH_CON_D_TZPC_HSI1_QCH_ENABLE, QCH_CON_D_TZPC_HSI1_QCH_CLOCK_REQ, QCH_CON_D_TZPC_HSI1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(GPIO_HSI1_QCH, QCH_CON_GPIO_HSI1_QCH_ENABLE, QCH_CON_GPIO_HSI1_QCH_CLOCK_REQ, QCH_CON_GPIO_HSI1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(HSI1_CMU_HSI1_QCH, QCH_CON_HSI1_CMU_HSI1_QCH_ENABLE, QCH_CON_HSI1_CMU_HSI1_QCH_CLOCK_REQ, QCH_CON_HSI1_CMU_HSI1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_ACEL_SI_D_HSI1_QCH, QCH_CON_LH_ACEL_SI_D_HSI1_QCH_ENABLE, QCH_CON_LH_ACEL_SI_D_HSI1_QCH_CLOCK_REQ, QCH_CON_LH_ACEL_SI_D_HSI1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PCIE_GEN2_QCH_AXI, QCH_CON_PCIE_GEN2_QCH_AXI_ENABLE, QCH_CON_PCIE_GEN2_QCH_AXI_CLOCK_REQ, QCH_CON_PCIE_GEN2_QCH_AXI_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PCIE_GEN2_QCH_PCS_APB, QCH_CON_PCIE_GEN2_QCH_PCS_APB_ENABLE, QCH_CON_PCIE_GEN2_QCH_PCS_APB_CLOCK_REQ, QCH_CON_PCIE_GEN2_QCH_PCS_APB_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PCIE_GEN2_QCH_DBI, QCH_CON_PCIE_GEN2_QCH_DBI_ENABLE, QCH_CON_PCIE_GEN2_QCH_DBI_CLOCK_REQ, QCH_CON_PCIE_GEN2_QCH_DBI_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PCIE_GEN2_QCH_APB, QCH_CON_PCIE_GEN2_QCH_APB_ENABLE, QCH_CON_PCIE_GEN2_QCH_APB_CLOCK_REQ, QCH_CON_PCIE_GEN2_QCH_APB_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PCIE_GEN2_QCH_REF, DMYQCH_CON_PCIE_GEN2_QCH_REF_ENABLE, DMYQCH_CON_PCIE_GEN2_QCH_REF_CLOCK_REQ, DMYQCH_CON_PCIE_GEN2_QCH_REF_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PCIE_GEN2_QCH_PMA_APB, QCH_CON_PCIE_GEN2_QCH_PMA_APB_ENABLE, QCH_CON_PCIE_GEN2_QCH_PMA_APB_CLOCK_REQ, QCH_CON_PCIE_GEN2_QCH_PMA_APB_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PCIE_GEN2_QCH_UDBG_APB, QCH_CON_PCIE_GEN2_QCH_UDBG_APB_ENABLE, QCH_CON_PCIE_GEN2_QCH_UDBG_APB_CLOCK_REQ, QCH_CON_PCIE_GEN2_QCH_UDBG_APB_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PCIE_GEN3_QCH_APB, QCH_CON_PCIE_GEN3_QCH_APB_ENABLE, QCH_CON_PCIE_GEN3_QCH_APB_CLOCK_REQ, QCH_CON_PCIE_GEN3_QCH_APB_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PCIE_GEN3_QCH_DBI, QCH_CON_PCIE_GEN3_QCH_DBI_ENABLE, QCH_CON_PCIE_GEN3_QCH_DBI_CLOCK_REQ, QCH_CON_PCIE_GEN3_QCH_DBI_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PCIE_GEN3_QCH_AXI, QCH_CON_PCIE_GEN3_QCH_AXI_ENABLE, QCH_CON_PCIE_GEN3_QCH_AXI_CLOCK_REQ, QCH_CON_PCIE_GEN3_QCH_AXI_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PCIE_GEN3_QCH_PCS_APB, QCH_CON_PCIE_GEN3_QCH_PCS_APB_ENABLE, QCH_CON_PCIE_GEN3_QCH_PCS_APB_CLOCK_REQ, QCH_CON_PCIE_GEN3_QCH_PCS_APB_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PCIE_GEN3_QCH_REF, DMYQCH_CON_PCIE_GEN3_QCH_REF_ENABLE, DMYQCH_CON_PCIE_GEN3_QCH_REF_CLOCK_REQ, DMYQCH_CON_PCIE_GEN3_QCH_REF_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PCIE_GEN3_QCH_UDBG_APB, QCH_CON_PCIE_GEN3_QCH_UDBG_APB_ENABLE, QCH_CON_PCIE_GEN3_QCH_UDBG_APB_CLOCK_REQ, QCH_CON_PCIE_GEN3_QCH_UDBG_APB_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PCIE_GEN3_QCH_PMA_APB, QCH_CON_PCIE_GEN3_QCH_PMA_APB_ENABLE, QCH_CON_PCIE_GEN3_QCH_PMA_APB_CLOCK_REQ, QCH_CON_PCIE_GEN3_QCH_PMA_APB_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PCIE_IA_GEN2_QCH, QCH_CON_PCIE_IA_GEN2_QCH_ENABLE, QCH_CON_PCIE_IA_GEN2_QCH_CLOCK_REQ, QCH_CON_PCIE_IA_GEN2_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PCIE_IA_GEN3_QCH, QCH_CON_PCIE_IA_GEN3_QCH_ENABLE, QCH_CON_PCIE_IA_GEN3_QCH_CLOCK_REQ, QCH_CON_PCIE_IA_GEN3_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_HSI1_QCH, QCH_CON_PPMU_HSI1_QCH_ENABLE, QCH_CON_PPMU_HSI1_QCH_CLOCK_REQ, QCH_CON_PPMU_HSI1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_SI_G_PPMU_HSI1_QCH, QCH_CON_SLH_AST_SI_G_PPMU_HSI1_QCH_ENABLE, QCH_CON_SLH_AST_SI_G_PPMU_HSI1_QCH_CLOCK_REQ, QCH_CON_SLH_AST_SI_G_PPMU_HSI1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_P_HSI1_QCH, QCH_CON_SLH_AXI_MI_P_HSI1_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_HSI1_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_HSI1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_HSI1_QCH_S1, QCH_CON_SYSMMU_HSI1_QCH_S1_ENABLE, QCH_CON_SYSMMU_HSI1_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_HSI1_QCH_S1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_HSI1_QCH_S2, QCH_CON_SYSMMU_HSI1_QCH_S2_ENABLE, QCH_CON_SYSMMU_HSI1_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_HSI1_QCH_S2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_HSI1_QCH, QCH_CON_SYSREG_HSI1_QCH_ENABLE, QCH_CON_SYSREG_HSI1_QCH_CLOCK_REQ, QCH_CON_SYSREG_HSI1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(VGEN_LITE_HSI1_QCH, QCH_CON_VGEN_LITE_HSI1_QCH_ENABLE, QCH_CON_VGEN_LITE_HSI1_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_HSI1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(D_TZPC_LME_QCH, QCH_CON_D_TZPC_LME_QCH_ENABLE, QCH_CON_D_TZPC_LME_QCH_CLOCK_REQ, QCH_CON_D_TZPC_LME_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(GDC_QCH, QCH_CON_GDC_QCH_ENABLE, QCH_CON_GDC_QCH_CLOCK_REQ, QCH_CON_GDC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(GDC_QCH_C2_M, QCH_CON_GDC_QCH_C2_M_ENABLE, QCH_CON_GDC_QCH_C2_M_CLOCK_REQ, QCH_CON_GDC_QCH_C2_M_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(GDC_QCH_C2_S, QCH_CON_GDC_QCH_C2_S_ENABLE, QCH_CON_GDC_QCH_C2_S_CLOCK_REQ, QCH_CON_GDC_QCH_C2_S_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_ACEL_SI_D_LME_QCH, QCH_CON_LH_ACEL_SI_D_LME_QCH_ENABLE, QCH_CON_LH_ACEL_SI_D_LME_QCH_CLOCK_REQ, QCH_CON_LH_ACEL_SI_D_LME_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_ID_LME_QCH, QCH_CON_LH_AXI_MI_ID_LME_QCH_ENABLE, QCH_CON_LH_AXI_MI_ID_LME_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_ID_LME_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_ID_LME_QCH, QCH_CON_LH_AXI_SI_ID_LME_QCH_ENABLE, QCH_CON_LH_AXI_SI_ID_LME_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_ID_LME_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LME_QCH_0, QCH_CON_LME_QCH_0_ENABLE, QCH_CON_LME_QCH_0_CLOCK_REQ, QCH_CON_LME_QCH_0_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LME_CMU_LME_QCH, QCH_CON_LME_CMU_LME_QCH_ENABLE, QCH_CON_LME_CMU_LME_QCH_CLOCK_REQ, QCH_CON_LME_CMU_LME_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_D_LME_QCH, QCH_CON_PPMU_D_LME_QCH_ENABLE, QCH_CON_PPMU_D_LME_QCH_CLOCK_REQ, QCH_CON_PPMU_D_LME_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(QE_D1_LME_QCH, QCH_CON_QE_D1_LME_QCH_ENABLE, QCH_CON_QE_D1_LME_QCH_CLOCK_REQ, QCH_CON_QE_D1_LME_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_SI_G_PPMU_LME_QCH, QCH_CON_SLH_AST_SI_G_PPMU_LME_QCH_ENABLE, QCH_CON_SLH_AST_SI_G_PPMU_LME_QCH_CLOCK_REQ, QCH_CON_SLH_AST_SI_G_PPMU_LME_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_P_LME_QCH, QCH_CON_SLH_AXI_MI_P_LME_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_LME_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_LME_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D_LME_QCH_S1, QCH_CON_SYSMMU_D_LME_QCH_S1_ENABLE, QCH_CON_SYSMMU_D_LME_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D_LME_QCH_S1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D_LME_QCH_S2, QCH_CON_SYSMMU_D_LME_QCH_S2_ENABLE, QCH_CON_SYSMMU_D_LME_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D_LME_QCH_S2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_LME_QCH, QCH_CON_SYSREG_LME_QCH_ENABLE, QCH_CON_SYSREG_LME_QCH_CLOCK_REQ, QCH_CON_SYSREG_LME_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(VGEN_LITE_D_GDC_QCH, QCH_CON_VGEN_LITE_D_GDC_QCH_ENABLE, QCH_CON_VGEN_LITE_D_GDC_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_D_GDC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(VGEN_LITE_D_LME_QCH, QCH_CON_VGEN_LITE_D_LME_QCH_ENABLE, QCH_CON_VGEN_LITE_D_LME_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_D_LME_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(D_TZPC_M2M_QCH, QCH_CON_D_TZPC_M2M_QCH_ENABLE, QCH_CON_D_TZPC_M2M_QCH_CLOCK_REQ, QCH_CON_D_TZPC_M2M_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(FRC_MC_QCH, QCH_CON_FRC_MC_QCH_ENABLE, QCH_CON_FRC_MC_QCH_CLOCK_REQ, QCH_CON_FRC_MC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(JPEG0_QCH, QCH_CON_JPEG0_QCH_ENABLE, QCH_CON_JPEG0_QCH_CLOCK_REQ, QCH_CON_JPEG0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(JPEG1_QCH, QCH_CON_JPEG1_QCH_ENABLE, QCH_CON_JPEG1_QCH_CLOCK_REQ, QCH_CON_JPEG1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(JSQZ_QCH, QCH_CON_JSQZ_QCH_ENABLE, QCH_CON_JSQZ_QCH_CLOCK_REQ, QCH_CON_JSQZ_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_ACEL_SI_D_M2M_QCH, QCH_CON_LH_ACEL_SI_D_M2M_QCH_ENABLE, QCH_CON_LH_ACEL_SI_D_M2M_QCH_CLOCK_REQ, QCH_CON_LH_ACEL_SI_D_M2M_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_FRC_MC_QCH, QCH_CON_LH_AXI_MI_FRC_MC_QCH_ENABLE, QCH_CON_LH_AXI_MI_FRC_MC_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_FRC_MC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_FRC_MC_QCH, QCH_CON_LH_AXI_SI_FRC_MC_QCH_ENABLE, QCH_CON_LH_AXI_SI_FRC_MC_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_FRC_MC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(M2M_QCH, QCH_CON_M2M_QCH_ENABLE, QCH_CON_M2M_QCH_CLOCK_REQ, QCH_CON_M2M_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(M2M_QCH_VOTF, QCH_CON_M2M_QCH_VOTF_ENABLE, QCH_CON_M2M_QCH_VOTF_CLOCK_REQ, QCH_CON_M2M_QCH_VOTF_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(M2M_CMU_M2M_QCH, QCH_CON_M2M_CMU_M2M_QCH_ENABLE, QCH_CON_M2M_CMU_M2M_QCH_CLOCK_REQ, QCH_CON_M2M_CMU_M2M_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_D_M2M_QCH, QCH_CON_PPMU_D_M2M_QCH_ENABLE, QCH_CON_PPMU_D_M2M_QCH_CLOCK_REQ, QCH_CON_PPMU_D_M2M_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(QE_FRC_MC_QCH, QCH_CON_QE_FRC_MC_QCH_ENABLE, QCH_CON_QE_FRC_MC_QCH_CLOCK_REQ, QCH_CON_QE_FRC_MC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(QE_JPEG0_QCH, QCH_CON_QE_JPEG0_QCH_ENABLE, QCH_CON_QE_JPEG0_QCH_CLOCK_REQ, QCH_CON_QE_JPEG0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(QE_JPEG1_QCH, QCH_CON_QE_JPEG1_QCH_ENABLE, QCH_CON_QE_JPEG1_QCH_CLOCK_REQ, QCH_CON_QE_JPEG1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(QE_JSQZ_QCH, QCH_CON_QE_JSQZ_QCH_ENABLE, QCH_CON_QE_JSQZ_QCH_CLOCK_REQ, QCH_CON_QE_JSQZ_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(QE_M2M_QCH, QCH_CON_QE_M2M_QCH_ENABLE, QCH_CON_QE_M2M_QCH_CLOCK_REQ, QCH_CON_QE_M2M_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_SI_G_PPMU_M2M_QCH, QCH_CON_SLH_AST_SI_G_PPMU_M2M_QCH_ENABLE, QCH_CON_SLH_AST_SI_G_PPMU_M2M_QCH_CLOCK_REQ, QCH_CON_SLH_AST_SI_G_PPMU_M2M_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_P_M2M_QCH, QCH_CON_SLH_AXI_MI_P_M2M_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_M2M_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_M2M_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D_M2M_PM_QCH_S2, QCH_CON_SYSMMU_D_M2M_PM_QCH_S2_ENABLE, QCH_CON_SYSMMU_D_M2M_PM_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D_M2M_PM_QCH_S2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D_M2M_PM_QCH_S1, QCH_CON_SYSMMU_D_M2M_PM_QCH_S1_ENABLE, QCH_CON_SYSMMU_D_M2M_PM_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D_M2M_PM_QCH_S1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_M2M_QCH, QCH_CON_SYSREG_M2M_QCH_ENABLE, QCH_CON_SYSREG_M2M_QCH_CLOCK_REQ, QCH_CON_SYSREG_M2M_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(VGEN_LITE_M2M_QCH, QCH_CON_VGEN_LITE_M2M_QCH_ENABLE, QCH_CON_VGEN_LITE_M2M_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_M2M_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(D_TZPC_MCSC_QCH, QCH_CON_D_TZPC_MCSC_QCH_ENABLE, QCH_CON_D_TZPC_MCSC_QCH_CLOCK_REQ, QCH_CON_D_TZPC_MCSC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_MI_OTF0_YUVPMCSC_QCH, QCH_CON_LH_AST_MI_OTF0_YUVPMCSC_QCH_ENABLE, QCH_CON_LH_AST_MI_OTF0_YUVPMCSC_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_OTF0_YUVPMCSC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_MI_OTF1_YUVPMCSC_QCH, QCH_CON_LH_AST_MI_OTF1_YUVPMCSC_QCH_ENABLE, QCH_CON_LH_AST_MI_OTF1_YUVPMCSC_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_OTF1_YUVPMCSC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_MI_OTF_BRPMCSC_QCH, QCH_CON_LH_AST_MI_OTF_BRPMCSC_QCH_ENABLE, QCH_CON_LH_AST_MI_OTF_BRPMCSC_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_OTF_BRPMCSC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_SI_OTF_MCSCYUVP_QCH, QCH_CON_LH_AST_SI_OTF_MCSCYUVP_QCH_ENABLE, QCH_CON_LH_AST_SI_OTF_MCSCYUVP_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_OTF_MCSCYUVP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_ID_MCSC0_QCH, QCH_CON_LH_AXI_MI_ID_MCSC0_QCH_ENABLE, QCH_CON_LH_AXI_MI_ID_MCSC0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_ID_MCSC0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_ID_MCSC1_QCH, QCH_CON_LH_AXI_MI_ID_MCSC1_QCH_ENABLE, QCH_CON_LH_AXI_MI_ID_MCSC1_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_ID_MCSC1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_ID_MCSC2_QCH, QCH_CON_LH_AXI_MI_ID_MCSC2_QCH_ENABLE, QCH_CON_LH_AXI_MI_ID_MCSC2_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_ID_MCSC2_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_ID_MCSC3_QCH, QCH_CON_LH_AXI_MI_ID_MCSC3_QCH_ENABLE, QCH_CON_LH_AXI_MI_ID_MCSC3_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_ID_MCSC3_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_ID_MCSC4_QCH, QCH_CON_LH_AXI_MI_ID_MCSC4_QCH_ENABLE, QCH_CON_LH_AXI_MI_ID_MCSC4_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_ID_MCSC4_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_ID_MCSC5_QCH, QCH_CON_LH_AXI_MI_ID_MCSC5_QCH_ENABLE, QCH_CON_LH_AXI_MI_ID_MCSC5_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_ID_MCSC5_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_ID_MCSC6_QCH, QCH_CON_LH_AXI_MI_ID_MCSC6_QCH_ENABLE, QCH_CON_LH_AXI_MI_ID_MCSC6_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_ID_MCSC6_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_D1_MCSC_QCH, QCH_CON_LH_AXI_SI_D1_MCSC_QCH_ENABLE, QCH_CON_LH_AXI_SI_D1_MCSC_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D1_MCSC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_D2_MCSC_QCH, QCH_CON_LH_AXI_SI_D2_MCSC_QCH_ENABLE, QCH_CON_LH_AXI_SI_D2_MCSC_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D2_MCSC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_D3_MCSC_QCH, QCH_CON_LH_AXI_SI_D3_MCSC_QCH_ENABLE, QCH_CON_LH_AXI_SI_D3_MCSC_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D3_MCSC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_D4_MCSC_QCH, QCH_CON_LH_AXI_SI_D4_MCSC_QCH_ENABLE, QCH_CON_LH_AXI_SI_D4_MCSC_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D4_MCSC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_ID_MCSC0_QCH, QCH_CON_LH_AXI_SI_ID_MCSC0_QCH_ENABLE, QCH_CON_LH_AXI_SI_ID_MCSC0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_ID_MCSC0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_ID_MCSC1_QCH, QCH_CON_LH_AXI_SI_ID_MCSC1_QCH_ENABLE, QCH_CON_LH_AXI_SI_ID_MCSC1_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_ID_MCSC1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_ID_MCSC2_QCH, QCH_CON_LH_AXI_SI_ID_MCSC2_QCH_ENABLE, QCH_CON_LH_AXI_SI_ID_MCSC2_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_ID_MCSC2_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_ID_MCSC3_QCH, QCH_CON_LH_AXI_SI_ID_MCSC3_QCH_ENABLE, QCH_CON_LH_AXI_SI_ID_MCSC3_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_ID_MCSC3_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_ID_MCSC4_QCH, QCH_CON_LH_AXI_SI_ID_MCSC4_QCH_ENABLE, QCH_CON_LH_AXI_SI_ID_MCSC4_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_ID_MCSC4_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_ID_MCSC5_QCH, QCH_CON_LH_AXI_SI_ID_MCSC5_QCH_ENABLE, QCH_CON_LH_AXI_SI_ID_MCSC5_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_ID_MCSC5_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_ID_MCSC6_QCH, QCH_CON_LH_AXI_SI_ID_MCSC6_QCH_ENABLE, QCH_CON_LH_AXI_SI_ID_MCSC6_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_ID_MCSC6_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(MCFP_QCH, QCH_CON_MCFP_QCH_ENABLE, QCH_CON_MCFP_QCH_CLOCK_REQ, QCH_CON_MCFP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(MCSC_QCH, QCH_CON_MCSC_QCH_ENABLE, QCH_CON_MCSC_QCH_CLOCK_REQ, QCH_CON_MCSC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(MCSC_QCH_C2R, QCH_CON_MCSC_QCH_C2R_ENABLE, QCH_CON_MCSC_QCH_C2R_CLOCK_REQ, QCH_CON_MCSC_QCH_C2R_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(MCSC_QCH_C2W, QCH_CON_MCSC_QCH_C2W_ENABLE, QCH_CON_MCSC_QCH_C2W_CLOCK_REQ, QCH_CON_MCSC_QCH_C2W_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(MCSC_CMU_MCSC_QCH, QCH_CON_MCSC_CMU_MCSC_QCH_ENABLE, QCH_CON_MCSC_CMU_MCSC_QCH_CLOCK_REQ, QCH_CON_MCSC_CMU_MCSC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_D0_MCSC_QCH, QCH_CON_PPMU_D0_MCSC_QCH_ENABLE, QCH_CON_PPMU_D0_MCSC_QCH_CLOCK_REQ, QCH_CON_PPMU_D0_MCSC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_D1_MCSC_QCH, QCH_CON_PPMU_D1_MCSC_QCH_ENABLE, QCH_CON_PPMU_D1_MCSC_QCH_CLOCK_REQ, QCH_CON_PPMU_D1_MCSC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_D2_MCSC_QCH, QCH_CON_PPMU_D2_MCSC_QCH_ENABLE, QCH_CON_PPMU_D2_MCSC_QCH_CLOCK_REQ, QCH_CON_PPMU_D2_MCSC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_D3_MCSC_QCH, QCH_CON_PPMU_D3_MCSC_QCH_ENABLE, QCH_CON_PPMU_D3_MCSC_QCH_CLOCK_REQ, QCH_CON_PPMU_D3_MCSC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_D4_MCSC_QCH, QCH_CON_PPMU_D4_MCSC_QCH_ENABLE, QCH_CON_PPMU_D4_MCSC_QCH_CLOCK_REQ, QCH_CON_PPMU_D4_MCSC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SIU_G_PPMU_MCSC_QCH, QCH_CON_SIU_G_PPMU_MCSC_QCH_ENABLE, QCH_CON_SIU_G_PPMU_MCSC_QCH_CLOCK_REQ, QCH_CON_SIU_G_PPMU_MCSC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_SI_G_PPMU_MCSC_QCH, QCH_CON_SLH_AST_SI_G_PPMU_MCSC_QCH_ENABLE, QCH_CON_SLH_AST_SI_G_PPMU_MCSC_QCH_CLOCK_REQ, QCH_CON_SLH_AST_SI_G_PPMU_MCSC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_P_MCSC_QCH, QCH_CON_SLH_AXI_MI_P_MCSC_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_MCSC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_MCSC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_D0_MCSC_QCH, QCH_CON_SLH_AXI_SI_D0_MCSC_QCH_ENABLE, QCH_CON_SLH_AXI_SI_D0_MCSC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_D0_MCSC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D0_MCSC_QCH_S1, QCH_CON_SYSMMU_D0_MCSC_QCH_S1_ENABLE, QCH_CON_SYSMMU_D0_MCSC_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D0_MCSC_QCH_S1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D0_MCSC_QCH_S2, QCH_CON_SYSMMU_D0_MCSC_QCH_S2_ENABLE, QCH_CON_SYSMMU_D0_MCSC_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D0_MCSC_QCH_S2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D1_MCSC_QCH_S1, QCH_CON_SYSMMU_D1_MCSC_QCH_S1_ENABLE, QCH_CON_SYSMMU_D1_MCSC_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D1_MCSC_QCH_S1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D1_MCSC_QCH_S2, QCH_CON_SYSMMU_D1_MCSC_QCH_S2_ENABLE, QCH_CON_SYSMMU_D1_MCSC_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D1_MCSC_QCH_S2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D2_MCSC_QCH_S1, QCH_CON_SYSMMU_D2_MCSC_QCH_S1_ENABLE, QCH_CON_SYSMMU_D2_MCSC_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D2_MCSC_QCH_S1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D2_MCSC_QCH_S2, QCH_CON_SYSMMU_D2_MCSC_QCH_S2_ENABLE, QCH_CON_SYSMMU_D2_MCSC_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D2_MCSC_QCH_S2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D3_MCSC_QCH_S1, QCH_CON_SYSMMU_D3_MCSC_QCH_S1_ENABLE, QCH_CON_SYSMMU_D3_MCSC_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D3_MCSC_QCH_S1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D3_MCSC_QCH_S2, QCH_CON_SYSMMU_D3_MCSC_QCH_S2_ENABLE, QCH_CON_SYSMMU_D3_MCSC_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D3_MCSC_QCH_S2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D4_MCSC_QCH_S1, QCH_CON_SYSMMU_D4_MCSC_QCH_S1_ENABLE, QCH_CON_SYSMMU_D4_MCSC_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D4_MCSC_QCH_S1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D4_MCSC_QCH_S2, QCH_CON_SYSMMU_D4_MCSC_QCH_S2_ENABLE, QCH_CON_SYSMMU_D4_MCSC_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D4_MCSC_QCH_S2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_MCSC_QCH, QCH_CON_SYSREG_MCSC_QCH_ENABLE, QCH_CON_SYSREG_MCSC_QCH_CLOCK_REQ, QCH_CON_SYSREG_MCSC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(VGEN_LITE_D0_MCSC_QCH, QCH_CON_VGEN_LITE_D0_MCSC_QCH_ENABLE, QCH_CON_VGEN_LITE_D0_MCSC_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_D0_MCSC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(VGEN_LITE_D1_MCSC_QCH, QCH_CON_VGEN_LITE_D1_MCSC_QCH_ENABLE, QCH_CON_VGEN_LITE_D1_MCSC_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_D1_MCSC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(VGEN_LITE_D2_MCSC_QCH, QCH_CON_VGEN_LITE_D2_MCSC_QCH_ENABLE, QCH_CON_VGEN_LITE_D2_MCSC_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_D2_MCSC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(D_TZPC_MFC0_QCH, QCH_CON_D_TZPC_MFC0_QCH_ENABLE, QCH_CON_D_TZPC_MFC0_QCH_CLOCK_REQ, QCH_CON_D_TZPC_MFC0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_MI_OTF0_MFC1MFC0_QCH, QCH_CON_LH_AST_MI_OTF0_MFC1MFC0_QCH_ENABLE, QCH_CON_LH_AST_MI_OTF0_MFC1MFC0_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_OTF0_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_MI_OTF1_MFC1MFC0_QCH, QCH_CON_LH_AST_MI_OTF1_MFC1MFC0_QCH_ENABLE, QCH_CON_LH_AST_MI_OTF1_MFC1MFC0_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_OTF1_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_MI_OTF2_MFC1MFC0_QCH, QCH_CON_LH_AST_MI_OTF2_MFC1MFC0_QCH_ENABLE, QCH_CON_LH_AST_MI_OTF2_MFC1MFC0_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_OTF2_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_MI_OTF3_MFC1MFC0_QCH, QCH_CON_LH_AST_MI_OTF3_MFC1MFC0_QCH_ENABLE, QCH_CON_LH_AST_MI_OTF3_MFC1MFC0_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_OTF3_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_SI_OTF0_MFC0MFC1_QCH, QCH_CON_LH_AST_SI_OTF0_MFC0MFC1_QCH_ENABLE, QCH_CON_LH_AST_SI_OTF0_MFC0MFC1_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_OTF0_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_SI_OTF1_MFC0MFC1_QCH, QCH_CON_LH_AST_SI_OTF1_MFC0MFC1_QCH_ENABLE, QCH_CON_LH_AST_SI_OTF1_MFC0MFC1_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_OTF1_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_SI_OTF2_MFC0MFC1_QCH, QCH_CON_LH_AST_SI_OTF2_MFC0MFC1_QCH_ENABLE, QCH_CON_LH_AST_SI_OTF2_MFC0MFC1_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_OTF2_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_SI_OTF3_MFC0MFC1_QCH, QCH_CON_LH_AST_SI_OTF3_MFC0MFC1_QCH_ENABLE, QCH_CON_LH_AST_SI_OTF3_MFC0MFC1_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_OTF3_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_ATB_MFC0_QCH_MI, QCH_CON_LH_ATB_MFC0_QCH_MI_ENABLE, QCH_CON_LH_ATB_MFC0_QCH_MI_CLOCK_REQ, QCH_CON_LH_ATB_MFC0_QCH_MI_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_ATB_MFC0_QCH_SI, QCH_CON_LH_ATB_MFC0_QCH_SI_ENABLE, QCH_CON_LH_ATB_MFC0_QCH_SI_CLOCK_REQ, QCH_CON_LH_ATB_MFC0_QCH_SI_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_ID_MFC0_QCH, QCH_CON_LH_AXI_MI_ID_MFC0_QCH_ENABLE, QCH_CON_LH_AXI_MI_ID_MFC0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_ID_MFC0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_D0_MFC0_QCH, QCH_CON_LH_AXI_SI_D0_MFC0_QCH_ENABLE, QCH_CON_LH_AXI_SI_D0_MFC0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D0_MFC0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_D1_MFC0_QCH, QCH_CON_LH_AXI_SI_D1_MFC0_QCH_ENABLE, QCH_CON_LH_AXI_SI_D1_MFC0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D1_MFC0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_ID_MFC0_QCH, QCH_CON_LH_AXI_SI_ID_MFC0_QCH_ENABLE, QCH_CON_LH_AXI_SI_ID_MFC0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_ID_MFC0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(MFC0_QCH, QCH_CON_MFC0_QCH_ENABLE, QCH_CON_MFC0_QCH_CLOCK_REQ, QCH_CON_MFC0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(MFC0_QCH_VOTF, QCH_CON_MFC0_QCH_VOTF_ENABLE, QCH_CON_MFC0_QCH_VOTF_CLOCK_REQ, QCH_CON_MFC0_QCH_VOTF_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(MFC0_CMU_MFC0_QCH, QCH_CON_MFC0_CMU_MFC0_QCH_ENABLE, QCH_CON_MFC0_CMU_MFC0_QCH_CLOCK_REQ, QCH_CON_MFC0_CMU_MFC0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_MFC0D0_QCH, QCH_CON_PPMU_MFC0D0_QCH_ENABLE, QCH_CON_PPMU_MFC0D0_QCH_CLOCK_REQ, QCH_CON_PPMU_MFC0D0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_MFC0D1_QCH, QCH_CON_PPMU_MFC0D1_QCH_ENABLE, QCH_CON_PPMU_MFC0D1_QCH_CLOCK_REQ, QCH_CON_PPMU_MFC0D1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_WFD_QCH, QCH_CON_PPMU_WFD_QCH_ENABLE, QCH_CON_PPMU_WFD_QCH_CLOCK_REQ, QCH_CON_PPMU_WFD_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_CLK_MFC0_NOCD_MFC0_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC0_NOCD_MFC0_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC0_NOCD_MFC0_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC0_NOCD_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_CLK_MFC0_NOCD_WFD_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC0_NOCD_WFD_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC0_NOCD_WFD_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC0_NOCD_WFD_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF0_MFC0_SW_RESET_QCH, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF0_MFC0_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF0_MFC0_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF0_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF1_MFC0_SW_RESET_QCH, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF1_MFC0_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF1_MFC0_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF1_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF2_MFC0_SW_RESET_QCH, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF2_MFC0_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF2_MFC0_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF2_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF3_MFC0_SW_RESET_QCH, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF3_MFC0_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF3_MFC0_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF3_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF0_MFC0_SW_RESET_QCH, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF0_MFC0_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF0_MFC0_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF0_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF1_MFC0_SW_RESET_QCH, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF1_MFC0_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF1_MFC0_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF1_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF2_MFC0_SW_RESET_QCH, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF2_MFC0_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF2_MFC0_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF2_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF3_MFC0_SW_RESET_QCH, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF3_MFC0_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF3_MFC0_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF3_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_MI_SW_RESET_QCH, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_MI_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_MI_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_MI_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_SI_SW_RESET_QCH, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_SI_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_SI_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_SI_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_SW_RESET_QCH, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SIU_G_PPMU_MFC0_QCH, QCH_CON_SIU_G_PPMU_MFC0_QCH_ENABLE, QCH_CON_SIU_G_PPMU_MFC0_QCH_CLOCK_REQ, QCH_CON_SIU_G_PPMU_MFC0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_SI_G_PPMU_MFC0_QCH, QCH_CON_SLH_AST_SI_G_PPMU_MFC0_QCH_ENABLE, QCH_CON_SLH_AST_SI_G_PPMU_MFC0_QCH_CLOCK_REQ, QCH_CON_SLH_AST_SI_G_PPMU_MFC0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_P_MFC0_QCH, QCH_CON_SLH_AXI_MI_P_MFC0_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_MFC0_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_MFC0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_MFC0D0_QCH_S1, QCH_CON_SYSMMU_MFC0D0_QCH_S1_ENABLE, QCH_CON_SYSMMU_MFC0D0_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_MFC0D0_QCH_S1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_MFC0D0_QCH_S2, QCH_CON_SYSMMU_MFC0D0_QCH_S2_ENABLE, QCH_CON_SYSMMU_MFC0D0_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_MFC0D0_QCH_S2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_MFC0D1_QCH_S1, QCH_CON_SYSMMU_MFC0D1_QCH_S1_ENABLE, QCH_CON_SYSMMU_MFC0D1_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_MFC0D1_QCH_S1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_MFC0D1_QCH_S2, QCH_CON_SYSMMU_MFC0D1_QCH_S2_ENABLE, QCH_CON_SYSMMU_MFC0D1_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_MFC0D1_QCH_S2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_MFC0_QCH, QCH_CON_SYSREG_MFC0_QCH_ENABLE, QCH_CON_SYSREG_MFC0_QCH_CLOCK_REQ, QCH_CON_SYSREG_MFC0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(VGEN_LITE_MFC0_QCH, QCH_CON_VGEN_LITE_MFC0_QCH_ENABLE, QCH_CON_VGEN_LITE_MFC0_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_MFC0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(WFD_QCH, QCH_CON_WFD_QCH_ENABLE, QCH_CON_WFD_QCH_CLOCK_REQ, QCH_CON_WFD_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ADM_APB_MFC0MFC1_QCH, DMYQCH_CON_ADM_APB_MFC0MFC1_QCH_ENABLE, DMYQCH_CON_ADM_APB_MFC0MFC1_QCH_CLOCK_REQ, DMYQCH_CON_ADM_APB_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(D_TZPC_MFC1_QCH, QCH_CON_D_TZPC_MFC1_QCH_ENABLE, QCH_CON_D_TZPC_MFC1_QCH_CLOCK_REQ, QCH_CON_D_TZPC_MFC1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_MI_OTF0_MFC0MFC1_QCH, QCH_CON_LH_AST_MI_OTF0_MFC0MFC1_QCH_ENABLE, QCH_CON_LH_AST_MI_OTF0_MFC0MFC1_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_OTF0_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_MI_OTF1_MFC0MFC1_QCH, QCH_CON_LH_AST_MI_OTF1_MFC0MFC1_QCH_ENABLE, QCH_CON_LH_AST_MI_OTF1_MFC0MFC1_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_OTF1_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_MI_OTF2_MFC0MFC1_QCH, QCH_CON_LH_AST_MI_OTF2_MFC0MFC1_QCH_ENABLE, QCH_CON_LH_AST_MI_OTF2_MFC0MFC1_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_OTF2_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_MI_OTF3_MFC0MFC1_QCH, QCH_CON_LH_AST_MI_OTF3_MFC0MFC1_QCH_ENABLE, QCH_CON_LH_AST_MI_OTF3_MFC0MFC1_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_OTF3_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_SI_OTF0_MFC1MFC0_QCH, QCH_CON_LH_AST_SI_OTF0_MFC1MFC0_QCH_ENABLE, QCH_CON_LH_AST_SI_OTF0_MFC1MFC0_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_OTF0_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_SI_OTF1_MFC1MFC0_QCH, QCH_CON_LH_AST_SI_OTF1_MFC1MFC0_QCH_ENABLE, QCH_CON_LH_AST_SI_OTF1_MFC1MFC0_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_OTF1_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_SI_OTF2_MFC1MFC0_QCH, QCH_CON_LH_AST_SI_OTF2_MFC1MFC0_QCH_ENABLE, QCH_CON_LH_AST_SI_OTF2_MFC1MFC0_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_OTF2_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_SI_OTF3_MFC1MFC0_QCH, QCH_CON_LH_AST_SI_OTF3_MFC1MFC0_QCH_ENABLE, QCH_CON_LH_AST_SI_OTF3_MFC1MFC0_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_OTF3_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_D0_MFC1_QCH, QCH_CON_LH_AXI_SI_D0_MFC1_QCH_ENABLE, QCH_CON_LH_AXI_SI_D0_MFC1_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D0_MFC1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_D1_MFC1_QCH, QCH_CON_LH_AXI_SI_D1_MFC1_QCH_ENABLE, QCH_CON_LH_AXI_SI_D1_MFC1_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D1_MFC1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(MFC1_QCH, QCH_CON_MFC1_QCH_ENABLE, QCH_CON_MFC1_QCH_CLOCK_REQ, QCH_CON_MFC1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(MFC1_CMU_MFC1_QCH, QCH_CON_MFC1_CMU_MFC1_QCH_ENABLE, QCH_CON_MFC1_CMU_MFC1_QCH_CLOCK_REQ, QCH_CON_MFC1_CMU_MFC1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_MFC1D0_QCH, QCH_CON_PPMU_MFC1D0_QCH_ENABLE, QCH_CON_PPMU_MFC1D0_QCH_CLOCK_REQ, QCH_CON_PPMU_MFC1D0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_MFC1D1_QCH, QCH_CON_PPMU_MFC1D1_QCH_ENABLE, QCH_CON_PPMU_MFC1D1_QCH_CLOCK_REQ, QCH_CON_PPMU_MFC1D1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_CLK_MFC1_NOCD_MFC1_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC1_NOCD_MFC1_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC1_NOCD_MFC1_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC1_NOCD_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF0_MFC1_SW_RESET_QCH, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF0_MFC1_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF0_MFC1_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF0_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF1_MFC1_SW_RESET_QCH, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF1_MFC1_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF1_MFC1_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF1_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF2_MFC1_SW_RESET_QCH, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF2_MFC1_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF2_MFC1_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF2_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF3_MFC1_SW_RESET_QCH, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF3_MFC1_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF3_MFC1_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF3_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF0_MFC1_SW_RESET_QCH, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF0_MFC1_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF0_MFC1_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF0_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF1_MFC1_SW_RESET_QCH, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF1_MFC1_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF1_MFC1_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF1_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF2_MFC1_SW_RESET_QCH, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF2_MFC1_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF2_MFC1_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF2_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF3_MFC1_SW_RESET_QCH, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF3_MFC1_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF3_MFC1_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF3_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_SW_RESET_QCH, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SIU_G_PPMU_MFC1_QCH, QCH_CON_SIU_G_PPMU_MFC1_QCH_ENABLE, QCH_CON_SIU_G_PPMU_MFC1_QCH_CLOCK_REQ, QCH_CON_SIU_G_PPMU_MFC1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_SI_G_PPMU_MFC1_QCH, QCH_CON_SLH_AST_SI_G_PPMU_MFC1_QCH_ENABLE, QCH_CON_SLH_AST_SI_G_PPMU_MFC1_QCH_CLOCK_REQ, QCH_CON_SLH_AST_SI_G_PPMU_MFC1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_P_MFC1_QCH, QCH_CON_SLH_AXI_MI_P_MFC1_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_MFC1_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_MFC1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_MFC1D0_QCH_S1, QCH_CON_SYSMMU_MFC1D0_QCH_S1_ENABLE, QCH_CON_SYSMMU_MFC1D0_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_MFC1D0_QCH_S1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_MFC1D0_QCH_S2, QCH_CON_SYSMMU_MFC1D0_QCH_S2_ENABLE, QCH_CON_SYSMMU_MFC1D0_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_MFC1D0_QCH_S2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_MFC1D1_QCH_S1, QCH_CON_SYSMMU_MFC1D1_QCH_S1_ENABLE, QCH_CON_SYSMMU_MFC1D1_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_MFC1D1_QCH_S1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_MFC1D1_QCH_S2, QCH_CON_SYSMMU_MFC1D1_QCH_S2_ENABLE, QCH_CON_SYSMMU_MFC1D1_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_MFC1D1_QCH_S2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_MFC1_QCH, QCH_CON_SYSREG_MFC1_QCH_ENABLE, QCH_CON_SYSREG_MFC1_QCH_CLOCK_REQ, QCH_CON_SYSREG_MFC1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(VGEN_MFC1_QCH, QCH_CON_VGEN_MFC1_QCH_ENABLE, QCH_CON_VGEN_MFC1_QCH_CLOCK_REQ, QCH_CON_VGEN_MFC1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(BUSIF_DDD_MIF_QCH, QCH_CON_BUSIF_DDD_MIF_QCH_ENABLE, QCH_CON_BUSIF_DDD_MIF_QCH_CLOCK_REQ, QCH_CON_BUSIF_DDD_MIF_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CMU_MIF_CMUREF_QCH, DMYQCH_CON_CMU_MIF_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_MIF_CMUREF_QCH_CLOCK_REQ, DMYQCH_CON_CMU_MIF_CMUREF_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DMC_QCH, QCH_CON_DMC_QCH_ENABLE, QCH_CON_DMC_QCH_CLOCK_REQ, QCH_CON_DMC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(D_TZPC_MIF_QCH, QCH_CON_D_TZPC_MIF_QCH_ENABLE, QCH_CON_D_TZPC_MIF_QCH_CLOCK_REQ, QCH_CON_D_TZPC_MIF_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(MIF_CMU_MIF_QCH, QCH_CON_MIF_CMU_MIF_QCH_ENABLE, QCH_CON_MIF_CMU_MIF_QCH_CLOCK_REQ, QCH_CON_MIF_CMU_MIF_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(QCH_ADAPTER_DDRPHY_QCH, QCH_CON_QCH_ADAPTER_DDRPHY_QCH_ENABLE, QCH_CON_QCH_ADAPTER_DDRPHY_QCH_CLOCK_REQ, QCH_CON_QCH_ADAPTER_DDRPHY_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(QCH_ADAPTER_DMC_QCH, QCH_CON_QCH_ADAPTER_DMC_QCH_ENABLE, QCH_CON_QCH_ADAPTER_DMC_QCH_CLOCK_REQ, QCH_CON_QCH_ADAPTER_DMC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(QCH_ADAPTER_PPC_DEBUG_QCH, QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH_ENABLE, QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH_CLOCK_REQ, QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_SI_G_PPMU_MIF_QCH, QCH_CON_SLH_AST_SI_G_PPMU_MIF_QCH_ENABLE, QCH_CON_SLH_AST_SI_G_PPMU_MIF_QCH_CLOCK_REQ, QCH_CON_SLH_AST_SI_G_PPMU_MIF_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_P_MIF_QCH, QCH_CON_SLH_AXI_MI_P_MIF_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_MIF_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_MIF_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SPC_MIF_QCH, QCH_CON_SPC_MIF_QCH_ENABLE, QCH_CON_SPC_MIF_QCH_CLOCK_REQ, QCH_CON_SPC_MIF_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_MIF_QCH, QCH_CON_SYSREG_MIF_QCH_ENABLE, QCH_CON_SYSREG_MIF_QCH_CLOCK_REQ, QCH_CON_SYSREG_MIF_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_PRIVATE_MIF_QCH, QCH_CON_SYSREG_PRIVATE_MIF_QCH_ENABLE, QCH_CON_SYSREG_PRIVATE_MIF_QCH_CLOCK_REQ, QCH_CON_SYSREG_PRIVATE_MIF_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(BAAW_CP_QCH, QCH_CON_BAAW_CP_QCH_ENABLE, QCH_CON_BAAW_CP_QCH_CLOCK_REQ, QCH_CON_BAAW_CP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(BAAW_P_GNSS_QCH, QCH_CON_BAAW_P_GNSS_QCH_ENABLE, QCH_CON_BAAW_P_GNSS_QCH_CLOCK_REQ, QCH_CON_BAAW_P_GNSS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(BDU_QCH, QCH_CON_BDU_QCH_ENABLE, QCH_CON_BDU_QCH_CLOCK_REQ, QCH_CON_BDU_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CACHEAID_NOCL0_QCH, QCH_CON_CACHEAID_NOCL0_QCH_ENABLE, QCH_CON_CACHEAID_NOCL0_QCH_CLOCK_REQ, QCH_CON_CACHEAID_NOCL0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CCI_QCH, DMYQCH_CON_CCI_QCH_ENABLE, DMYQCH_CON_CCI_QCH_CLOCK_REQ, DMYQCH_CON_CCI_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CCI_QCH_S, QCH_CON_CCI_QCH_S_ENABLE, QCH_CON_CCI_QCH_S_CLOCK_REQ, QCH_CON_CCI_QCH_S_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CMU_NOCL0_CMUREF_QCH, DMYQCH_CON_CMU_NOCL0_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_NOCL0_CMUREF_QCH_CLOCK_REQ, DMYQCH_CON_CMU_NOCL0_CMUREF_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(D_TZPC_NOCL0_QCH, QCH_CON_D_TZPC_NOCL0_QCH_ENABLE, QCH_CON_D_TZPC_NOCL0_QCH_CLOCK_REQ, QCH_CON_D_TZPC_NOCL0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_ACEL_MI_D0_G3D_QCH, QCH_CON_LH_ACEL_MI_D0_G3D_QCH_ENABLE, QCH_CON_LH_ACEL_MI_D0_G3D_QCH_CLOCK_REQ, QCH_CON_LH_ACEL_MI_D0_G3D_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_ACEL_MI_D1_G3D_QCH, QCH_CON_LH_ACEL_MI_D1_G3D_QCH_ENABLE, QCH_CON_LH_ACEL_MI_D1_G3D_QCH_CLOCK_REQ, QCH_CON_LH_ACEL_MI_D1_G3D_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_ACEL_MI_D2_G3D_QCH, QCH_CON_LH_ACEL_MI_D2_G3D_QCH_ENABLE, QCH_CON_LH_ACEL_MI_D2_G3D_QCH_CLOCK_REQ, QCH_CON_LH_ACEL_MI_D2_G3D_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_ACEL_MI_D3_G3D_QCH, QCH_CON_LH_ACEL_MI_D3_G3D_QCH_ENABLE, QCH_CON_LH_ACEL_MI_D3_G3D_QCH_CLOCK_REQ, QCH_CON_LH_ACEL_MI_D3_G3D_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_ACEL_SI_D0_ACP_QCH, QCH_CON_LH_ACEL_SI_D0_ACP_QCH_ENABLE, QCH_CON_LH_ACEL_SI_D0_ACP_QCH_CLOCK_REQ, QCH_CON_LH_ACEL_SI_D0_ACP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_ACEL_SI_D1_ACP_QCH, QCH_CON_LH_ACEL_SI_D1_ACP_QCH_ENABLE, QCH_CON_LH_ACEL_SI_D1_ACP_QCH_CLOCK_REQ, QCH_CON_LH_ACEL_SI_D1_ACP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_MI_G_NOCL1A_QCH, QCH_CON_LH_AST_MI_G_NOCL1A_QCH_ENABLE, QCH_CON_LH_AST_MI_G_NOCL1A_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_G_NOCL1A_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_MI_G_NOCL1B_QCH, QCH_CON_LH_AST_MI_G_NOCL1B_QCH_ENABLE, QCH_CON_LH_AST_MI_G_NOCL1B_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_G_NOCL1B_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_MI_G_NOCL1C_QCH, QCH_CON_LH_AST_MI_G_NOCL1C_QCH_ENABLE, QCH_CON_LH_AST_MI_G_NOCL1C_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_G_NOCL1C_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_ATB_SI_T_BDU_QCH, QCH_CON_LH_ATB_SI_T_BDU_QCH_ENABLE, QCH_CON_LH_ATB_SI_T_BDU_QCH_CLOCK_REQ, QCH_CON_LH_ATB_SI_T_BDU_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_D_APM_QCH, QCH_CON_LH_AXI_MI_D_APM_QCH_ENABLE, QCH_CON_LH_AXI_MI_D_APM_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D_APM_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_G_CSSYS_QCH, QCH_CON_LH_AXI_MI_G_CSSYS_QCH_ENABLE, QCH_CON_LH_AXI_MI_G_CSSYS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_G_CSSYS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_IG_CSSYS_NOCL0_QCH, QCH_CON_LH_AXI_MI_IG_CSSYS_NOCL0_QCH_ENABLE, QCH_CON_LH_AXI_MI_IG_CSSYS_NOCL0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_IG_CSSYS_NOCL0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_IG_CSSYS_NOCL0_QCH, QCH_CON_LH_AXI_SI_IG_CSSYS_NOCL0_QCH_ENABLE, QCH_CON_LH_AXI_SI_IG_CSSYS_NOCL0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_IG_CSSYS_NOCL0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_CHI_MI_D0_CLUSTER0_QCH, QCH_CON_LH_CHI_MI_D0_CLUSTER0_QCH_ENABLE, QCH_CON_LH_CHI_MI_D0_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LH_CHI_MI_D0_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_CHI_MI_D1_CLUSTER0_QCH, QCH_CON_LH_CHI_MI_D1_CLUSTER0_QCH_ENABLE, QCH_CON_LH_CHI_MI_D1_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LH_CHI_MI_D1_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_QDI_MI_D_AUD_QCH, QCH_CON_LH_QDI_MI_D_AUD_QCH_ENABLE, QCH_CON_LH_QDI_MI_D_AUD_QCH_CLOCK_REQ, QCH_CON_LH_QDI_MI_D_AUD_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(NOCIF_CMUTOPC_QCH, QCH_CON_NOCIF_CMUTOPC_QCH_ENABLE, QCH_CON_NOCIF_CMUTOPC_QCH_CLOCK_REQ, QCH_CON_NOCIF_CMUTOPC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(NOCL0_CMU_NOCL0_QCH, QCH_CON_NOCL0_CMU_NOCL0_QCH_ENABLE, QCH_CON_NOCL0_CMU_NOCL0_QCH_CLOCK_REQ, QCH_CON_NOCL0_CMU_NOCL0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PBHA_GEN_D0_MODEM_QCH, QCH_CON_PBHA_GEN_D0_MODEM_QCH_ENABLE, QCH_CON_PBHA_GEN_D0_MODEM_QCH_CLOCK_REQ, QCH_CON_PBHA_GEN_D0_MODEM_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PBHA_GEN_D1_MODEM_QCH, QCH_CON_PBHA_GEN_D1_MODEM_QCH_ENABLE, QCH_CON_PBHA_GEN_D1_MODEM_QCH_CLOCK_REQ, QCH_CON_PBHA_GEN_D1_MODEM_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPC_SCI_QCH, QCH_CON_PPC_SCI_QCH_ENABLE, QCH_CON_PPC_SCI_QCH_CLOCK_REQ, QCH_CON_PPC_SCI_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_APM_QCH, QCH_CON_PPMU_APM_QCH_ENABLE, QCH_CON_PPMU_APM_QCH_CLOCK_REQ, QCH_CON_PPMU_APM_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_CPUCL0_0_QCH, QCH_CON_PPMU_CPUCL0_0_QCH_ENABLE, QCH_CON_PPMU_CPUCL0_0_QCH_CLOCK_REQ, QCH_CON_PPMU_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_CPUCL0_1_QCH, QCH_CON_PPMU_CPUCL0_1_QCH_ENABLE, QCH_CON_PPMU_CPUCL0_1_QCH_CLOCK_REQ, QCH_CON_PPMU_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_G3D0_QCH, QCH_CON_PPMU_G3D0_QCH_ENABLE, QCH_CON_PPMU_G3D0_QCH_CLOCK_REQ, QCH_CON_PPMU_G3D0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_G3D1_QCH, QCH_CON_PPMU_G3D1_QCH_ENABLE, QCH_CON_PPMU_G3D1_QCH_CLOCK_REQ, QCH_CON_PPMU_G3D1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_G3D2_QCH, QCH_CON_PPMU_G3D2_QCH_ENABLE, QCH_CON_PPMU_G3D2_QCH_CLOCK_REQ, QCH_CON_PPMU_G3D2_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_G3D3_QCH, QCH_CON_PPMU_G3D3_QCH_ENABLE, QCH_CON_PPMU_G3D3_QCH_CLOCK_REQ, QCH_CON_PPMU_G3D3_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_SYNC_GEN_QCH, DMYQCH_CON_PPMU_SYNC_GEN_QCH_ENABLE, DMYQCH_CON_PPMU_SYNC_GEN_QCH_CLOCK_REQ, DMYQCH_CON_PPMU_SYNC_GEN_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_CLK_NOCL0_NOCD_CCI_QCH, QCH_CON_RSTNSYNC_CLK_NOCL0_NOCD_CCI_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_NOCL0_NOCD_CCI_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_NOCL0_NOCD_CCI_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_CLK_NOCL0_NOCP_CCI_QCH, QCH_CON_RSTNSYNC_CLK_NOCL0_NOCP_CCI_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_NOCL0_NOCP_CCI_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_NOCL0_NOCP_CCI_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_SR_CLK_NOCL0_NOCD_CCI_QCH, QCH_CON_RSTNSYNC_SR_CLK_NOCL0_NOCD_CCI_QCH_ENABLE, QCH_CON_RSTNSYNC_SR_CLK_NOCL0_NOCD_CCI_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_SR_CLK_NOCL0_NOCD_CCI_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SIU_G0_PPMU_NOCL0_QCH, QCH_CON_SIU_G0_PPMU_NOCL0_QCH_ENABLE, QCH_CON_SIU_G0_PPMU_NOCL0_QCH_CLOCK_REQ, QCH_CON_SIU_G0_PPMU_NOCL0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SIU_G1_PPMU_NOCL0_QCH, QCH_CON_SIU_G1_PPMU_NOCL0_QCH_ENABLE, QCH_CON_SIU_G1_PPMU_NOCL0_QCH_CLOCK_REQ, QCH_CON_SIU_G1_PPMU_NOCL0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SIU_G2_PPMU_NOCL0_QCH, QCH_CON_SIU_G2_PPMU_NOCL0_QCH_ENABLE, QCH_CON_SIU_G2_PPMU_NOCL0_QCH_CLOCK_REQ, QCH_CON_SIU_G2_PPMU_NOCL0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SIU_G3_PPMU_NOCL0_QCH, QCH_CON_SIU_G3_PPMU_NOCL0_QCH_ENABLE, QCH_CON_SIU_G3_PPMU_NOCL0_QCH_CLOCK_REQ, QCH_CON_SIU_G3_PPMU_NOCL0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SIU_G4_PPMU_NOCL0_QCH, QCH_CON_SIU_G4_PPMU_NOCL0_QCH_ENABLE, QCH_CON_SIU_G4_PPMU_NOCL0_QCH_CLOCK_REQ, QCH_CON_SIU_G4_PPMU_NOCL0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SIU_G5_PPMU_NOCL0_QCH, QCH_CON_SIU_G5_PPMU_NOCL0_QCH_ENABLE, QCH_CON_SIU_G5_PPMU_NOCL0_QCH_CLOCK_REQ, QCH_CON_SIU_G5_PPMU_NOCL0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_ACEL_MI_D_SSP_QCH, QCH_CON_SLH_ACEL_MI_D_SSP_QCH_ENABLE, QCH_CON_SLH_ACEL_MI_D_SSP_QCH_CLOCK_REQ, QCH_CON_SLH_ACEL_MI_D_SSP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_MI_G_PPMU_AUD_QCH, QCH_CON_SLH_AST_MI_G_PPMU_AUD_QCH_ENABLE, QCH_CON_SLH_AST_MI_G_PPMU_AUD_QCH_CLOCK_REQ, QCH_CON_SLH_AST_MI_G_PPMU_AUD_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_MI_G_PPMU_GNSS_QCH, QCH_CON_SLH_AST_MI_G_PPMU_GNSS_QCH_ENABLE, QCH_CON_SLH_AST_MI_G_PPMU_GNSS_QCH_CLOCK_REQ, QCH_CON_SLH_AST_MI_G_PPMU_GNSS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_MI_G_PPMU_MIF0_QCH, QCH_CON_SLH_AST_MI_G_PPMU_MIF0_QCH_ENABLE, QCH_CON_SLH_AST_MI_G_PPMU_MIF0_QCH_CLOCK_REQ, QCH_CON_SLH_AST_MI_G_PPMU_MIF0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_MI_G_PPMU_MIF1_QCH, QCH_CON_SLH_AST_MI_G_PPMU_MIF1_QCH_ENABLE, QCH_CON_SLH_AST_MI_G_PPMU_MIF1_QCH_CLOCK_REQ, QCH_CON_SLH_AST_MI_G_PPMU_MIF1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_MI_G_PPMU_MIF2_QCH, QCH_CON_SLH_AST_MI_G_PPMU_MIF2_QCH_ENABLE, QCH_CON_SLH_AST_MI_G_PPMU_MIF2_QCH_CLOCK_REQ, QCH_CON_SLH_AST_MI_G_PPMU_MIF2_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_MI_G_PPMU_MIF3_QCH, QCH_CON_SLH_AST_MI_G_PPMU_MIF3_QCH_ENABLE, QCH_CON_SLH_AST_MI_G_PPMU_MIF3_QCH_CLOCK_REQ, QCH_CON_SLH_AST_MI_G_PPMU_MIF3_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_MI_G_PPMU_MODEM_QCH, QCH_CON_SLH_AST_MI_G_PPMU_MODEM_QCH_ENABLE, QCH_CON_SLH_AST_MI_G_PPMU_MODEM_QCH_CLOCK_REQ, QCH_CON_SLH_AST_MI_G_PPMU_MODEM_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_MI_G_PPMU_NOCL1A_QCH, QCH_CON_SLH_AST_MI_G_PPMU_NOCL1A_QCH_ENABLE, QCH_CON_SLH_AST_MI_G_PPMU_NOCL1A_QCH_CLOCK_REQ, QCH_CON_SLH_AST_MI_G_PPMU_NOCL1A_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_MI_G_PPMU_NOCL1B_QCH, QCH_CON_SLH_AST_MI_G_PPMU_NOCL1B_QCH_ENABLE, QCH_CON_SLH_AST_MI_G_PPMU_NOCL1B_QCH_CLOCK_REQ, QCH_CON_SLH_AST_MI_G_PPMU_NOCL1B_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_MI_G_PPMU_NOCL1C_QCH, QCH_CON_SLH_AST_MI_G_PPMU_NOCL1C_QCH_ENABLE, QCH_CON_SLH_AST_MI_G_PPMU_NOCL1C_QCH_CLOCK_REQ, QCH_CON_SLH_AST_MI_G_PPMU_NOCL1C_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_MI_G_PPMU_SSP_QCH, QCH_CON_SLH_AST_MI_G_PPMU_SSP_QCH_ENABLE, QCH_CON_SLH_AST_MI_G_PPMU_SSP_QCH_CLOCK_REQ, QCH_CON_SLH_AST_MI_G_PPMU_SSP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_MI_G_PPMU_UFD_QCH, QCH_CON_SLH_AST_MI_G_PPMU_UFD_QCH_ENABLE, QCH_CON_SLH_AST_MI_G_PPMU_UFD_QCH_CLOCK_REQ, QCH_CON_SLH_AST_MI_G_PPMU_UFD_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_MI_IG_DEBUG_MUX_NOCL0_QCH, QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL0_QCH_ENABLE, QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL0_QCH_CLOCK_REQ, QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_MI_IG_PPMU_P_CLUSTER0_QCH, QCH_CON_SLH_AST_MI_IG_PPMU_P_CLUSTER0_QCH_ENABLE, QCH_CON_SLH_AST_MI_IG_PPMU_P_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_SLH_AST_MI_IG_PPMU_P_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_SI_IG_DEBUG_MUX_NOCL0_QCH, QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL0_QCH_ENABLE, QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL0_QCH_CLOCK_REQ, QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_SI_IG_PPMU_P_CLUSTER0_QCH, QCH_CON_SLH_AST_SI_IG_PPMU_P_CLUSTER0_QCH_ENABLE, QCH_CON_SLH_AST_SI_IG_PPMU_P_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_SLH_AST_SI_IG_PPMU_P_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_D0_MODEM_QCH, QCH_CON_SLH_AXI_MI_D0_MODEM_QCH_ENABLE, QCH_CON_SLH_AXI_MI_D0_MODEM_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_D0_MODEM_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_D1_MODEM_QCH, QCH_CON_SLH_AXI_MI_D1_MODEM_QCH_ENABLE, QCH_CON_SLH_AXI_MI_D1_MODEM_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_D1_MODEM_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_D2_MODEM_QCH, QCH_CON_SLH_AXI_MI_D2_MODEM_QCH_ENABLE, QCH_CON_SLH_AXI_MI_D2_MODEM_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_D2_MODEM_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_D_UFD_QCH, QCH_CON_SLH_AXI_MI_D_UFD_QCH_ENABLE, QCH_CON_SLH_AXI_MI_D_UFD_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_D_UFD_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_P_CLUSTER0_NOCL0_QCH, QCH_CON_SLH_AXI_MI_P_CLUSTER0_NOCL0_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_CLUSTER0_NOCL0_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_CLUSTER0_NOCL0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_P_APM_QCH, QCH_CON_SLH_AXI_SI_P_APM_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_APM_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_APM_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_P_AUD_QCH, QCH_CON_SLH_AXI_SI_P_AUD_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_AUD_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_AUD_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_P_CPUCL0_QCH, QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_P_G3D_QCH, QCH_CON_SLH_AXI_SI_P_G3D_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_G3D_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_G3D_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_P_GNSS_QCH, QCH_CON_SLH_AXI_SI_P_GNSS_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_GNSS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_GNSS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_P_MCW_QCH, QCH_CON_SLH_AXI_SI_P_MCW_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_MCW_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_MCW_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_P_MIF0_QCH, QCH_CON_SLH_AXI_SI_P_MIF0_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_MIF0_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_MIF0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_P_MIF1_QCH, QCH_CON_SLH_AXI_SI_P_MIF1_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_MIF1_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_MIF1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_P_MIF2_QCH, QCH_CON_SLH_AXI_SI_P_MIF2_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_MIF2_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_MIF2_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_P_MIF3_QCH, QCH_CON_SLH_AXI_SI_P_MIF3_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_MIF3_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_MIF3_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_P_MODEM_QCH, QCH_CON_SLH_AXI_SI_P_MODEM_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_MODEM_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_MODEM_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_P_PERIC1_QCH, QCH_CON_SLH_AXI_SI_P_PERIC1_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_PERIC1_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_PERIC1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_P_PERIS_QCH, QCH_CON_SLH_AXI_SI_P_PERIS_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_PERIS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_PERIS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_P_PERISGIC_QCH, QCH_CON_SLH_AXI_SI_P_PERISGIC_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_PERISGIC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_PERISGIC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_P_SSP_QCH, QCH_CON_SLH_AXI_SI_P_SSP_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_SSP_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_SSP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_P_UFD_QCH, QCH_CON_SLH_AXI_SI_P_UFD_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_UFD_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_UFD_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_MODEM_QCH_S1, QCH_CON_SYSMMU_MODEM_QCH_S1_ENABLE, QCH_CON_SYSMMU_MODEM_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_MODEM_QCH_S1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_MODEM_QCH_S2, QCH_CON_SYSMMU_MODEM_QCH_S2_ENABLE, QCH_CON_SYSMMU_MODEM_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_MODEM_QCH_S2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_S2_APM_QCH, QCH_CON_SYSMMU_S2_APM_QCH_ENABLE, QCH_CON_SYSMMU_S2_APM_QCH_CLOCK_REQ, QCH_CON_SYSMMU_S2_APM_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_S2_G3D_QCH_S0, QCH_CON_SYSMMU_S2_G3D_QCH_S0_ENABLE, QCH_CON_SYSMMU_S2_G3D_QCH_S0_CLOCK_REQ, QCH_CON_SYSMMU_S2_G3D_QCH_S0_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_S2_G3D_QCH_S1, QCH_CON_SYSMMU_S2_G3D_QCH_S1_ENABLE, QCH_CON_SYSMMU_S2_G3D_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_S2_G3D_QCH_S1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_S2_G3D_QCH_S2, QCH_CON_SYSMMU_S2_G3D_QCH_S2_ENABLE, QCH_CON_SYSMMU_S2_G3D_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_S2_G3D_QCH_S2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_S2_G3D_QCH_S3, QCH_CON_SYSMMU_S2_G3D_QCH_S3_ENABLE, QCH_CON_SYSMMU_S2_G3D_QCH_S3_CLOCK_REQ, QCH_CON_SYSMMU_S2_G3D_QCH_S3_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_S2_G3D_QCH_S4, QCH_CON_SYSMMU_S2_G3D_QCH_S4_ENABLE, QCH_CON_SYSMMU_S2_G3D_QCH_S4_CLOCK_REQ, QCH_CON_SYSMMU_S2_G3D_QCH_S4_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_NOCL0_QCH, QCH_CON_SYSREG_NOCL0_QCH_ENABLE, QCH_CON_SYSREG_NOCL0_QCH_CLOCK_REQ, QCH_CON_SYSREG_NOCL0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(TREX_D0_ACP_QCH, QCH_CON_TREX_D0_ACP_QCH_ENABLE, QCH_CON_TREX_D0_ACP_QCH_CLOCK_REQ, QCH_CON_TREX_D0_ACP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(TREX_D1_ACP_QCH, QCH_CON_TREX_D1_ACP_QCH_ENABLE, QCH_CON_TREX_D1_ACP_QCH_CLOCK_REQ, QCH_CON_TREX_D1_ACP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(TREX_D_NOCL0_QCH, QCH_CON_TREX_D_NOCL0_QCH_ENABLE, QCH_CON_TREX_D_NOCL0_QCH_CLOCK_REQ, QCH_CON_TREX_D_NOCL0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(TREX_P_NOCL0_QCH, QCH_CON_TREX_P_NOCL0_QCH_ENABLE, QCH_CON_TREX_P_NOCL0_QCH_CLOCK_REQ, QCH_CON_TREX_P_NOCL0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(VGEN_D0_G3D_QCH, QCH_CON_VGEN_D0_G3D_QCH_ENABLE, QCH_CON_VGEN_D0_G3D_QCH_CLOCK_REQ, QCH_CON_VGEN_D0_G3D_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(VGEN_D1_G3D_QCH, QCH_CON_VGEN_D1_G3D_QCH_ENABLE, QCH_CON_VGEN_D1_G3D_QCH_CLOCK_REQ, QCH_CON_VGEN_D1_G3D_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(VGEN_D2_G3D_QCH, QCH_CON_VGEN_D2_G3D_QCH_ENABLE, QCH_CON_VGEN_D2_G3D_QCH_CLOCK_REQ, QCH_CON_VGEN_D2_G3D_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(VGEN_D3_G3D_QCH, QCH_CON_VGEN_D3_G3D_QCH_ENABLE, QCH_CON_VGEN_D3_G3D_QCH_CLOCK_REQ, QCH_CON_VGEN_D3_G3D_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(VGEN_LITE_MODEM_QCH, QCH_CON_VGEN_LITE_MODEM_QCH_ENABLE, QCH_CON_VGEN_LITE_MODEM_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_MODEM_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(WOW_DVFS_D0_CPUCL0_QCH, QCH_CON_WOW_DVFS_D0_CPUCL0_QCH_ENABLE, QCH_CON_WOW_DVFS_D0_CPUCL0_QCH_CLOCK_REQ, QCH_CON_WOW_DVFS_D0_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(WOW_DVFS_D0_G3D_QCH, QCH_CON_WOW_DVFS_D0_G3D_QCH_ENABLE, QCH_CON_WOW_DVFS_D0_G3D_QCH_CLOCK_REQ, QCH_CON_WOW_DVFS_D0_G3D_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(WOW_DVFS_D0_MIF_QCH, QCH_CON_WOW_DVFS_D0_MIF_QCH_ENABLE, QCH_CON_WOW_DVFS_D0_MIF_QCH_CLOCK_REQ, QCH_CON_WOW_DVFS_D0_MIF_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(WOW_DVFS_D1_CPUCL0_QCH, QCH_CON_WOW_DVFS_D1_CPUCL0_QCH_ENABLE, QCH_CON_WOW_DVFS_D1_CPUCL0_QCH_CLOCK_REQ, QCH_CON_WOW_DVFS_D1_CPUCL0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(WOW_DVFS_D1_MIF_QCH, QCH_CON_WOW_DVFS_D1_MIF_QCH_ENABLE, QCH_CON_WOW_DVFS_D1_MIF_QCH_CLOCK_REQ, QCH_CON_WOW_DVFS_D1_MIF_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(WOW_DVFS_D2_MIF_QCH, QCH_CON_WOW_DVFS_D2_MIF_QCH_ENABLE, QCH_CON_WOW_DVFS_D2_MIF_QCH_CLOCK_REQ, QCH_CON_WOW_DVFS_D2_MIF_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(WOW_DVFS_D3_MIF_QCH, QCH_CON_WOW_DVFS_D3_MIF_QCH_ENABLE, QCH_CON_WOW_DVFS_D3_MIF_QCH_CLOCK_REQ, QCH_CON_WOW_DVFS_D3_MIF_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(WOW_DVFS_IRPS0_QCH, QCH_CON_WOW_DVFS_IRPS0_QCH_ENABLE, QCH_CON_WOW_DVFS_IRPS0_QCH_CLOCK_REQ, QCH_CON_WOW_DVFS_IRPS0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(WOW_DVFS_IRPS1_QCH, QCH_CON_WOW_DVFS_IRPS1_QCH_ENABLE, QCH_CON_WOW_DVFS_IRPS1_QCH_CLOCK_REQ, QCH_CON_WOW_DVFS_IRPS1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(WOW_DVFS_IRPS2_QCH, QCH_CON_WOW_DVFS_IRPS2_QCH_ENABLE, QCH_CON_WOW_DVFS_IRPS2_QCH_CLOCK_REQ, QCH_CON_WOW_DVFS_IRPS2_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(WOW_DVFS_IRPS3_QCH, QCH_CON_WOW_DVFS_IRPS3_QCH_ENABLE, QCH_CON_WOW_DVFS_IRPS3_QCH_CLOCK_REQ, QCH_CON_WOW_DVFS_IRPS3_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(WOW_DVFS_NOCL0_QCH, QCH_CON_WOW_DVFS_NOCL0_QCH_ENABLE, QCH_CON_WOW_DVFS_NOCL0_QCH_CLOCK_REQ, QCH_CON_WOW_DVFS_NOCL0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(BAAW_P_DNC_QCH, QCH_CON_BAAW_P_DNC_QCH_ENABLE, QCH_CON_BAAW_P_DNC_QCH_CLOCK_REQ, QCH_CON_BAAW_P_DNC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CMU_NOCL1A_CMUREF_QCH, DMYQCH_CON_CMU_NOCL1A_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_NOCL1A_CMUREF_QCH_CLOCK_REQ, DMYQCH_CON_CMU_NOCL1A_CMUREF_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(D_TZPC_NOCL1A_QCH, QCH_CON_D_TZPC_NOCL1A_QCH_ENABLE, QCH_CON_D_TZPC_NOCL1A_QCH_CLOCK_REQ, QCH_CON_D_TZPC_NOCL1A_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_ACEL_MI_D_HSI1_QCH, QCH_CON_LH_ACEL_MI_D_HSI1_QCH_ENABLE, QCH_CON_LH_ACEL_MI_D_HSI1_QCH_CLOCK_REQ, QCH_CON_LH_ACEL_MI_D_HSI1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_ACEL_MI_D_LME_QCH, QCH_CON_LH_ACEL_MI_D_LME_QCH_ENABLE, QCH_CON_LH_ACEL_MI_D_LME_QCH_CLOCK_REQ, QCH_CON_LH_ACEL_MI_D_LME_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_ACEL_MI_D_M2M_QCH, QCH_CON_LH_ACEL_MI_D_M2M_QCH_ENABLE, QCH_CON_LH_ACEL_MI_D_M2M_QCH_CLOCK_REQ, QCH_CON_LH_ACEL_MI_D_M2M_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_SI_G_NOCL1A_QCH, QCH_CON_LH_AST_SI_G_NOCL1A_QCH_ENABLE, QCH_CON_LH_AST_SI_G_NOCL1A_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_G_NOCL1A_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_D0_MFC0_QCH, QCH_CON_LH_AXI_MI_D0_MFC0_QCH_ENABLE, QCH_CON_LH_AXI_MI_D0_MFC0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D0_MFC0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_D0_MFC1_QCH, QCH_CON_LH_AXI_MI_D0_MFC1_QCH_ENABLE, QCH_CON_LH_AXI_MI_D0_MFC1_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D0_MFC1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_D1_DPUF_QCH, QCH_CON_LH_AXI_MI_D1_DPUF_QCH_ENABLE, QCH_CON_LH_AXI_MI_D1_DPUF_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D1_DPUF_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_D1_MFC0_QCH, QCH_CON_LH_AXI_MI_D1_MFC0_QCH_ENABLE, QCH_CON_LH_AXI_MI_D1_MFC0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D1_MFC0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_D1_MFC1_QCH, QCH_CON_LH_AXI_MI_D1_MFC1_QCH_ENABLE, QCH_CON_LH_AXI_MI_D1_MFC1_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D1_MFC1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(NOCL1A_CMU_NOCL1A_QCH, QCH_CON_NOCL1A_CMU_NOCL1A_QCH_ENABLE, QCH_CON_NOCL1A_CMU_NOCL1A_QCH_CLOCK_REQ, QCH_CON_NOCL1A_CMU_NOCL1A_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SIU_2X1_P0_NOCL1A_QCH, QCH_CON_SIU_2X1_P0_NOCL1A_QCH_ENABLE, QCH_CON_SIU_2X1_P0_NOCL1A_QCH_CLOCK_REQ, QCH_CON_SIU_2X1_P0_NOCL1A_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SIU_4X1_P0_NOCL1A_QCH, QCH_CON_SIU_4X1_P0_NOCL1A_QCH_ENABLE, QCH_CON_SIU_4X1_P0_NOCL1A_QCH_CLOCK_REQ, QCH_CON_SIU_4X1_P0_NOCL1A_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SIU_8X1_P0_NOCL1A_QCH, QCH_CON_SIU_8X1_P0_NOCL1A_QCH_ENABLE, QCH_CON_SIU_8X1_P0_NOCL1A_QCH_CLOCK_REQ, QCH_CON_SIU_8X1_P0_NOCL1A_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_MI_G_PPMU_DNC_QCH, QCH_CON_SLH_AST_MI_G_PPMU_DNC_QCH_ENABLE, QCH_CON_SLH_AST_MI_G_PPMU_DNC_QCH_CLOCK_REQ, QCH_CON_SLH_AST_MI_G_PPMU_DNC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_MI_G_PPMU_DPUF_QCH, QCH_CON_SLH_AST_MI_G_PPMU_DPUF_QCH_ENABLE, QCH_CON_SLH_AST_MI_G_PPMU_DPUF_QCH_CLOCK_REQ, QCH_CON_SLH_AST_MI_G_PPMU_DPUF_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_MI_G_PPMU_HSI1_QCH, QCH_CON_SLH_AST_MI_G_PPMU_HSI1_QCH_ENABLE, QCH_CON_SLH_AST_MI_G_PPMU_HSI1_QCH_CLOCK_REQ, QCH_CON_SLH_AST_MI_G_PPMU_HSI1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_MI_G_PPMU_LME_QCH, QCH_CON_SLH_AST_MI_G_PPMU_LME_QCH_ENABLE, QCH_CON_SLH_AST_MI_G_PPMU_LME_QCH_CLOCK_REQ, QCH_CON_SLH_AST_MI_G_PPMU_LME_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_MI_G_PPMU_M2M_QCH, QCH_CON_SLH_AST_MI_G_PPMU_M2M_QCH_ENABLE, QCH_CON_SLH_AST_MI_G_PPMU_M2M_QCH_CLOCK_REQ, QCH_CON_SLH_AST_MI_G_PPMU_M2M_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_MI_G_PPMU_MFC0_QCH, QCH_CON_SLH_AST_MI_G_PPMU_MFC0_QCH_ENABLE, QCH_CON_SLH_AST_MI_G_PPMU_MFC0_QCH_CLOCK_REQ, QCH_CON_SLH_AST_MI_G_PPMU_MFC0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_MI_G_PPMU_MFC1_QCH, QCH_CON_SLH_AST_MI_G_PPMU_MFC1_QCH_ENABLE, QCH_CON_SLH_AST_MI_G_PPMU_MFC1_QCH_CLOCK_REQ, QCH_CON_SLH_AST_MI_G_PPMU_MFC1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_MI_IG_DEBUG_MUX_NOCL1A_QCH, QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1A_QCH_ENABLE, QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1A_QCH_CLOCK_REQ, QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1A_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_MI_IG_PPMU_NOCL1A_QCH, QCH_CON_SLH_AST_MI_IG_PPMU_NOCL1A_QCH_ENABLE, QCH_CON_SLH_AST_MI_IG_PPMU_NOCL1A_QCH_CLOCK_REQ, QCH_CON_SLH_AST_MI_IG_PPMU_NOCL1A_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_SI_G_PPMU_NOCL1A_QCH, QCH_CON_SLH_AST_SI_G_PPMU_NOCL1A_QCH_ENABLE, QCH_CON_SLH_AST_SI_G_PPMU_NOCL1A_QCH_CLOCK_REQ, QCH_CON_SLH_AST_SI_G_PPMU_NOCL1A_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_SI_IG_DEBUG_MUX_NOCL1A_QCH, QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1A_QCH_ENABLE, QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1A_QCH_CLOCK_REQ, QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1A_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_SI_IG_PPMU_NOCL1A_QCH, QCH_CON_SLH_AST_SI_IG_PPMU_NOCL1A_QCH_ENABLE, QCH_CON_SLH_AST_SI_IG_PPMU_NOCL1A_QCH_CLOCK_REQ, QCH_CON_SLH_AST_SI_IG_PPMU_NOCL1A_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_D0_DPUF_QCH, QCH_CON_SLH_AXI_MI_D0_DPUF_QCH_ENABLE, QCH_CON_SLH_AXI_MI_D0_DPUF_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_D0_DPUF_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_P_DNC_QCH, QCH_CON_SLH_AXI_SI_P_DNC_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_DNC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_DNC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_P_DPUB_QCH, QCH_CON_SLH_AXI_SI_P_DPUB_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_DPUB_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_DPUB_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_P_DPUF_QCH, QCH_CON_SLH_AXI_SI_P_DPUF_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_DPUF_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_DPUF_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_P_HSI1_QCH, QCH_CON_SLH_AXI_SI_P_HSI1_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_HSI1_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_HSI1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_P_LME_QCH, QCH_CON_SLH_AXI_SI_P_LME_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_LME_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_LME_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_P_M2M_QCH, QCH_CON_SLH_AXI_SI_P_M2M_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_M2M_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_M2M_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_P_MFC0_QCH, QCH_CON_SLH_AXI_SI_P_MFC0_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_MFC0_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_MFC0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_P_MFC1_QCH, QCH_CON_SLH_AXI_SI_P_MFC1_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_MFC1_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_MFC1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_P_PERIC0_QCH, QCH_CON_SLH_AXI_SI_P_PERIC0_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_PERIC0_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_PERIC0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_P_PERIC2_QCH, QCH_CON_SLH_AXI_SI_P_PERIC2_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_PERIC2_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_PERIC2_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_NOCL1A_QCH, QCH_CON_SYSREG_NOCL1A_QCH_ENABLE, QCH_CON_SYSREG_NOCL1A_QCH_CLOCK_REQ, QCH_CON_SYSREG_NOCL1A_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(TREX_D_NOCL1A_QCH, QCH_CON_TREX_D_NOCL1A_QCH_ENABLE, QCH_CON_TREX_D_NOCL1A_QCH_CLOCK_REQ, QCH_CON_TREX_D_NOCL1A_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(TREX_P_NOCL1A_QCH, QCH_CON_TREX_P_NOCL1A_QCH_ENABLE, QCH_CON_TREX_P_NOCL1A_QCH_CLOCK_REQ, QCH_CON_TREX_P_NOCL1A_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CMU_NOCL1B_CMUREF_QCH, DMYQCH_CON_CMU_NOCL1B_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_NOCL1B_CMUREF_QCH_CLOCK_REQ, DMYQCH_CON_CMU_NOCL1B_CMUREF_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DIT_QCH, QCH_CON_DIT_QCH_ENABLE, QCH_CON_DIT_QCH_CLOCK_REQ, QCH_CON_DIT_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(D_TZPC_NOCL1B_QCH, QCH_CON_D_TZPC_NOCL1B_QCH_ENABLE, QCH_CON_D_TZPC_NOCL1B_QCH_CLOCK_REQ, QCH_CON_D_TZPC_NOCL1B_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_ACEL_MI_D_UFS_QCH, QCH_CON_LH_ACEL_MI_D_UFS_QCH_ENABLE, QCH_CON_LH_ACEL_MI_D_UFS_QCH_CLOCK_REQ, QCH_CON_LH_ACEL_MI_D_UFS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_ACEL_MI_ID_DIT_QCH, QCH_CON_LH_ACEL_MI_ID_DIT_QCH_ENABLE, QCH_CON_LH_ACEL_MI_ID_DIT_QCH_CLOCK_REQ, QCH_CON_LH_ACEL_MI_ID_DIT_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_ACEL_SI_ID_DIT_QCH, QCH_CON_LH_ACEL_SI_ID_DIT_QCH_ENABLE, QCH_CON_LH_ACEL_SI_ID_DIT_QCH_CLOCK_REQ, QCH_CON_LH_ACEL_SI_ID_DIT_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_SI_G_NOCL1B_QCH, QCH_CON_LH_AST_SI_G_NOCL1B_QCH_ENABLE, QCH_CON_LH_AST_SI_G_NOCL1B_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_G_NOCL1B_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_ID_TT_QCH, QCH_CON_LH_AXI_MI_ID_TT_QCH_ENABLE, QCH_CON_LH_AXI_MI_ID_TT_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_ID_TT_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_ID_TT_QCH, QCH_CON_LH_AXI_SI_ID_TT_QCH_ENABLE, QCH_CON_LH_AXI_SI_ID_TT_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_ID_TT_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(NOCL1B_CMU_NOCL1B_QCH, QCH_CON_NOCL1B_CMU_NOCL1B_QCH_ENABLE, QCH_CON_NOCL1B_CMU_NOCL1B_QCH_CLOCK_REQ, QCH_CON_NOCL1B_CMU_NOCL1B_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PDMA_QCH, QCH_CON_PDMA_QCH_ENABLE, QCH_CON_PDMA_QCH_CLOCK_REQ, QCH_CON_PDMA_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_DIT_QCH, QCH_CON_PPMU_DIT_QCH_ENABLE, QCH_CON_PPMU_DIT_QCH_CLOCK_REQ, QCH_CON_PPMU_DIT_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_D_TT_QCH, QCH_CON_PPMU_D_TT_QCH_ENABLE, QCH_CON_PPMU_D_TT_QCH_CLOCK_REQ, QCH_CON_PPMU_D_TT_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(QE_PDMA_QCH, QCH_CON_QE_PDMA_QCH_ENABLE, QCH_CON_QE_PDMA_QCH_CLOCK_REQ, QCH_CON_QE_PDMA_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(QE_SPDMA_QCH, QCH_CON_QE_SPDMA_QCH_ENABLE, QCH_CON_QE_SPDMA_QCH_CLOCK_REQ, QCH_CON_QE_SPDMA_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SIU_8X1_P0_NOCL1B_QCH, QCH_CON_SIU_8X1_P0_NOCL1B_QCH_ENABLE, QCH_CON_SIU_8X1_P0_NOCL1B_QCH_CLOCK_REQ, QCH_CON_SIU_8X1_P0_NOCL1B_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_ACEL_MI_D_HSI0_QCH, QCH_CON_SLH_ACEL_MI_D_HSI0_QCH_ENABLE, QCH_CON_SLH_ACEL_MI_D_HSI0_QCH_CLOCK_REQ, QCH_CON_SLH_ACEL_MI_D_HSI0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_MI_G_PPMU_HSI0_QCH, QCH_CON_SLH_AST_MI_G_PPMU_HSI0_QCH_ENABLE, QCH_CON_SLH_AST_MI_G_PPMU_HSI0_QCH_CLOCK_REQ, QCH_CON_SLH_AST_MI_G_PPMU_HSI0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_MI_G_PPMU_UFS_QCH, QCH_CON_SLH_AST_MI_G_PPMU_UFS_QCH_ENABLE, QCH_CON_SLH_AST_MI_G_PPMU_UFS_QCH_CLOCK_REQ, QCH_CON_SLH_AST_MI_G_PPMU_UFS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_MI_IG_DEBUG_MUX_NOCL1B_QCH, QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1B_QCH_ENABLE, QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1B_QCH_CLOCK_REQ, QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1B_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_MI_IG_PPMU_DIT_QCH, QCH_CON_SLH_AST_MI_IG_PPMU_DIT_QCH_ENABLE, QCH_CON_SLH_AST_MI_IG_PPMU_DIT_QCH_CLOCK_REQ, QCH_CON_SLH_AST_MI_IG_PPMU_DIT_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_MI_IG_PPMU_TREXP_QCH, QCH_CON_SLH_AST_MI_IG_PPMU_TREXP_QCH_ENABLE, QCH_CON_SLH_AST_MI_IG_PPMU_TREXP_QCH_CLOCK_REQ, QCH_CON_SLH_AST_MI_IG_PPMU_TREXP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_MI_IG_PPMU_XIU_D_TT_QCH, QCH_CON_SLH_AST_MI_IG_PPMU_XIU_D_TT_QCH_ENABLE, QCH_CON_SLH_AST_MI_IG_PPMU_XIU_D_TT_QCH_CLOCK_REQ, QCH_CON_SLH_AST_MI_IG_PPMU_XIU_D_TT_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_SI_G_PPMU_NOCL1B_QCH, QCH_CON_SLH_AST_SI_G_PPMU_NOCL1B_QCH_ENABLE, QCH_CON_SLH_AST_SI_G_PPMU_NOCL1B_QCH_CLOCK_REQ, QCH_CON_SLH_AST_SI_G_PPMU_NOCL1B_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_SI_IG_DEBUG_MUX_NOCL1B_QCH, QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1B_QCH_ENABLE, QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1B_QCH_CLOCK_REQ, QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1B_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_SI_IG_PPMU_DIT_QCH, QCH_CON_SLH_AST_SI_IG_PPMU_DIT_QCH_ENABLE, QCH_CON_SLH_AST_SI_IG_PPMU_DIT_QCH_CLOCK_REQ, QCH_CON_SLH_AST_SI_IG_PPMU_DIT_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_SI_IG_PPMU_TREXP_QCH, QCH_CON_SLH_AST_SI_IG_PPMU_TREXP_QCH_ENABLE, QCH_CON_SLH_AST_SI_IG_PPMU_TREXP_QCH_CLOCK_REQ, QCH_CON_SLH_AST_SI_IG_PPMU_TREXP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_SI_IG_PPMU_XIU_D_TT_QCH, QCH_CON_SLH_AST_SI_IG_PPMU_XIU_D_TT_QCH_ENABLE, QCH_CON_SLH_AST_SI_IG_PPMU_XIU_D_TT_QCH_CLOCK_REQ, QCH_CON_SLH_AST_SI_IG_PPMU_XIU_D_TT_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_P_HSI0_QCH, QCH_CON_SLH_AXI_SI_P_HSI0_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_HSI0_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_HSI0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_P_UFS_QCH, QCH_CON_SLH_AXI_SI_P_UFS_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_UFS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_UFS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SPDMA_QCH, QCH_CON_SPDMA_QCH_ENABLE, QCH_CON_SPDMA_QCH_CLOCK_REQ, QCH_CON_SPDMA_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_S2_DIT_QCH, QCH_CON_SYSMMU_S2_DIT_QCH_ENABLE, QCH_CON_SYSMMU_S2_DIT_QCH_CLOCK_REQ, QCH_CON_SYSMMU_S2_DIT_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_S2_TT_QCH, QCH_CON_SYSMMU_S2_TT_QCH_ENABLE, QCH_CON_SYSMMU_S2_TT_QCH_CLOCK_REQ, QCH_CON_SYSMMU_S2_TT_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_NOCL1B_QCH, QCH_CON_SYSREG_NOCL1B_QCH_ENABLE, QCH_CON_SYSREG_NOCL1B_QCH_CLOCK_REQ, QCH_CON_SYSREG_NOCL1B_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(TREX_D_NOCL1B_QCH, QCH_CON_TREX_D_NOCL1B_QCH_ENABLE, QCH_CON_TREX_D_NOCL1B_QCH_CLOCK_REQ, QCH_CON_TREX_D_NOCL1B_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(TREX_P_NOCL1B_QCH, QCH_CON_TREX_P_NOCL1B_QCH_ENABLE, QCH_CON_TREX_P_NOCL1B_QCH_CLOCK_REQ, QCH_CON_TREX_P_NOCL1B_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(VGEN_LITE_NOCL1B_QCH, QCH_CON_VGEN_LITE_NOCL1B_QCH_ENABLE, QCH_CON_VGEN_LITE_NOCL1B_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_NOCL1B_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(VGEN_PDMA_QCH, QCH_CON_VGEN_PDMA_QCH_ENABLE, QCH_CON_VGEN_PDMA_QCH_CLOCK_REQ, QCH_CON_VGEN_PDMA_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(VGEN_SPDMA_QCH, QCH_CON_VGEN_SPDMA_QCH_ENABLE, QCH_CON_VGEN_SPDMA_QCH_CLOCK_REQ, QCH_CON_VGEN_SPDMA_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(CMU_NOCL1C_CMUREF_QCH, DMYQCH_CON_CMU_NOCL1C_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_NOCL1C_CMUREF_QCH_CLOCK_REQ, DMYQCH_CON_CMU_NOCL1C_CMUREF_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(D_TZPC_NOCL1C_QCH, QCH_CON_D_TZPC_NOCL1C_QCH_ENABLE, QCH_CON_D_TZPC_NOCL1C_QCH_CLOCK_REQ, QCH_CON_D_TZPC_NOCL1C_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_SI_G_NOCL1C_QCH, QCH_CON_LH_AST_SI_G_NOCL1C_QCH_ENABLE, QCH_CON_LH_AST_SI_G_NOCL1C_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_G_NOCL1C_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_D0_BRP_QCH, QCH_CON_LH_AXI_MI_D0_BRP_QCH_ENABLE, QCH_CON_LH_AXI_MI_D0_BRP_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D0_BRP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_D0_CSIS_QCH, QCH_CON_LH_AXI_MI_D0_CSIS_QCH_ENABLE, QCH_CON_LH_AXI_MI_D0_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D0_CSIS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_D0_YUVP_QCH, QCH_CON_LH_AXI_MI_D0_YUVP_QCH_ENABLE, QCH_CON_LH_AXI_MI_D0_YUVP_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D0_YUVP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_D1_BRP_QCH, QCH_CON_LH_AXI_MI_D1_BRP_QCH_ENABLE, QCH_CON_LH_AXI_MI_D1_BRP_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D1_BRP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_D1_CSIS_QCH, QCH_CON_LH_AXI_MI_D1_CSIS_QCH_ENABLE, QCH_CON_LH_AXI_MI_D1_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D1_CSIS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_D1_MCSC_QCH, QCH_CON_LH_AXI_MI_D1_MCSC_QCH_ENABLE, QCH_CON_LH_AXI_MI_D1_MCSC_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D1_MCSC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_D2_BRP_QCH, QCH_CON_LH_AXI_MI_D2_BRP_QCH_ENABLE, QCH_CON_LH_AXI_MI_D2_BRP_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D2_BRP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_D2_CSIS_QCH, QCH_CON_LH_AXI_MI_D2_CSIS_QCH_ENABLE, QCH_CON_LH_AXI_MI_D2_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D2_CSIS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_D2_MCSC_QCH, QCH_CON_LH_AXI_MI_D2_MCSC_QCH_ENABLE, QCH_CON_LH_AXI_MI_D2_MCSC_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D2_MCSC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_D3_MCSC_QCH, QCH_CON_LH_AXI_MI_D3_MCSC_QCH_ENABLE, QCH_CON_LH_AXI_MI_D3_MCSC_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D3_MCSC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_D4_MCSC_QCH, QCH_CON_LH_AXI_MI_D4_MCSC_QCH_ENABLE, QCH_CON_LH_AXI_MI_D4_MCSC_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D4_MCSC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_D_CSTAT_QCH, QCH_CON_LH_AXI_MI_D_CSTAT_QCH_ENABLE, QCH_CON_LH_AXI_MI_D_CSTAT_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D_CSTAT_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(NOCL1C_CMU_NOCL1C_QCH, QCH_CON_NOCL1C_CMU_NOCL1C_QCH_ENABLE, QCH_CON_NOCL1C_CMU_NOCL1C_QCH_CLOCK_REQ, QCH_CON_NOCL1C_CMU_NOCL1C_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SIU_8X1_P0_NOCL1C_QCH, QCH_CON_SIU_8X1_P0_NOCL1C_QCH_ENABLE, QCH_CON_SIU_8X1_P0_NOCL1C_QCH_CLOCK_REQ, QCH_CON_SIU_8X1_P0_NOCL1C_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_MI_G_PPMU_BRP_QCH, QCH_CON_SLH_AST_MI_G_PPMU_BRP_QCH_ENABLE, QCH_CON_SLH_AST_MI_G_PPMU_BRP_QCH_CLOCK_REQ, QCH_CON_SLH_AST_MI_G_PPMU_BRP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_MI_G_PPMU_CSIS_QCH, QCH_CON_SLH_AST_MI_G_PPMU_CSIS_QCH_ENABLE, QCH_CON_SLH_AST_MI_G_PPMU_CSIS_QCH_CLOCK_REQ, QCH_CON_SLH_AST_MI_G_PPMU_CSIS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_MI_G_PPMU_CSTAT_QCH, QCH_CON_SLH_AST_MI_G_PPMU_CSTAT_QCH_ENABLE, QCH_CON_SLH_AST_MI_G_PPMU_CSTAT_QCH_CLOCK_REQ, QCH_CON_SLH_AST_MI_G_PPMU_CSTAT_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_MI_G_PPMU_MCSC_QCH, QCH_CON_SLH_AST_MI_G_PPMU_MCSC_QCH_ENABLE, QCH_CON_SLH_AST_MI_G_PPMU_MCSC_QCH_CLOCK_REQ, QCH_CON_SLH_AST_MI_G_PPMU_MCSC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_MI_G_PPMU_YUVP_QCH, QCH_CON_SLH_AST_MI_G_PPMU_YUVP_QCH_ENABLE, QCH_CON_SLH_AST_MI_G_PPMU_YUVP_QCH_CLOCK_REQ, QCH_CON_SLH_AST_MI_G_PPMU_YUVP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_MI_IG_DEBUG_MUX_NOCL1C_QCH, QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1C_QCH_ENABLE, QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1C_QCH_CLOCK_REQ, QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1C_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_MI_IG_PPMU_NOCL1C_QCH, QCH_CON_SLH_AST_MI_IG_PPMU_NOCL1C_QCH_ENABLE, QCH_CON_SLH_AST_MI_IG_PPMU_NOCL1C_QCH_CLOCK_REQ, QCH_CON_SLH_AST_MI_IG_PPMU_NOCL1C_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_SI_G_PPMU_NOCL1C_QCH, QCH_CON_SLH_AST_SI_G_PPMU_NOCL1C_QCH_ENABLE, QCH_CON_SLH_AST_SI_G_PPMU_NOCL1C_QCH_CLOCK_REQ, QCH_CON_SLH_AST_SI_G_PPMU_NOCL1C_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_SI_IG_DEBUG_MUX_NOCL1C_QCH, QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1C_QCH_ENABLE, QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1C_QCH_CLOCK_REQ, QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1C_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_SI_IG_PPMU_NOCL1C_QCH, QCH_CON_SLH_AST_SI_IG_PPMU_NOCL1C_QCH_ENABLE, QCH_CON_SLH_AST_SI_IG_PPMU_NOCL1C_QCH_CLOCK_REQ, QCH_CON_SLH_AST_SI_IG_PPMU_NOCL1C_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_D0_MCSC_QCH, QCH_CON_SLH_AXI_MI_D0_MCSC_QCH_ENABLE, QCH_CON_SLH_AXI_MI_D0_MCSC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_D0_MCSC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_D1_YUVP_QCH, QCH_CON_SLH_AXI_MI_D1_YUVP_QCH_ENABLE, QCH_CON_SLH_AXI_MI_D1_YUVP_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_D1_YUVP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_P_BRP_QCH, QCH_CON_SLH_AXI_SI_P_BRP_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_BRP_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_BRP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_P_CSIS_QCH, QCH_CON_SLH_AXI_SI_P_CSIS_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_CSIS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_CSIS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_P_CSTAT_QCH, QCH_CON_SLH_AXI_SI_P_CSTAT_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_CSTAT_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_CSTAT_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_P_MCSC_QCH, QCH_CON_SLH_AXI_SI_P_MCSC_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_MCSC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_MCSC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_P_YUVP_QCH, QCH_CON_SLH_AXI_SI_P_YUVP_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_YUVP_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_YUVP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_NOCL1C_QCH, QCH_CON_SYSREG_NOCL1C_QCH_ENABLE, QCH_CON_SYSREG_NOCL1C_QCH_CLOCK_REQ, QCH_CON_SYSREG_NOCL1C_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(TREX_D_NOCL1C_QCH, QCH_CON_TREX_D_NOCL1C_QCH_ENABLE, QCH_CON_TREX_D_NOCL1C_QCH_CLOCK_REQ, QCH_CON_TREX_D_NOCL1C_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(TREX_P_NOCL1C_QCH, QCH_CON_TREX_P_NOCL1C_QCH_ENABLE, QCH_CON_TREX_P_NOCL1C_QCH_CLOCK_REQ, QCH_CON_TREX_P_NOCL1C_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(D_TZPC_PERIC0_QCH, QCH_CON_D_TZPC_PERIC0_QCH_ENABLE, QCH_CON_D_TZPC_PERIC0_QCH_CLOCK_REQ, QCH_CON_D_TZPC_PERIC0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(GPIO_PERIC0_QCH, QCH_CON_GPIO_PERIC0_QCH_ENABLE, QCH_CON_GPIO_PERIC0_QCH_CLOCK_REQ, QCH_CON_GPIO_PERIC0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(I3C00_QCH_S, QCH_CON_I3C00_QCH_S_ENABLE, QCH_CON_I3C00_QCH_S_CLOCK_REQ, QCH_CON_I3C00_QCH_S_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(I3C00_QCH_P, QCH_CON_I3C00_QCH_P_ENABLE, QCH_CON_I3C00_QCH_P_CLOCK_REQ, QCH_CON_I3C00_QCH_P_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(I3C01_QCH_S, QCH_CON_I3C01_QCH_S_ENABLE, QCH_CON_I3C01_QCH_S_CLOCK_REQ, QCH_CON_I3C01_QCH_S_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(I3C01_QCH_P, QCH_CON_I3C01_QCH_P_ENABLE, QCH_CON_I3C01_QCH_P_CLOCK_REQ, QCH_CON_I3C01_QCH_P_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(I3C02_QCH_S, QCH_CON_I3C02_QCH_S_ENABLE, QCH_CON_I3C02_QCH_S_CLOCK_REQ, QCH_CON_I3C02_QCH_S_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(I3C02_QCH_P, QCH_CON_I3C02_QCH_P_ENABLE, QCH_CON_I3C02_QCH_P_CLOCK_REQ, QCH_CON_I3C02_QCH_P_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PERIC0_CMU_PERIC0_QCH, QCH_CON_PERIC0_CMU_PERIC0_QCH_ENABLE, QCH_CON_PERIC0_CMU_PERIC0_QCH_CLOCK_REQ, QCH_CON_PERIC0_CMU_PERIC0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_P_PERIC0_QCH, QCH_CON_SLH_AXI_MI_P_PERIC0_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_PERIC0_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_PERIC0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_PERIC0_QCH, QCH_CON_SYSREG_PERIC0_QCH_ENABLE, QCH_CON_SYSREG_PERIC0_QCH_CLOCK_REQ, QCH_CON_SYSREG_PERIC0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USI04_I2C_QCH, QCH_CON_USI04_I2C_QCH_ENABLE, QCH_CON_USI04_I2C_QCH_CLOCK_REQ, QCH_CON_USI04_I2C_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USI04_USI_QCH, QCH_CON_USI04_USI_QCH_ENABLE, QCH_CON_USI04_USI_QCH_CLOCK_REQ, QCH_CON_USI04_USI_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(BT_UART_QCH, QCH_CON_BT_UART_QCH_ENABLE, QCH_CON_BT_UART_QCH_CLOCK_REQ, QCH_CON_BT_UART_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(D_TZPC_PERIC1_QCH, QCH_CON_D_TZPC_PERIC1_QCH_ENABLE, QCH_CON_D_TZPC_PERIC1_QCH_CLOCK_REQ, QCH_CON_D_TZPC_PERIC1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(GPIO_PERIC1_QCH, QCH_CON_GPIO_PERIC1_QCH_ENABLE, QCH_CON_GPIO_PERIC1_QCH_CLOCK_REQ, QCH_CON_GPIO_PERIC1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PERIC1_CMU_PERIC1_QCH, QCH_CON_PERIC1_CMU_PERIC1_QCH_ENABLE, QCH_CON_PERIC1_CMU_PERIC1_QCH_CLOCK_REQ, QCH_CON_PERIC1_CMU_PERIC1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_P_PERIC1_QCH, QCH_CON_SLH_AXI_MI_P_PERIC1_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_PERIC1_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_PERIC1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SPI_MULTI_SLV_Q_CTRL_PERIC1_QCH, QCH_CON_SPI_MULTI_SLV_Q_CTRL_PERIC1_QCH_ENABLE, QCH_CON_SPI_MULTI_SLV_Q_CTRL_PERIC1_QCH_CLOCK_REQ, QCH_CON_SPI_MULTI_SLV_Q_CTRL_PERIC1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_PERIC1_QCH, QCH_CON_SYSREG_PERIC1_QCH_ENABLE, QCH_CON_SYSREG_PERIC1_QCH_CLOCK_REQ, QCH_CON_SYSREG_PERIC1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USI07_SPI_I2C_QCH, QCH_CON_USI07_SPI_I2C_QCH_ENABLE, QCH_CON_USI07_SPI_I2C_QCH_CLOCK_REQ, QCH_CON_USI07_SPI_I2C_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USI07_USI_QCH, QCH_CON_USI07_USI_QCH_ENABLE, QCH_CON_USI07_USI_QCH_CLOCK_REQ, QCH_CON_USI07_USI_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USI08_SPI_I2C_QCH, QCH_CON_USI08_SPI_I2C_QCH_ENABLE, QCH_CON_USI08_SPI_I2C_QCH_CLOCK_REQ, QCH_CON_USI08_SPI_I2C_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USI08_USI_QCH, QCH_CON_USI08_USI_QCH_ENABLE, QCH_CON_USI08_USI_QCH_CLOCK_REQ, QCH_CON_USI08_USI_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USI09_I2C_QCH, QCH_CON_USI09_I2C_QCH_ENABLE, QCH_CON_USI09_I2C_QCH_CLOCK_REQ, QCH_CON_USI09_I2C_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USI09_USI_QCH, QCH_CON_USI09_USI_QCH_ENABLE, QCH_CON_USI09_USI_QCH_CLOCK_REQ, QCH_CON_USI09_USI_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USI10_I2C_QCH, QCH_CON_USI10_I2C_QCH_ENABLE, QCH_CON_USI10_I2C_QCH_CLOCK_REQ, QCH_CON_USI10_I2C_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USI10_USI_QCH, QCH_CON_USI10_USI_QCH_ENABLE, QCH_CON_USI10_USI_QCH_CLOCK_REQ, QCH_CON_USI10_USI_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DBG_UART_QCH, QCH_CON_DBG_UART_QCH_ENABLE, QCH_CON_DBG_UART_QCH_CLOCK_REQ, QCH_CON_DBG_UART_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(D_TZPC_PERIC2_QCH, QCH_CON_D_TZPC_PERIC2_QCH_ENABLE, QCH_CON_D_TZPC_PERIC2_QCH_CLOCK_REQ, QCH_CON_D_TZPC_PERIC2_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(GPIO_PERIC2_QCH, QCH_CON_GPIO_PERIC2_QCH_ENABLE, QCH_CON_GPIO_PERIC2_QCH_CLOCK_REQ, QCH_CON_GPIO_PERIC2_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(I3C03_OIS_QCH_S, QCH_CON_I3C03_OIS_QCH_S_ENABLE, QCH_CON_I3C03_OIS_QCH_S_CLOCK_REQ, QCH_CON_I3C03_OIS_QCH_S_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(I3C03_OIS_QCH_P, QCH_CON_I3C03_OIS_QCH_P_ENABLE, QCH_CON_I3C03_OIS_QCH_P_CLOCK_REQ, QCH_CON_I3C03_OIS_QCH_P_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(I3C04_QCH_S, QCH_CON_I3C04_QCH_S_ENABLE, QCH_CON_I3C04_QCH_S_CLOCK_REQ, QCH_CON_I3C04_QCH_S_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(I3C04_QCH_P, QCH_CON_I3C04_QCH_P_ENABLE, QCH_CON_I3C04_QCH_P_CLOCK_REQ, QCH_CON_I3C04_QCH_P_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(I3C05_QCH_S, QCH_CON_I3C05_QCH_S_ENABLE, QCH_CON_I3C05_QCH_S_CLOCK_REQ, QCH_CON_I3C05_QCH_S_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(I3C05_QCH_P, QCH_CON_I3C05_QCH_P_ENABLE, QCH_CON_I3C05_QCH_P_CLOCK_REQ, QCH_CON_I3C05_QCH_P_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(I3C06_QCH_S, QCH_CON_I3C06_QCH_S_ENABLE, QCH_CON_I3C06_QCH_S_CLOCK_REQ, QCH_CON_I3C06_QCH_S_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(I3C06_QCH_P, QCH_CON_I3C06_QCH_P_ENABLE, QCH_CON_I3C06_QCH_P_CLOCK_REQ, QCH_CON_I3C06_QCH_P_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(I3C07_QCH_S, QCH_CON_I3C07_QCH_S_ENABLE, QCH_CON_I3C07_QCH_S_CLOCK_REQ, QCH_CON_I3C07_QCH_S_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(I3C07_QCH_P, QCH_CON_I3C07_QCH_P_ENABLE, QCH_CON_I3C07_QCH_P_CLOCK_REQ, QCH_CON_I3C07_QCH_P_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(I3C08_QCH_S, QCH_CON_I3C08_QCH_S_ENABLE, QCH_CON_I3C08_QCH_S_CLOCK_REQ, QCH_CON_I3C08_QCH_S_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(I3C08_QCH_P, QCH_CON_I3C08_QCH_P_ENABLE, QCH_CON_I3C08_QCH_P_CLOCK_REQ, QCH_CON_I3C08_QCH_P_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(I3C09_QCH_S, QCH_CON_I3C09_QCH_S_ENABLE, QCH_CON_I3C09_QCH_S_CLOCK_REQ, QCH_CON_I3C09_QCH_S_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(I3C09_QCH_P, QCH_CON_I3C09_QCH_P_ENABLE, QCH_CON_I3C09_QCH_P_CLOCK_REQ, QCH_CON_I3C09_QCH_P_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(I3C10_QCH_S, QCH_CON_I3C10_QCH_S_ENABLE, QCH_CON_I3C10_QCH_S_CLOCK_REQ, QCH_CON_I3C10_QCH_S_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(I3C10_QCH_P, QCH_CON_I3C10_QCH_P_ENABLE, QCH_CON_I3C10_QCH_P_CLOCK_REQ, QCH_CON_I3C10_QCH_P_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(I3C11_QCH_S, QCH_CON_I3C11_QCH_S_ENABLE, QCH_CON_I3C11_QCH_S_CLOCK_REQ, QCH_CON_I3C11_QCH_S_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(I3C11_QCH_P, QCH_CON_I3C11_QCH_P_ENABLE, QCH_CON_I3C11_QCH_P_CLOCK_REQ, QCH_CON_I3C11_QCH_P_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PERIC2_CMU_PERIC2_QCH, QCH_CON_PERIC2_CMU_PERIC2_QCH_ENABLE, QCH_CON_PERIC2_CMU_PERIC2_QCH_CLOCK_REQ, QCH_CON_PERIC2_CMU_PERIC2_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PWM_QCH, QCH_CON_PWM_QCH_ENABLE, QCH_CON_PWM_QCH_CLOCK_REQ, QCH_CON_PWM_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_LP_CSISPERIC2_QCH, QCH_CON_SLH_AXI_MI_LP_CSISPERIC2_QCH_ENABLE, QCH_CON_SLH_AXI_MI_LP_CSISPERIC2_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_LP_CSISPERIC2_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_P_PERIC2_QCH, QCH_CON_SLH_AXI_MI_P_PERIC2_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_PERIC2_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_PERIC2_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SPI_MULTI_SLV_Q_CTRL_PERIC2_QCH, QCH_CON_SPI_MULTI_SLV_Q_CTRL_PERIC2_QCH_ENABLE, QCH_CON_SPI_MULTI_SLV_Q_CTRL_PERIC2_QCH_CLOCK_REQ, QCH_CON_SPI_MULTI_SLV_Q_CTRL_PERIC2_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_PERIC2_QCH, QCH_CON_SYSREG_PERIC2_QCH_ENABLE, QCH_CON_SYSREG_PERIC2_QCH_CLOCK_REQ, QCH_CON_SYSREG_PERIC2_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USI00_SPI_I2C_QCH, QCH_CON_USI00_SPI_I2C_QCH_ENABLE, QCH_CON_USI00_SPI_I2C_QCH_CLOCK_REQ, QCH_CON_USI00_SPI_I2C_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USI00_USI_QCH, QCH_CON_USI00_USI_QCH_ENABLE, QCH_CON_USI00_USI_QCH_CLOCK_REQ, QCH_CON_USI00_USI_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USI01_SPI_I2C_QCH, QCH_CON_USI01_SPI_I2C_QCH_ENABLE, QCH_CON_USI01_SPI_I2C_QCH_CLOCK_REQ, QCH_CON_USI01_SPI_I2C_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USI01_USI_QCH, QCH_CON_USI01_USI_QCH_ENABLE, QCH_CON_USI01_USI_QCH_CLOCK_REQ, QCH_CON_USI01_USI_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USI02_I2C_QCH, QCH_CON_USI02_I2C_QCH_ENABLE, QCH_CON_USI02_I2C_QCH_CLOCK_REQ, QCH_CON_USI02_I2C_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USI02_USI_QCH, QCH_CON_USI02_USI_QCH_ENABLE, QCH_CON_USI02_USI_QCH_CLOCK_REQ, QCH_CON_USI02_USI_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USI03_I2C_QCH, QCH_CON_USI03_I2C_QCH_ENABLE, QCH_CON_USI03_I2C_QCH_CLOCK_REQ, QCH_CON_USI03_I2C_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USI03_USI_QCH, QCH_CON_USI03_USI_QCH_ENABLE, QCH_CON_USI03_USI_QCH_CLOCK_REQ, QCH_CON_USI03_USI_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USI05_I2C_QCH, QCH_CON_USI05_I2C_QCH_ENABLE, QCH_CON_USI05_I2C_QCH_CLOCK_REQ, QCH_CON_USI05_I2C_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USI05_USI_OIS_QCH, QCH_CON_USI05_USI_OIS_QCH_ENABLE, QCH_CON_USI05_USI_OIS_QCH_CLOCK_REQ, QCH_CON_USI05_USI_OIS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USI06_I2C_QCH, QCH_CON_USI06_I2C_QCH_ENABLE, QCH_CON_USI06_I2C_QCH_CLOCK_REQ, QCH_CON_USI06_I2C_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USI06_USI_OIS_QCH, QCH_CON_USI06_USI_OIS_QCH_ENABLE, QCH_CON_USI06_USI_OIS_QCH_CLOCK_REQ, QCH_CON_USI06_USI_OIS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USI11_I2C_QCH, QCH_CON_USI11_I2C_QCH_ENABLE, QCH_CON_USI11_I2C_QCH_CLOCK_REQ, QCH_CON_USI11_I2C_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(USI11_USI_QCH, QCH_CON_USI11_USI_QCH_ENABLE, QCH_CON_USI11_USI_QCH_CLOCK_REQ, QCH_CON_USI11_USI_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(BUSIF_DDD_PERIS_QCH, QCH_CON_BUSIF_DDD_PERIS_QCH_ENABLE, QCH_CON_BUSIF_DDD_PERIS_QCH_CLOCK_REQ, QCH_CON_BUSIF_DDD_PERIS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DFTMUX_PERIS_QCH, DMYQCH_CON_DFTMUX_PERIS_QCH_ENABLE, DMYQCH_CON_DFTMUX_PERIS_QCH_CLOCK_REQ, DMYQCH_CON_DFTMUX_PERIS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(D_TZPC_PERIS_QCH, QCH_CON_D_TZPC_PERIS_QCH_ENABLE, QCH_CON_D_TZPC_PERIS_QCH_CLOCK_REQ, QCH_CON_D_TZPC_PERIS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(GIC_QCH, QCH_CON_GIC_QCH_ENABLE, QCH_CON_GIC_QCH_CLOCK_REQ, QCH_CON_GIC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_MI_LD_ICC_CPUGIC_CLUSTER0_QCH, QCH_CON_LH_AST_MI_LD_ICC_CPUGIC_CLUSTER0_QCH_ENABLE, QCH_CON_LH_AST_MI_LD_ICC_CPUGIC_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_LD_ICC_CPUGIC_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_SI_LD_IRI_GICCPU_CLUSTER0_QCH, QCH_CON_LH_AST_SI_LD_IRI_GICCPU_CLUSTER0_QCH_ENABLE, QCH_CON_LH_AST_SI_LD_IRI_GICCPU_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_LD_IRI_GICCPU_CLUSTER0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(MCT_QCH, QCH_CON_MCT_QCH_ENABLE, QCH_CON_MCT_QCH_CLOCK_REQ, QCH_CON_MCT_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(OTP_CON_BIRA_QCH, QCH_CON_OTP_CON_BIRA_QCH_ENABLE, QCH_CON_OTP_CON_BIRA_QCH_CLOCK_REQ, QCH_CON_OTP_CON_BIRA_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(OTP_CON_TOP_QCH, QCH_CON_OTP_CON_TOP_QCH_ENABLE, QCH_CON_OTP_CON_TOP_QCH_CLOCK_REQ, QCH_CON_OTP_CON_TOP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PERIS_CMU_PERIS_QCH, QCH_CON_PERIS_CMU_PERIS_QCH_ENABLE, QCH_CON_PERIS_CMU_PERIS_QCH_CLOCK_REQ, QCH_CON_PERIS_CMU_PERIS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_P_PERIS_QCH, QCH_CON_SLH_AXI_MI_P_PERIS_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_PERIS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_PERIS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_P_PERISGIC_QCH, QCH_CON_SLH_AXI_MI_P_PERISGIC_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_PERISGIC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_PERISGIC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_PERIS_QCH, QCH_CON_SYSREG_PERIS_QCH_ENABLE, QCH_CON_SYSREG_PERIS_QCH_CLOCK_REQ, QCH_CON_SYSREG_PERIS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(TMU_SUB_QCH, QCH_CON_TMU_SUB_QCH_ENABLE, QCH_CON_TMU_SUB_QCH_CLOCK_REQ, QCH_CON_TMU_SUB_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(TMU_TOP_QCH, QCH_CON_TMU_TOP_QCH_ENABLE, QCH_CON_TMU_TOP_QCH_CLOCK_REQ, QCH_CON_TMU_TOP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(WDT0_QCH, QCH_CON_WDT0_QCH_ENABLE, QCH_CON_WDT0_QCH_CLOCK_REQ, QCH_CON_WDT0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(WDT1_QCH, QCH_CON_WDT1_QCH_ENABLE, QCH_CON_WDT1_QCH_CLOCK_REQ, QCH_CON_WDT1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(BIS_S2D_QCH, DMYQCH_CON_BIS_S2D_QCH_ENABLE, DMYQCH_CON_BIS_S2D_QCH_CLOCK_REQ, DMYQCH_CON_BIS_S2D_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(S2D_CMU_S2D_QCH, QCH_CON_S2D_CMU_S2D_QCH_ENABLE, QCH_CON_S2D_CMU_S2D_QCH_CLOCK_REQ, QCH_CON_S2D_CMU_S2D_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_G_SCAN2DRAM_QCH, QCH_CON_SLH_AXI_MI_G_SCAN2DRAM_QCH_ENABLE, QCH_CON_SLH_AXI_MI_G_SCAN2DRAM_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_G_SCAN2DRAM_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(D_TZPC_SDMA_QCH, QCH_CON_D_TZPC_SDMA_QCH_ENABLE, QCH_CON_D_TZPC_SDMA_QCH_CLOCK_REQ, QCH_CON_D_TZPC_SDMA_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(IP_SDMA_QCH, QCH_CON_IP_SDMA_QCH_ENABLE, QCH_CON_IP_SDMA_QCH_CLOCK_REQ, QCH_CON_IP_SDMA_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_SI_LD_STRM_SDMADSP0_QCH, QCH_CON_LH_AST_SI_LD_STRM_SDMADSP0_QCH_ENABLE, QCH_CON_LH_AST_SI_LD_STRM_SDMADSP0_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_LD_STRM_SDMADSP0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_LP_DNCSDMA_QCH, QCH_CON_LH_AXI_MI_LP_DNCSDMA_QCH_ENABLE, QCH_CON_LH_AXI_MI_LP_DNCSDMA_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LP_DNCSDMA_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_LD_SDMADNC_DATA0_QCH, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA0_QCH_ENABLE, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_LD_SDMADNC_DATA1_QCH, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA1_QCH_ENABLE, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA1_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_LD_SDMADNC_DATA2_QCH, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA2_QCH_ENABLE, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA2_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA2_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_LD_SDMADNC_DATA3_QCH, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA3_QCH_ENABLE, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA3_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA3_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_LD_SDMADNC_DATA4_QCH, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA4_QCH_ENABLE, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA4_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA4_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_LD_SDMADNC_DATA5_QCH, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA5_QCH_ENABLE, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA5_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA5_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_LD_SDMADNC_DATA6_QCH, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA6_QCH_ENABLE, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA6_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA6_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_LD_SDMADNC_DATA7_QCH, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA7_QCH_ENABLE, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA7_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA7_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_LD_SDMADNC_MMU0_QCH, QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU0_QCH_ENABLE, QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_LD_SDMADNC_MMU1_QCH, QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU1_QCH_ENABLE, QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU1_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_LD_SDMADNC_MMU2_QCH, QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU2_QCH_ENABLE, QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU2_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU2_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_LD_SDMADNC_MMU3_QCH, QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU3_QCH_ENABLE, QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU3_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU3_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SDMA_CMU_SDMA_QCH, QCH_CON_SDMA_CMU_SDMA_QCH_ENABLE, QCH_CON_SDMA_CMU_SDMA_QCH_CLOCK_REQ, QCH_CON_SDMA_CMU_SDMA_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_LP_SDMA_QCH, QCH_CON_SLH_AXI_MI_LP_SDMA_QCH_ENABLE, QCH_CON_SLH_AXI_MI_LP_SDMA_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_LP_SDMA_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_SDMA_QCH, QCH_CON_SYSREG_SDMA_QCH_ENABLE, QCH_CON_SYSREG_SDMA_QCH_CLOCK_REQ, QCH_CON_SYSREG_SDMA_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(BAAW_SSS_QCH, QCH_CON_BAAW_SSS_QCH_ENABLE, QCH_CON_BAAW_SSS_QCH_CLOCK_REQ, QCH_CON_BAAW_SSS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(D_TZPC_SSP_QCH, QCH_CON_D_TZPC_SSP_QCH_ENABLE, QCH_CON_D_TZPC_SSP_QCH_CLOCK_REQ, QCH_CON_D_TZPC_SSP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(HW_APBSEMA_MEC_QCH, QCH_CON_HW_APBSEMA_MEC_QCH_ENABLE, QCH_CON_HW_APBSEMA_MEC_QCH_CLOCK_REQ, QCH_CON_HW_APBSEMA_MEC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_L_STRONG_QCH, QCH_CON_LH_AXI_MI_L_STRONG_QCH_ENABLE, QCH_CON_LH_AXI_MI_L_STRONG_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_L_STRONG_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_SSP_QCH, QCH_CON_PPMU_SSP_QCH_ENABLE, QCH_CON_PPMU_SSP_QCH_CLOCK_REQ, QCH_CON_PPMU_SSP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(QE_SSS_QCH, QCH_CON_QE_SSS_QCH_ENABLE, QCH_CON_QE_SSS_QCH_CLOCK_REQ, QCH_CON_QE_SSS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(QE_STRONG_QCH, QCH_CON_QE_STRONG_QCH_ENABLE, QCH_CON_QE_STRONG_QCH_CLOCK_REQ, QCH_CON_QE_STRONG_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_ACEL_SI_D_SSP_QCH, QCH_CON_SLH_ACEL_SI_D_SSP_QCH_ENABLE, QCH_CON_SLH_ACEL_SI_D_SSP_QCH_CLOCK_REQ, QCH_CON_SLH_ACEL_SI_D_SSP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_SI_G_PPMU_SSP_QCH, QCH_CON_SLH_AST_SI_G_PPMU_SSP_QCH_ENABLE, QCH_CON_SLH_AST_SI_G_PPMU_SSP_QCH_CLOCK_REQ, QCH_CON_SLH_AST_SI_G_PPMU_SSP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_P_SSP_QCH, QCH_CON_SLH_AXI_MI_P_SSP_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_SSP_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_SSP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SSP_CMU_SSP_QCH, QCH_CON_SSP_CMU_SSP_QCH_ENABLE, QCH_CON_SSP_CMU_SSP_QCH_CLOCK_REQ, QCH_CON_SSP_CMU_SSP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SSS_QCH, QCH_CON_SSS_QCH_ENABLE, QCH_CON_SSS_QCH_CLOCK_REQ, QCH_CON_SSS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_SSP_QCH, QCH_CON_SYSMMU_SSP_QCH_ENABLE, QCH_CON_SYSMMU_SSP_QCH_CLOCK_REQ, QCH_CON_SYSMMU_SSP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_SSP_QCH, QCH_CON_SYSREG_SSP_QCH_ENABLE, QCH_CON_SYSREG_SSP_QCH_CLOCK_REQ, QCH_CON_SYSREG_SSP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(VGEN_LITE_SSP_QCH, QCH_CON_VGEN_LITE_SSP_QCH_ENABLE, QCH_CON_VGEN_LITE_SSP_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_SSP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_CLK_STRONG_FREE_OSCCLK_QCH, QCH_CON_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_CLK_STRONG_FREE_OSCCLK_CPU_QCH, QCH_CON_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_CPU_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_CPU_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_CPU_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(STRONG_CMU_STRONG_QCH, QCH_CON_STRONG_CMU_STRONG_QCH_ENABLE, QCH_CON_STRONG_CMU_STRONG_QCH_CLOCK_REQ, QCH_CON_STRONG_CMU_STRONG_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(BAAW_D_UFDDNC_QCH, QCH_CON_BAAW_D_UFDDNC_QCH_ENABLE, QCH_CON_BAAW_D_UFDDNC_QCH_CLOCK_REQ, QCH_CON_BAAW_D_UFDDNC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(D_TZPC_UFD_QCH, QCH_CON_D_TZPC_UFD_QCH_ENABLE, QCH_CON_D_TZPC_UFD_QCH_CLOCK_REQ, QCH_CON_D_TZPC_UFD_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(I3C_UFD_QCH_PCLK, QCH_CON_I3C_UFD_QCH_PCLK_ENABLE, QCH_CON_I3C_UFD_QCH_PCLK_CLOCK_REQ, QCH_CON_I3C_UFD_QCH_PCLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(I3C_UFD_QCH_SCLK, QCH_CON_I3C_UFD_QCH_SCLK_ENABLE, QCH_CON_I3C_UFD_QCH_SCLK_CLOCK_REQ, QCH_CON_I3C_UFD_QCH_SCLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_SI_OTF_UFDDNC_QCH, QCH_CON_LH_AST_SI_OTF_UFDDNC_QCH_ENABLE, QCH_CON_LH_AST_SI_OTF_UFDDNC_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_OTF_UFDDNC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PDMA_UFD_QCH, QCH_CON_PDMA_UFD_QCH_ENABLE, QCH_CON_PDMA_UFD_QCH_CLOCK_REQ, QCH_CON_PDMA_UFD_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_D_UFD_QCH, QCH_CON_PPMU_D_UFD_QCH_ENABLE, QCH_CON_PPMU_D_UFD_QCH_CLOCK_REQ, QCH_CON_PPMU_D_UFD_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_CLK_UFD_NOC_UFD_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_UFD_NOC_UFD_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_UFD_NOC_UFD_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_UFD_NOC_UFD_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_SR_CLK_UFD_NOC_LH_AST_SI_OTF_UFDDNC_SW_RESET_QCH, QCH_CON_RSTNSYNC_SR_CLK_UFD_NOC_LH_AST_SI_OTF_UFDDNC_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_SR_CLK_UFD_NOC_LH_AST_SI_OTF_UFDDNC_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_SR_CLK_UFD_NOC_LH_AST_SI_OTF_UFDDNC_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(RSTNSYNC_SR_CLK_UFD_NOC_SLH_AST_MI_OTF_CSISUFD_SW_RESET_QCH, QCH_CON_RSTNSYNC_SR_CLK_UFD_NOC_SLH_AST_MI_OTF_CSISUFD_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_SR_CLK_UFD_NOC_SLH_AST_MI_OTF_CSISUFD_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_SR_CLK_UFD_NOC_SLH_AST_MI_OTF_CSISUFD_SW_RESET_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_MI_OTF_CSISUFD_QCH, QCH_CON_SLH_AST_MI_OTF_CSISUFD_QCH_ENABLE, QCH_CON_SLH_AST_MI_OTF_CSISUFD_QCH_CLOCK_REQ, QCH_CON_SLH_AST_MI_OTF_CSISUFD_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_SI_G_PPMU_UFD_QCH, QCH_CON_SLH_AST_SI_G_PPMU_UFD_QCH_ENABLE, QCH_CON_SLH_AST_SI_G_PPMU_UFD_QCH_CLOCK_REQ, QCH_CON_SLH_AST_SI_G_PPMU_UFD_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_LP_CMGPUFD_QCH, QCH_CON_SLH_AXI_MI_LP_CMGPUFD_QCH_ENABLE, QCH_CON_SLH_AXI_MI_LP_CMGPUFD_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_LP_CMGPUFD_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_P_UFD_QCH, QCH_CON_SLH_AXI_MI_P_UFD_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_UFD_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_UFD_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_D_UFD_QCH, QCH_CON_SLH_AXI_SI_D_UFD_QCH_ENABLE, QCH_CON_SLH_AXI_SI_D_UFD_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_D_UFD_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_LD_UFDDNC_QCH, QCH_CON_SLH_AXI_SI_LD_UFDDNC_QCH_ENABLE, QCH_CON_SLH_AXI_SI_LD_UFDDNC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_LD_UFDDNC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_LP_UFDCSIS_QCH, QCH_CON_SLH_AXI_SI_LP_UFDCSIS_QCH_ENABLE, QCH_CON_SLH_AXI_SI_LP_UFDCSIS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_LP_UFDCSIS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SRAM_MIU_UFD_QCH, QCH_CON_SRAM_MIU_UFD_QCH_ENABLE, QCH_CON_SRAM_MIU_UFD_QCH_CLOCK_REQ, QCH_CON_SRAM_MIU_UFD_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D_UFD_QCH_S1, QCH_CON_SYSMMU_D_UFD_QCH_S1_ENABLE, QCH_CON_SYSMMU_D_UFD_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D_UFD_QCH_S1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D_UFD_QCH_S2, QCH_CON_SYSMMU_D_UFD_QCH_S2_ENABLE, QCH_CON_SYSMMU_D_UFD_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D_UFD_QCH_S2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_UFD_QCH, QCH_CON_SYSREG_UFD_QCH_ENABLE, QCH_CON_SYSREG_UFD_QCH_CLOCK_REQ, QCH_CON_SYSREG_UFD_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_UFD_SECURE_QCH, QCH_CON_SYSREG_UFD_SECURE_QCH_ENABLE, QCH_CON_SYSREG_UFD_SECURE_QCH_CLOCK_REQ, QCH_CON_SYSREG_UFD_SECURE_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(UFD_CMU_UFD_QCH, QCH_CON_UFD_CMU_UFD_QCH_ENABLE, QCH_CON_UFD_CMU_UFD_QCH_CLOCK_REQ, QCH_CON_UFD_CMU_UFD_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(VGEN_LITE_D_UFD_QCH, QCH_CON_VGEN_LITE_D_UFD_QCH_ENABLE, QCH_CON_VGEN_LITE_D_UFD_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_D_UFD_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(UFD_QCH, QCH_CON_UFD_QCH_ENABLE, QCH_CON_UFD_QCH_CLOCK_REQ, QCH_CON_UFD_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(D_TZPC_UFS_QCH, QCH_CON_D_TZPC_UFS_QCH_ENABLE, QCH_CON_D_TZPC_UFS_QCH_CLOCK_REQ, QCH_CON_D_TZPC_UFS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(GPIO_HSI1UFS_QCH, QCH_CON_GPIO_HSI1UFS_QCH_ENABLE, QCH_CON_GPIO_HSI1UFS_QCH_CLOCK_REQ, QCH_CON_GPIO_HSI1UFS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(GPIO_UFS_QCH, QCH_CON_GPIO_UFS_QCH_ENABLE, QCH_CON_GPIO_UFS_QCH_CLOCK_REQ, QCH_CON_GPIO_UFS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_ACEL_SI_D_UFS_QCH, QCH_CON_LH_ACEL_SI_D_UFS_QCH_ENABLE, QCH_CON_LH_ACEL_SI_D_UFS_QCH_CLOCK_REQ, QCH_CON_LH_ACEL_SI_D_UFS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(MMC_CARD_QCH, QCH_CON_MMC_CARD_QCH_ENABLE, QCH_CON_MMC_CARD_QCH_CLOCK_REQ, QCH_CON_MMC_CARD_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_UFS_QCH, QCH_CON_PPMU_UFS_QCH_ENABLE, QCH_CON_PPMU_UFS_QCH_CLOCK_REQ, QCH_CON_PPMU_UFS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_SI_G_PPMU_UFS_QCH, QCH_CON_SLH_AST_SI_G_PPMU_UFS_QCH_ENABLE, QCH_CON_SLH_AST_SI_G_PPMU_UFS_QCH_CLOCK_REQ, QCH_CON_SLH_AST_SI_G_PPMU_UFS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_P_UFS_QCH, QCH_CON_SLH_AXI_MI_P_UFS_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_UFS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_UFS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SPC_UFS_QCH, QCH_CON_SPC_UFS_QCH_ENABLE, QCH_CON_SPC_UFS_QCH_CLOCK_REQ, QCH_CON_SPC_UFS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_UFS_QCH_S2, QCH_CON_SYSMMU_UFS_QCH_S2_ENABLE, QCH_CON_SYSMMU_UFS_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_UFS_QCH_S2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_UFS_QCH, QCH_CON_SYSREG_UFS_QCH_ENABLE, QCH_CON_SYSREG_UFS_QCH_CLOCK_REQ, QCH_CON_SYSREG_UFS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(UFS_CMU_UFS_QCH, QCH_CON_UFS_CMU_UFS_QCH_ENABLE, QCH_CON_UFS_CMU_UFS_QCH_CLOCK_REQ, QCH_CON_UFS_CMU_UFS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(UFS_EMBD_QCH_FMP, QCH_CON_UFS_EMBD_QCH_FMP_ENABLE, QCH_CON_UFS_EMBD_QCH_FMP_CLOCK_REQ, QCH_CON_UFS_EMBD_QCH_FMP_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(UFS_EMBD_QCH, QCH_CON_UFS_EMBD_QCH_ENABLE, QCH_CON_UFS_EMBD_QCH_CLOCK_REQ, QCH_CON_UFS_EMBD_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(VGEN_LITE_UFS_QCH, QCH_CON_VGEN_LITE_UFS_QCH_ENABLE, QCH_CON_VGEN_LITE_UFS_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_UFS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(ASYNCINTERRUPT_VTS_QCH_ASYNCINTERRUPT_VT, QCH_CON_ASYNCINTERRUPT_VTS_QCH_ASYNCINTERRUPT_VT_ENABLE, QCH_CON_ASYNCINTERRUPT_VTS_QCH_ASYNCINTERRUPT_VT_CLOCK_REQ, QCH_CON_ASYNCINTERRUPT_VTS_QCH_ASYNCINTERRUPT_VT_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(BAAW_VTS_QCH, QCH_CON_BAAW_VTS_QCH_ENABLE, QCH_CON_BAAW_VTS_QCH_CLOCK_REQ, QCH_CON_BAAW_VTS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DMIC_IF0_QCH_PCLK, QCH_CON_DMIC_IF0_QCH_PCLK_ENABLE, QCH_CON_DMIC_IF0_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_IF0_QCH_PCLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DMIC_IF0_QCH_DMIC, DMYQCH_CON_DMIC_IF0_QCH_DMIC_ENABLE, DMYQCH_CON_DMIC_IF0_QCH_DMIC_CLOCK_REQ, DMYQCH_CON_DMIC_IF0_QCH_DMIC_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DMIC_IF1_QCH_PCLK, QCH_CON_DMIC_IF1_QCH_PCLK_ENABLE, QCH_CON_DMIC_IF1_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_IF1_QCH_PCLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DMIC_IF1_QCH_DMIC, DMYQCH_CON_DMIC_IF1_QCH_DMIC_ENABLE, DMYQCH_CON_DMIC_IF1_QCH_DMIC_CLOCK_REQ, DMYQCH_CON_DMIC_IF1_QCH_DMIC_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DMIC_IF2_QCH_PCLK, QCH_CON_DMIC_IF2_QCH_PCLK_ENABLE, QCH_CON_DMIC_IF2_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_IF2_QCH_PCLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(DMIC_IF2_QCH_DMIC, DMYQCH_CON_DMIC_IF2_QCH_DMIC_ENABLE, DMYQCH_CON_DMIC_IF2_QCH_DMIC_CLOCK_REQ, DMYQCH_CON_DMIC_IF2_QCH_DMIC_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(GPIO_VTS_QCH, QCH_CON_GPIO_VTS_QCH_ENABLE, QCH_CON_GPIO_VTS_QCH_CLOCK_REQ, QCH_CON_GPIO_VTS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(INTMEM_CODE_QCH, QCH_CON_INTMEM_CODE_QCH_ENABLE, QCH_CON_INTMEM_CODE_QCH_CLOCK_REQ, QCH_CON_INTMEM_CODE_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(INTMEM_DATA0_QCH, QCH_CON_INTMEM_DATA0_QCH_ENABLE, QCH_CON_INTMEM_DATA0_QCH_CLOCK_REQ, QCH_CON_INTMEM_DATA0_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(INTMEM_DATA1_QCH, QCH_CON_INTMEM_DATA1_QCH_ENABLE, QCH_CON_INTMEM_DATA1_QCH_CLOCK_REQ, QCH_CON_INTMEM_DATA1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(INTMEM_PCM_QCH, QCH_CON_INTMEM_PCM_QCH_ENABLE, QCH_CON_INTMEM_PCM_QCH_CLOCK_REQ, QCH_CON_INTMEM_PCM_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_MI_IP_VC2VTS_QCH, QCH_CON_LH_AXI_MI_IP_VC2VTS_QCH_ENABLE, QCH_CON_LH_AXI_MI_IP_VC2VTS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_IP_VC2VTS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_ID_VTS2VC_QCH, QCH_CON_LH_AXI_SI_ID_VTS2VC_QCH_ENABLE, QCH_CON_LH_AXI_SI_ID_VTS2VC_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_ID_VTS2VC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(MAILBOX_ABOX_VTS_QCH, QCH_CON_MAILBOX_ABOX_VTS_QCH_ENABLE, QCH_CON_MAILBOX_ABOX_VTS_QCH_CLOCK_REQ, QCH_CON_MAILBOX_ABOX_VTS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(MAILBOX_AP_VTS_QCH, QCH_CON_MAILBOX_AP_VTS_QCH_ENABLE, QCH_CON_MAILBOX_AP_VTS_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP_VTS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(MAILBOX_DNC_VTS_QCH, QCH_CON_MAILBOX_DNC_VTS_QCH_ENABLE, QCH_CON_MAILBOX_DNC_VTS_QCH_CLOCK_REQ, QCH_CON_MAILBOX_DNC_VTS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SERIAL_LIF_VT_QCH_PCLK, QCH_CON_SERIAL_LIF_VT_QCH_PCLK_ENABLE, QCH_CON_SERIAL_LIF_VT_QCH_PCLK_CLOCK_REQ, QCH_CON_SERIAL_LIF_VT_QCH_PCLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SERIAL_LIF_VT_QCH_CCLK, QCH_CON_SERIAL_LIF_VT_QCH_CCLK_ENABLE, QCH_CON_SERIAL_LIF_VT_QCH_CCLK_CLOCK_REQ, QCH_CON_SERIAL_LIF_VT_QCH_CCLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SERIAL_LIF_VT_QCH_ACLK, QCH_CON_SERIAL_LIF_VT_QCH_ACLK_ENABLE, QCH_CON_SERIAL_LIF_VT_QCH_ACLK_CLOCK_REQ, QCH_CON_SERIAL_LIF_VT_QCH_ACLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SERIAL_LIF_VT_QCH_BCLK, QCH_CON_SERIAL_LIF_VT_QCH_BCLK_ENABLE, QCH_CON_SERIAL_LIF_VT_QCH_BCLK_CLOCK_REQ, QCH_CON_SERIAL_LIF_VT_QCH_BCLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SS_VTS_GLUE_QCH_DMIC_IF_PAD0, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0_ENABLE, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0_CLOCK_REQ, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SS_VTS_GLUE_QCH_DMIC_IF_PAD1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1_ENABLE, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1_CLOCK_REQ, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SS_VTS_GLUE_QCH_DMIC_IF_PAD2, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD2_ENABLE, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD2_CLOCK_REQ, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SS_VTS_GLUE_QCH_DMIC_AUD_DIV2_CLK, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_DIV2_CLK_ENABLE, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_DIV2_CLK_CLOCK_REQ, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_DIV2_CLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_VTS_QCH, QCH_CON_SYSREG_VTS_QCH_ENABLE, QCH_CON_SYSREG_VTS_QCH_CLOCK_REQ, QCH_CON_SYSREG_VTS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(TIMER_QCH, QCH_CON_TIMER_QCH_ENABLE, QCH_CON_TIMER_QCH_CLOCK_REQ, QCH_CON_TIMER_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(TIMER1_QCH, QCH_CON_TIMER1_QCH_ENABLE, QCH_CON_TIMER1_QCH_CLOCK_REQ, QCH_CON_TIMER1_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(TIMER2_QCH, QCH_CON_TIMER2_QCH_ENABLE, QCH_CON_TIMER2_QCH_CLOCK_REQ, QCH_CON_TIMER2_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(VTS_CMU_VTS_QCH, QCH_CON_VTS_CMU_VTS_QCH_ENABLE, QCH_CON_VTS_CMU_VTS_QCH_CLOCK_REQ, QCH_CON_VTS_CMU_VTS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(WDT_VTS_QCH, QCH_CON_WDT_VTS_QCH_ENABLE, QCH_CON_WDT_VTS_QCH_CLOCK_REQ, QCH_CON_WDT_VTS_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(YAMIN_MCU_VTS_QCH_CLKIN, QCH_CON_YAMIN_MCU_VTS_QCH_CLKIN_ENABLE, QCH_CON_YAMIN_MCU_VTS_QCH_CLKIN_CLOCK_REQ, QCH_CON_YAMIN_MCU_VTS_QCH_CLKIN_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(YAMIN_MCU_VTS_QCH_DBGCLK, QCH_CON_YAMIN_MCU_VTS_QCH_DBGCLK_ENABLE, QCH_CON_YAMIN_MCU_VTS_QCH_DBGCLK_CLOCK_REQ, QCH_CON_YAMIN_MCU_VTS_QCH_DBGCLK_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(BUSIF_DDD_YUVP_QCH, QCH_CON_BUSIF_DDD_YUVP_QCH_ENABLE, QCH_CON_BUSIF_DDD_YUVP_QCH_CLOCK_REQ, QCH_CON_BUSIF_DDD_YUVP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(D_TZPC_YUVP_QCH, QCH_CON_D_TZPC_YUVP_QCH_ENABLE, QCH_CON_D_TZPC_YUVP_QCH_CLOCK_REQ, QCH_CON_D_TZPC_YUVP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_MI_OTF_MCSCYUVP_QCH, QCH_CON_LH_AST_MI_OTF_MCSCYUVP_QCH_ENABLE, QCH_CON_LH_AST_MI_OTF_MCSCYUVP_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_OTF_MCSCYUVP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_SI_OTF0_YUVPMCSC_QCH, QCH_CON_LH_AST_SI_OTF0_YUVPMCSC_QCH_ENABLE, QCH_CON_LH_AST_SI_OTF0_YUVPMCSC_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_OTF0_YUVPMCSC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AST_SI_OTF1_YUVPMCSC_QCH, QCH_CON_LH_AST_SI_OTF1_YUVPMCSC_QCH_ENABLE, QCH_CON_LH_AST_SI_OTF1_YUVPMCSC_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_OTF1_YUVPMCSC_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(LH_AXI_SI_D0_YUVP_QCH, QCH_CON_LH_AXI_SI_D0_YUVP_QCH_ENABLE, QCH_CON_LH_AXI_SI_D0_YUVP_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D0_YUVP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_D0_YUVP_QCH, QCH_CON_PPMU_D0_YUVP_QCH_ENABLE, QCH_CON_PPMU_D0_YUVP_QCH_CLOCK_REQ, QCH_CON_PPMU_D0_YUVP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(PPMU_D1_YUVP_QCH, QCH_CON_PPMU_D1_YUVP_QCH_ENABLE, QCH_CON_PPMU_D1_YUVP_QCH_CLOCK_REQ, QCH_CON_PPMU_D1_YUVP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SIU_G_PPMU_YUVP_QCH, QCH_CON_SIU_G_PPMU_YUVP_QCH_ENABLE, QCH_CON_SIU_G_PPMU_YUVP_QCH_CLOCK_REQ, QCH_CON_SIU_G_PPMU_YUVP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AST_SI_G_PPMU_YUVP_QCH, QCH_CON_SLH_AST_SI_G_PPMU_YUVP_QCH_ENABLE, QCH_CON_SLH_AST_SI_G_PPMU_YUVP_QCH_CLOCK_REQ, QCH_CON_SLH_AST_SI_G_PPMU_YUVP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_MI_P_YUVP_QCH, QCH_CON_SLH_AXI_MI_P_YUVP_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_YUVP_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_YUVP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SLH_AXI_SI_D1_YUVP_QCH, QCH_CON_SLH_AXI_SI_D1_YUVP_QCH_ENABLE, QCH_CON_SLH_AXI_SI_D1_YUVP_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_D1_YUVP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D0_YUVP_QCH_S1, QCH_CON_SYSMMU_D0_YUVP_QCH_S1_ENABLE, QCH_CON_SYSMMU_D0_YUVP_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D0_YUVP_QCH_S1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D0_YUVP_QCH_S2, QCH_CON_SYSMMU_D0_YUVP_QCH_S2_ENABLE, QCH_CON_SYSMMU_D0_YUVP_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D0_YUVP_QCH_S2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D1_YUVP_QCH_S1, QCH_CON_SYSMMU_D1_YUVP_QCH_S1_ENABLE, QCH_CON_SYSMMU_D1_YUVP_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D1_YUVP_QCH_S1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSMMU_D1_YUVP_QCH_S2, QCH_CON_SYSMMU_D1_YUVP_QCH_S2_ENABLE, QCH_CON_SYSMMU_D1_YUVP_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D1_YUVP_QCH_S2_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(SYSREG_YUVP_QCH, QCH_CON_SYSREG_YUVP_QCH_ENABLE, QCH_CON_SYSREG_YUVP_QCH_CLOCK_REQ, QCH_CON_SYSREG_YUVP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(VGEN_LITE_D0_YUVP_QCH, QCH_CON_VGEN_LITE_D0_YUVP_QCH_ENABLE, QCH_CON_VGEN_LITE_D0_YUVP_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_D0_YUVP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(VGEN_LITE_D1_YUVP_QCH, QCH_CON_VGEN_LITE_D1_YUVP_QCH_ENABLE, QCH_CON_VGEN_LITE_D1_YUVP_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_D1_YUVP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(YUVP_QCH, QCH_CON_YUVP_QCH_ENABLE, QCH_CON_YUVP_QCH_CLOCK_REQ, QCH_CON_YUVP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(YUVP_QCH_VOTF0, QCH_CON_YUVP_QCH_VOTF0_ENABLE, QCH_CON_YUVP_QCH_VOTF0_CLOCK_REQ, QCH_CON_YUVP_QCH_VOTF0_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(YUVP_QCH_VOTF1, QCH_CON_YUVP_QCH_VOTF1_ENABLE, QCH_CON_YUVP_QCH_VOTF1_CLOCK_REQ, QCH_CON_YUVP_QCH_VOTF1_IGNORE_FORCE_PM_EN),
|
||
|
|
CLK_QCH(YUVP_CMU_YUVP_QCH, QCH_CON_YUVP_CMU_YUVP_QCH_ENABLE, QCH_CON_YUVP_CMU_YUVP_QCH_CLOCK_REQ, QCH_CON_YUVP_CMU_YUVP_QCH_IGNORE_FORCE_PM_EN),
|
||
|
|
};
|
||
|
|
|
||
|
|
unsigned int cmucal_option_size = 50;
|
||
|
|
struct cmucal_option cmucal_option_list[] = {
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_ALIVE, ALIVE_CMU_ALIVE_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, ALIVE_CMU_ALIVE_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_ALLCSIS, ALLCSIS_CMU_ALLCSIS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, ALLCSIS_CMU_ALLCSIS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_AUD, AUD_CMU_AUD_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, AUD_CMU_AUD_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_BRP, BRP_CMU_BRP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, BRP_CMU_BRP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_CHUB, CHUB_CMU_CHUB_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CHUB_CMU_CHUB_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_CHUBVTS, CHUBVTS_CMU_CHUBVTS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CHUBVTS_CMU_CHUBVTS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_CMGP, CMGP_CMU_CMGP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CMGP_CMU_CMGP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_TOP, CMU_CMU_TOP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CMU_CMU_TOP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_CPUCL0, CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_CPUCL0_GLB, CPUCL0_GLB_CMU_CPUCL0_GLB_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CPUCL0_GLB_CMU_CPUCL0_GLB_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_CPUCL1, CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_CPUCL2, CPUCL2_CMU_CPUCL2_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CPUCL2_CMU_CPUCL2_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_CSIS, CSIS_CMU_CSIS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CSIS_CMU_CSIS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_CSTAT, CSTAT_CMU_CSTAT_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CSTAT_CMU_CSTAT_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_DBGCORE, DBGCORE_CMU_DBGCORE_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, DBGCORE_CMU_DBGCORE_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_DNC, DNC_CMU_DNC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, DNC_CMU_DNC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_DPUB, DPUB_CMU_DPUB_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, DPUB_CMU_DPUB_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_DPUF, DPUF_CMU_DPUF_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, DPUF_CMU_DPUF_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_DPUF1, DPUF1_CMU_DPUF1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, DPUF1_CMU_DPUF1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_DRCP, DRCP_CMU_DRCP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, DRCP_CMU_DRCP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_DSP, DSP_CMU_DSP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, DSP_CMU_DSP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_DSU, DSU_CMU_DSU_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, DSU_CMU_DSU_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_G3D, G3D_CMU_G3D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, G3D_CMU_G3D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_G3DCORE, G3DCORE_CMU_G3DCORE_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, G3DCORE_CMU_G3DCORE_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_GNPU, GNPU_CMU_GNPU_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, GNPU_CMU_GNPU_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_GNSS, GNSS_CMU_GNSS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, GNSS_CMU_GNSS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_HSI0, HSI0_CMU_HSI0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, HSI0_CMU_HSI0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_HSI1, HSI1_CMU_HSI1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, HSI1_CMU_HSI1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_LME, LME_CMU_LME_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, LME_CMU_LME_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_M2M, M2M_CMU_M2M_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, M2M_CMU_M2M_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_MCSC, MCSC_CMU_MCSC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, MCSC_CMU_MCSC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_MFC0, MFC0_CMU_MFC0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, MFC0_CMU_MFC0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_MFC1, MFC1_CMU_MFC1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, MFC1_CMU_MFC1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_MIF, MIF_CMU_MIF_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, MIF_CMU_MIF_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_NOCL0, NOCL0_CMU_NOCL0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, NOCL0_CMU_NOCL0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_NOCL1A, NOCL1A_CMU_NOCL1A_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, NOCL1A_CMU_NOCL1A_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_NOCL1B, NOCL1B_CMU_NOCL1B_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, NOCL1B_CMU_NOCL1B_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_NOCL1C, NOCL1C_CMU_NOCL1C_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, NOCL1C_CMU_NOCL1C_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_PERIC0, PERIC0_CMU_PERIC0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, PERIC0_CMU_PERIC0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_PERIC1, PERIC1_CMU_PERIC1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, PERIC1_CMU_PERIC1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_PERIC2, PERIC2_CMU_PERIC2_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, PERIC2_CMU_PERIC2_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_PERIS, PERIS_CMU_PERIS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, PERIS_CMU_PERIS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_S2D, S2D_CMU_S2D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, S2D_CMU_S2D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_SDMA, SDMA_CMU_SDMA_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, SDMA_CMU_SDMA_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_SSP, SSP_CMU_SSP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, SSP_CMU_SSP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_STRONG, STRONG_CMU_STRONG_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, STRONG_CMU_STRONG_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_UFD, UFD_CMU_UFD_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, UFD_CMU_UFD_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_UFS, UFS_CMU_UFS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, UFS_CMU_UFS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_VTS, VTS_CMU_VTS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, VTS_CMU_VTS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
CLK_OPTION(CTRL_OPTION_CMU_YUVP, YUVP_CMU_YUVP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, YUVP_CMU_YUVP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING),
|
||
|
|
};
|
||
|
|
|