146 lines
6 KiB
C
146 lines
6 KiB
C
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/*
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* Copyright (C) 2018-2021 Advanced Micro Devices, Inc. All rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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#include "soc15.h"
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#include "gc/gc_10_4_0_offset.h"
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#include "gc/gc_10_4_0_sh_mask.h"
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#include "gc/gc_10_4_0_default.h"
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#include "soc15_common.h"
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#include "soc15_hw_ip.h"
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#include "emu_mobile0_asic_init.h"
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#include "emu_mobile1_asic_init.h"
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#define DRM_SGPU_PROGRAM_RSMU
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static void emu_mobile0_asic_init(struct amdgpu_device *adev)
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{
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int i = 0;
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for (i = 0; i < ARRAY_SIZE(emu_mobile0_setting_cl78945); i++) {
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unsigned int val = emu_mobile0_setting_cl78945[i].val;
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unsigned int reg = emu_mobile0_setting_cl78945[i].reg;
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WREG32(reg, val);
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DRM_DEBUG("M0, try to set reg:0x%x to value:0x%x\n", reg,
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val);
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}
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}
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static void emu_mobile1_asic_init(struct amdgpu_device *adev)
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{
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int i = 0;
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for (i = 0; i < ARRAY_SIZE(emu_mobile1_setting_cl87835); i++) {
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uint32_t reg = emu_mobile1_setting_cl87835[i].reg;
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uint32_t val = emu_mobile1_setting_cl87835[i].val;
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/* The original reg address is byte alignment */
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WREG32(reg / 4, val);
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DRM_INFO("M1 init 0x%x(dword:0x%x)=0x%x!\n", reg, reg / 4, val);
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}
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}
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int emu_soc_asic_init(struct amdgpu_device *adev)
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{
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if (sgpu_no_hw_access != 0)
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return 0;
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else if (AMDGPU_IS_MGFX0_EVT1(adev->grbm_chip_rev))
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emu_mobile0_asic_init(adev);
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else if (AMDGPU_IS_MGFX1(adev->grbm_chip_rev))
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emu_mobile1_asic_init(adev);
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#if 0
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/* Change register's default value:
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* SQ_CONFIG: NEW_TRANS_ARB_SCHEME (bit 7)
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*/
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if (AMDGPU_IS_MGFX0(adev->grbm_chip_rev) ||
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AMDGPU_IS_MGFX1(adev->grbm_chip_rev)) {
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uint32_t data = RREG32_SOC15(GC, 0, mmSQ_CONFIG);
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data = REG_SET_FIELD(data, SQ_CONFIG,
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NEW_TRANS_ARB_SCHEME, 1);
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WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CONFIG), data);
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}
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#endif
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return 0;
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}
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#ifdef DRM_SGPU_PROGRAM_RSMU
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#include "rsmu/rsmu_0_0_2_offset.h"
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void sgpu_mm_wreg32(void __iomem *addr, uint32_t value)
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{
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if (sgpu_no_hw_access == 0)
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writel(value, addr);
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}
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void emu_write_rsmu_registers(struct amdgpu_device *adev)
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{
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DRM_INFO("%s] Configure RSMU: register mmio base: 0x%px\n",__func__, (void*)adev->rmmio_base);
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DRM_INFO("%s] Configure RSMU: register mmio size: %u\n",__func__, (unsigned)adev->rmmio_size);
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sgpu_mm_wreg32(adev->rmmio + RSMU_AEB_LOCK_0_GC, 0xfffffff8);
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sgpu_mm_wreg32(adev->rmmio + RSMU_AEB_LOCK_1_GC, 0xffffffff);
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sgpu_mm_wreg32(adev->rmmio + RSMU_COLD_RESETB_GC, 0x00000001);
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sgpu_mm_wreg32(adev->rmmio + RSMU_HARD_RESETB_GC, 0x00000001);
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sgpu_mm_wreg32(adev->rmmio + RSMU_CUSTOM_HARD_RESETB_GC, 0x00000007);
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sgpu_mm_wreg32(adev->rmmio + RSMU_SEC_MASTER_TRUST_LEVEL_6_GC, 0x00ffffdb);
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sgpu_mm_wreg32(adev->rmmio + RSMU_SEC_MISC_MASK_SET0_GROUP_DEFAULT_GC, 0x000001ff);
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sgpu_mm_wreg32(adev->rmmio + RSMU_SEC_MISC_MASK_SET1_GROUP_DEFAULT_GC, 0x000002ff);
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sgpu_mm_wreg32(adev->rmmio + RSMU_SEC_ACCESS_CONTROL_GROUP_DEFAULT_GC, 0x00000036);
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sgpu_mm_wreg32(adev->rmmio + RSMU_SEC_START_ADDR_GROUP_0_GC, 0x0003f000);
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sgpu_mm_wreg32(adev->rmmio + RSMU_SEC_END_ADDR_GROUP_0_GC, 0x0003ffff);
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sgpu_mm_wreg32(adev->rmmio + RSMU_SEC_MISC_MASK_SET0_GROUP_0_GC, 0x00000101);
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sgpu_mm_wreg32(adev->rmmio + RSMU_SEC_MISC_MASK_SET1_GROUP_0_GC, 0x00000201);
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sgpu_mm_wreg32(adev->rmmio + RSMU_SEC_ACCESS_CONTROL_GROUP_0_GC, 0x00000036);
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sgpu_mm_wreg32(adev->rmmio + RSMU_SEC_START_ADDR_GROUP_1_GC, 0x0003e000);
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sgpu_mm_wreg32(adev->rmmio + RSMU_SEC_END_ADDR_GROUP_1_GC, 0x0003efff);
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sgpu_mm_wreg32(adev->rmmio + RSMU_SEC_MISC_MASK_SET0_GROUP_1_GC, 0x00000107);
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sgpu_mm_wreg32(adev->rmmio + RSMU_SEC_MISC_MASK_SET1_GROUP_1_GC, 0x00000207);
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sgpu_mm_wreg32(adev->rmmio + RSMU_SEC_ACCESS_CONTROL_GROUP_1_GC, 0x00000036);
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sgpu_mm_wreg32(adev->rmmio + RSMU_SEC_START_ADDR_GROUP_2_GC, 0x0003a000);
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sgpu_mm_wreg32(adev->rmmio + RSMU_SEC_END_ADDR_GROUP_2_GC, 0x0003afff);
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sgpu_mm_wreg32(adev->rmmio + RSMU_SEC_MISC_MASK_SET0_GROUP_2_GC,0x00000107);
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sgpu_mm_wreg32(adev->rmmio + RSMU_SEC_MISC_MASK_SET1_GROUP_2_GC,0x00000207);
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sgpu_mm_wreg32(adev->rmmio + RSMU_SEC_ACCESS_CONTROL_GROUP_2_GC,0x00000036);
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sgpu_mm_wreg32(adev->rmmio + RSMU_SEC_START_ADDR_GROUP_3_GC, 0x0003a01c);
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sgpu_mm_wreg32(adev->rmmio + RSMU_SEC_END_ADDR_GROUP_3_GC, 0x0003a027);
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sgpu_mm_wreg32(adev->rmmio + RSMU_SEC_MISC_MASK_SET0_GROUP_3_GC, 0x00000107);
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sgpu_mm_wreg32(adev->rmmio + RSMU_SEC_MISC_MASK_SET1_GROUP_3_GC, 0x000002ff);
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sgpu_mm_wreg32(adev->rmmio + RSMU_SEC_ACCESS_CONTROL_GROUP_3_GC, 0x00000036);
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sgpu_mm_wreg32(adev->rmmio + RSMU_SEC_START_ADDR_GROUP_4_GC, 0x0003b20c);
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sgpu_mm_wreg32(adev->rmmio + RSMU_SEC_END_ADDR_GROUP_4_GC, 0x0003b21b);
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sgpu_mm_wreg32(adev->rmmio + RSMU_SEC_MISC_MASK_SET0_GROUP_4_GC, 0x00000107);
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sgpu_mm_wreg32(adev->rmmio + RSMU_SEC_MISC_MASK_SET1_GROUP_4_GC, 0x00000207);
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sgpu_mm_wreg32(adev->rmmio + RSMU_SEC_ACCESS_CONTROL_GROUP_4_GC, 0x00000036);
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sgpu_mm_wreg32(adev->rmmio + RSMU_SEC_MASTER_TRUST_LEVEL_RSMU_GC, 0x004bffff);
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sgpu_mm_wreg32(adev->rmmio + RSMU_SEC_ACCESS_CONTROL_RSMU_GC, 0x00007fff);
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sgpu_mm_wreg32(adev->rmmio + RSMU_SEC_SLAVE_RANGE_ENABLE_GC, 0x0000001f);
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}
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#else
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void emu_write_rsmu_registers(struct amdgpu_device *adev) {}
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#endif
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