2024-06-15 16:02:09 -03:00
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/dts-v1/;
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/ {
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interrupt-parent = <0x01>;
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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model = "OrangePi One Plus";
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2024-06-15 16:25:47 -03:00
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compatible = "xunlong,orangepi-one-plus", "allwinner,sun50i-h6";
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2024-06-15 16:02:09 -03:00
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cpus {
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#address-cells = <0x01>;
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#size-cells = <0x00>;
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cpu@0 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <0x00>;
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enable-method = "psci";
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clocks = <0x02 0x15>;
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clock-latency-ns = <0x3b9b0>;
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#cooling-cells = <0x02>;
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phandle = <0x04>;
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};
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cpu@1 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <0x01>;
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enable-method = "psci";
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clocks = <0x02 0x15>;
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clock-latency-ns = <0x3b9b0>;
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#cooling-cells = <0x02>;
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phandle = <0x05>;
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};
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cpu@2 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <0x02>;
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enable-method = "psci";
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clocks = <0x02 0x15>;
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clock-latency-ns = <0x3b9b0>;
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#cooling-cells = <0x02>;
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phandle = <0x06>;
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};
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cpu@3 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <0x03>;
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enable-method = "psci";
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clocks = <0x02 0x15>;
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clock-latency-ns = <0x3b9b0>;
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#cooling-cells = <0x02>;
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phandle = <0x07>;
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};
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};
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display-engine {
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compatible = "allwinner,sun50i-h6-display-engine";
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allwinner,pipelines = <0x03>;
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status = "okay";
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phandle = <0x3b>;
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};
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osc24M_clk {
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#clock-cells = <0x00>;
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compatible = "fixed-clock";
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clock-frequency = <0x16e3600>;
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clock-output-names = "osc24M";
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phandle = <0x0e>;
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};
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pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <0x00 0x8c 0x04 0x00 0x8d 0x04 0x00 0x8e 0x04 0x00 0x8f 0x04>;
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interrupt-affinity = <0x04 0x05 0x06 0x07>;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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arm,no-tick-in-suspend;
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interrupts = <0x01 0x0d 0xf04 0x01 0x0e 0xf04 0x01 0x0b 0xf04 0x01 0x0a 0xf04>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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ranges;
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bus@1000000 {
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2024-06-15 16:25:47 -03:00
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compatible = "allwinner,sun50i-h6-de3", "allwinner,sun50i-a64-de2";
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2024-06-15 16:02:09 -03:00
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reg = <0x1000000 0x400000>;
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allwinner,sram = <0x08 0x01>;
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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ranges = <0x00 0x1000000 0x400000>;
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clock@0 {
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compatible = "allwinner,sun50i-h6-de3-clk";
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reg = <0x00 0x10000>;
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clocks = <0x02 0x1d 0x02 0x1e>;
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2024-06-15 16:25:47 -03:00
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clock-names = "mod", "bus";
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2024-06-15 16:02:09 -03:00
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resets = <0x02 0x01>;
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#clock-cells = <0x01>;
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#reset-cells = <0x01>;
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phandle = <0x09>;
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};
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mixer@100000 {
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compatible = "allwinner,sun50i-h6-de3-mixer-0";
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reg = <0x100000 0x100000>;
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clocks = <0x09 0x00 0x09 0x06>;
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2024-06-15 16:25:47 -03:00
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clock-names = "bus", "mod";
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2024-06-15 16:02:09 -03:00
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resets = <0x09 0x00>;
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iommus = <0x0a 0x00>;
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phandle = <0x03>;
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ports {
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#address-cells = <0x01>;
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#size-cells = <0x00>;
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port@1 {
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reg = <0x01>;
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phandle = <0x3c>;
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endpoint {
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remote-endpoint = <0x0b>;
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phandle = <0x28>;
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};
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};
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};
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};
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};
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video-codec@1c0e000 {
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compatible = "allwinner,sun50i-h6-video-engine";
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reg = <0x1c0e000 0x2000>;
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clocks = <0x02 0x26 0x02 0x25 0x02 0x36>;
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2024-06-15 16:25:47 -03:00
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clock-names = "ahb", "mod", "ram";
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2024-06-15 16:02:09 -03:00
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resets = <0x02 0x05>;
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interrupts = <0x00 0x59 0x04>;
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allwinner,sram = <0x0c 0x01>;
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iommus = <0x0a 0x03>;
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};
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gpu@1800000 {
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2024-06-15 16:25:47 -03:00
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compatible = "allwinner,sun50i-h6-mali", "arm,mali-t720";
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2024-06-15 16:02:09 -03:00
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reg = <0x1800000 0x4000>;
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interrupts = <0x00 0x54 0x04 0x00 0x55 0x04 0x00 0x53 0x04>;
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2024-06-15 16:25:47 -03:00
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interrupt-names = "job", "mmu", "gpu";
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2024-06-15 16:02:09 -03:00
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clocks = <0x02 0x21 0x02 0x22>;
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2024-06-15 16:25:47 -03:00
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clock-names = "core", "bus";
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2024-06-15 16:02:09 -03:00
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resets = <0x02 0x03>;
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status = "okay";
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mali-supply = <0x0d>;
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phandle = <0x3d>;
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};
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crypto@1904000 {
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compatible = "allwinner,sun50i-h6-crypto";
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reg = <0x1904000 0x1000>;
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interrupts = <0x00 0x57 0x04>;
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clocks = <0x02 0x24 0x02 0x23 0x02 0x37>;
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2024-06-15 16:25:47 -03:00
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clock-names = "bus", "mod", "ram";
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2024-06-15 16:02:09 -03:00
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resets = <0x02 0x04>;
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phandle = <0x3e>;
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};
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syscon@3000000 {
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2024-06-15 16:25:47 -03:00
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compatible = "allwinner,sun50i-h6-system-control", "allwinner,sun50i-a64-system-control";
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2024-06-15 16:02:09 -03:00
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reg = <0x3000000 0x1000>;
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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ranges;
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phandle = <0x1c>;
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sram@28000 {
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compatible = "mmio-sram";
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reg = <0x28000 0x1e000>;
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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ranges = <0x00 0x28000 0x1e000>;
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phandle = <0x3f>;
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sram-section@0 {
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2024-06-15 16:25:47 -03:00
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compatible = "allwinner,sun50i-h6-sram-c", "allwinner,sun50i-a64-sram-c";
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2024-06-15 16:02:09 -03:00
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reg = <0x00 0x1e000>;
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phandle = <0x08>;
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};
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};
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sram@1a00000 {
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compatible = "mmio-sram";
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reg = <0x1a00000 0x200000>;
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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ranges = <0x00 0x1a00000 0x200000>;
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phandle = <0x40>;
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sram-section@0 {
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2024-06-15 16:25:47 -03:00
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compatible = "allwinner,sun50i-h6-sram-c1", "allwinner,sun4i-a10-sram-c1";
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2024-06-15 16:02:09 -03:00
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reg = <0x00 0x200000>;
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phandle = <0x0c>;
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};
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};
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};
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clock@3001000 {
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compatible = "allwinner,sun50i-h6-ccu";
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reg = <0x3001000 0x1000>;
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clocks = <0x0e 0x0f 0x00 0x0f 0x02>;
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2024-06-15 16:25:47 -03:00
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clock-names = "hosc", "losc", "iosc";
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2024-06-15 16:02:09 -03:00
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#clock-cells = <0x01>;
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#reset-cells = <0x01>;
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phandle = <0x02>;
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};
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dma-controller@3002000 {
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compatible = "allwinner,sun50i-h6-dma";
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reg = <0x3002000 0x1000>;
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interrupts = <0x00 0x2b 0x04>;
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clocks = <0x02 0x2b 0x02 0x35>;
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2024-06-15 16:25:47 -03:00
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clock-names = "bus", "mbus";
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2024-06-15 16:02:09 -03:00
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dma-channels = <0x10>;
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dma-requests = <0x2e>;
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resets = <0x02 0x08>;
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#dma-cells = <0x01>;
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phandle = <0x1b>;
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};
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mailbox@3003000 {
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2024-06-15 16:25:47 -03:00
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compatible = "allwinner,sun50i-h6-msgbox", "allwinner,sun6i-a31-msgbox";
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2024-06-15 16:02:09 -03:00
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reg = <0x3003000 0x1000>;
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clocks = <0x02 0x2c>;
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resets = <0x02 0x09>;
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interrupts = <0x00 0x2c 0x04>;
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#mbox-cells = <0x01>;
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phandle = <0x41>;
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};
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efuse@3006000 {
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compatible = "allwinner,sun50i-h6-sid";
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reg = <0x3006000 0x400>;
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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phandle = <0x42>;
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thermal-sensor-calibration@14 {
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reg = <0x14 0x08>;
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phandle = <0x35>;
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};
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cpu-speed-grade@1c {
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reg = <0x1c 0x04>;
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phandle = <0x43>;
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};
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};
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watchdog@30090a0 {
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2024-06-15 16:25:47 -03:00
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compatible = "allwinner,sun50i-h6-wdt", "allwinner,sun6i-a31-wdt";
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2024-06-15 16:02:09 -03:00
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reg = <0x30090a0 0x20>;
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interrupts = <0x00 0x32 0x04>;
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clocks = <0x0e>;
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status = "disabled";
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phandle = <0x44>;
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};
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pwm@300a000 {
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compatible = "allwinner,sun50i-h6-pwm";
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reg = <0x300a000 0x400>;
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clocks = <0x0e 0x02 0x32>;
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2024-06-15 16:25:47 -03:00
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clock-names = "mod", "bus";
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2024-06-15 16:02:09 -03:00
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resets = <0x02 0x0e>;
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#pwm-cells = <0x03>;
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status = "disabled";
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phandle = <0x45>;
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};
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pinctrl@300b000 {
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compatible = "allwinner,sun50i-h6-pinctrl";
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reg = <0x300b000 0x400>;
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interrupts = <0x00 0x33 0x04 0x00 0x35 0x04 0x00 0x36 0x04 0x00 0x3b 0x04>;
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clocks = <0x02 0x1a 0x0e 0x0f 0x00>;
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2024-06-15 16:25:47 -03:00
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clock-names = "apb", "hosc", "losc";
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2024-06-15 16:02:09 -03:00
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gpio-controller;
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#gpio-cells = <0x03>;
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interrupt-controller;
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#interrupt-cells = <0x03>;
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vcc-pc-supply = <0x10>;
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|
|
|
vcc-pd-supply = <0x11>;
|
|
|
|
|
vcc-pg-supply = <0x12>;
|
|
|
|
|
phandle = <0x14>;
|
|
|
|
|
|
|
|
|
|
rgmii-pins {
|
2024-06-15 16:25:47 -03:00
|
|
|
pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD7", "PD8", "PD9", "PD10", "PD11", "PD12", "PD13", "PD19", "PD20";
|
2024-06-15 16:02:09 -03:00
|
|
|
function = "emac";
|
|
|
|
|
drive-strength = <0x28>;
|
|
|
|
|
phandle = <0x1d>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
hdmi-pins {
|
2024-06-15 16:25:47 -03:00
|
|
|
pins = "PH8", "PH9", "PH10";
|
2024-06-15 16:02:09 -03:00
|
|
|
function = "hdmi";
|
|
|
|
|
phandle = <0x25>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c0-pins {
|
2024-06-15 16:25:47 -03:00
|
|
|
pins = "PD25", "PD26";
|
2024-06-15 16:02:09 -03:00
|
|
|
function = "i2c0";
|
|
|
|
|
phandle = <0x18>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c1-pins {
|
2024-06-15 16:25:47 -03:00
|
|
|
pins = "PH5", "PH6";
|
2024-06-15 16:02:09 -03:00
|
|
|
function = "i2c1";
|
|
|
|
|
phandle = <0x19>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c2-pins {
|
2024-06-15 16:25:47 -03:00
|
|
|
pins = "PD23", "PD24";
|
2024-06-15 16:02:09 -03:00
|
|
|
function = "i2c2";
|
|
|
|
|
phandle = <0x1a>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mmc0-pins {
|
2024-06-15 16:25:47 -03:00
|
|
|
pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
|
2024-06-15 16:02:09 -03:00
|
|
|
function = "mmc0";
|
|
|
|
|
drive-strength = <0x1e>;
|
|
|
|
|
bias-pull-up;
|
|
|
|
|
phandle = <0x13>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mmc1-pins {
|
2024-06-15 16:25:47 -03:00
|
|
|
pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
|
2024-06-15 16:02:09 -03:00
|
|
|
function = "mmc1";
|
|
|
|
|
drive-strength = <0x1e>;
|
|
|
|
|
bias-pull-up;
|
|
|
|
|
phandle = <0x15>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mmc2-pins {
|
2024-06-15 16:25:47 -03:00
|
|
|
pins = "PC1", "PC4", "PC5", "PC6", "PC7", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14";
|
2024-06-15 16:02:09 -03:00
|
|
|
function = "mmc2";
|
|
|
|
|
drive-strength = <0x1e>;
|
|
|
|
|
bias-pull-up;
|
|
|
|
|
phandle = <0x16>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
spi0-pins {
|
2024-06-15 16:25:47 -03:00
|
|
|
pins = "PC0", "PC2", "PC3";
|
2024-06-15 16:02:09 -03:00
|
|
|
function = "spi0";
|
|
|
|
|
phandle = <0x46>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
spi0-cs-pin {
|
|
|
|
|
pins = "PC5";
|
|
|
|
|
function = "spi0";
|
|
|
|
|
phandle = <0x47>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
spi1-pins {
|
2024-06-15 16:25:47 -03:00
|
|
|
pins = "PH4", "PH5", "PH6";
|
2024-06-15 16:02:09 -03:00
|
|
|
function = "spi1";
|
|
|
|
|
phandle = <0x48>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
spi1-cs-pin {
|
|
|
|
|
pins = "PH3";
|
|
|
|
|
function = "spi1";
|
|
|
|
|
phandle = <0x49>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
spdif-tx-pin {
|
|
|
|
|
pins = "PH7";
|
|
|
|
|
function = "spdif";
|
|
|
|
|
phandle = <0x20>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart0-ph-pins {
|
2024-06-15 16:25:47 -03:00
|
|
|
pins = "PH0", "PH1";
|
2024-06-15 16:02:09 -03:00
|
|
|
function = "uart0";
|
|
|
|
|
phandle = <0x17>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart1-pins {
|
2024-06-15 16:25:47 -03:00
|
|
|
pins = "PG6", "PG7";
|
2024-06-15 16:02:09 -03:00
|
|
|
function = "uart1";
|
|
|
|
|
phandle = <0x4a>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart1-rts-cts-pins {
|
2024-06-15 16:25:47 -03:00
|
|
|
pins = "PG8", "PG9";
|
2024-06-15 16:02:09 -03:00
|
|
|
function = "uart1";
|
|
|
|
|
phandle = <0x4b>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
interrupt-controller@3021000 {
|
|
|
|
|
compatible = "arm,gic-400";
|
|
|
|
|
reg = <0x3021000 0x1000 0x3022000 0x2000 0x3024000 0x2000 0x3026000 0x2000>;
|
|
|
|
|
interrupts = <0x01 0x09 0xf04>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <0x03>;
|
|
|
|
|
phandle = <0x01>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
iommu@30f0000 {
|
|
|
|
|
compatible = "allwinner,sun50i-h6-iommu";
|
|
|
|
|
reg = <0x30f0000 0x10000>;
|
|
|
|
|
interrupts = <0x00 0x39 0x04>;
|
|
|
|
|
clocks = <0x02 0x33>;
|
|
|
|
|
resets = <0x02 0x0f>;
|
|
|
|
|
#iommu-cells = <0x01>;
|
|
|
|
|
phandle = <0x0a>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mmc@4020000 {
|
2024-06-15 16:25:47 -03:00
|
|
|
compatible = "allwinner,sun50i-h6-mmc", "allwinner,sun50i-a64-mmc";
|
2024-06-15 16:02:09 -03:00
|
|
|
reg = <0x4020000 0x1000>;
|
|
|
|
|
clocks = <0x02 0x43 0x02 0x40>;
|
2024-06-15 16:25:47 -03:00
|
|
|
clock-names = "ahb", "mmc";
|
2024-06-15 16:02:09 -03:00
|
|
|
resets = <0x02 0x12>;
|
|
|
|
|
reset-names = "ahb";
|
|
|
|
|
interrupts = <0x00 0x23 0x04>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <0x13>;
|
|
|
|
|
max-frequency = <0x8f0d180>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
#address-cells = <0x01>;
|
|
|
|
|
#size-cells = <0x00>;
|
|
|
|
|
vmmc-supply = <0x11>;
|
|
|
|
|
cd-gpios = <0x14 0x05 0x06 0x01>;
|
|
|
|
|
bus-width = <0x04>;
|
|
|
|
|
phandle = <0x4c>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mmc@4021000 {
|
2024-06-15 16:25:47 -03:00
|
|
|
compatible = "allwinner,sun50i-h6-mmc", "allwinner,sun50i-a64-mmc";
|
2024-06-15 16:02:09 -03:00
|
|
|
reg = <0x4021000 0x1000>;
|
|
|
|
|
clocks = <0x02 0x44 0x02 0x41>;
|
2024-06-15 16:25:47 -03:00
|
|
|
clock-names = "ahb", "mmc";
|
2024-06-15 16:02:09 -03:00
|
|
|
resets = <0x02 0x13>;
|
|
|
|
|
reset-names = "ahb";
|
|
|
|
|
interrupts = <0x00 0x24 0x04>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <0x15>;
|
|
|
|
|
max-frequency = <0x8f0d180>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
#address-cells = <0x01>;
|
|
|
|
|
#size-cells = <0x00>;
|
|
|
|
|
phandle = <0x4d>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mmc@4022000 {
|
2024-06-15 16:25:47 -03:00
|
|
|
compatible = "allwinner,sun50i-h6-emmc", "allwinner,sun50i-a64-emmc";
|
2024-06-15 16:02:09 -03:00
|
|
|
reg = <0x4022000 0x1000>;
|
|
|
|
|
clocks = <0x02 0x45 0x02 0x42>;
|
2024-06-15 16:25:47 -03:00
|
|
|
clock-names = "ahb", "mmc";
|
2024-06-15 16:02:09 -03:00
|
|
|
resets = <0x02 0x14>;
|
|
|
|
|
reset-names = "ahb";
|
|
|
|
|
interrupts = <0x00 0x25 0x04>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <0x16>;
|
|
|
|
|
max-frequency = <0x8f0d180>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
#address-cells = <0x01>;
|
|
|
|
|
#size-cells = <0x00>;
|
|
|
|
|
phandle = <0x4e>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
serial@5000000 {
|
|
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
|
|
reg = <0x5000000 0x400>;
|
|
|
|
|
interrupts = <0x00 0x00 0x04>;
|
|
|
|
|
reg-shift = <0x02>;
|
|
|
|
|
reg-io-width = <0x04>;
|
|
|
|
|
clocks = <0x02 0x46>;
|
|
|
|
|
resets = <0x02 0x15>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <0x17>;
|
|
|
|
|
phandle = <0x4f>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
serial@5000400 {
|
|
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
|
|
reg = <0x5000400 0x400>;
|
|
|
|
|
interrupts = <0x00 0x01 0x04>;
|
|
|
|
|
reg-shift = <0x02>;
|
|
|
|
|
reg-io-width = <0x04>;
|
|
|
|
|
clocks = <0x02 0x47>;
|
|
|
|
|
resets = <0x02 0x16>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
phandle = <0x50>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
serial@5000800 {
|
|
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
|
|
reg = <0x5000800 0x400>;
|
|
|
|
|
interrupts = <0x00 0x02 0x04>;
|
|
|
|
|
reg-shift = <0x02>;
|
|
|
|
|
reg-io-width = <0x04>;
|
|
|
|
|
clocks = <0x02 0x48>;
|
|
|
|
|
resets = <0x02 0x17>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
phandle = <0x51>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
serial@5000c00 {
|
|
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
|
|
reg = <0x5000c00 0x400>;
|
|
|
|
|
interrupts = <0x00 0x03 0x04>;
|
|
|
|
|
reg-shift = <0x02>;
|
|
|
|
|
reg-io-width = <0x04>;
|
|
|
|
|
clocks = <0x02 0x49>;
|
|
|
|
|
resets = <0x02 0x18>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
phandle = <0x52>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c@5002000 {
|
2024-06-15 16:25:47 -03:00
|
|
|
compatible = "allwinner,sun50i-h6-i2c", "allwinner,sun6i-a31-i2c";
|
2024-06-15 16:02:09 -03:00
|
|
|
reg = <0x5002000 0x400>;
|
|
|
|
|
interrupts = <0x00 0x04 0x04>;
|
|
|
|
|
clocks = <0x02 0x4a>;
|
|
|
|
|
resets = <0x02 0x19>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <0x18>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
#address-cells = <0x01>;
|
|
|
|
|
#size-cells = <0x00>;
|
|
|
|
|
phandle = <0x53>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c@5002400 {
|
2024-06-15 16:25:47 -03:00
|
|
|
compatible = "allwinner,sun50i-h6-i2c", "allwinner,sun6i-a31-i2c";
|
2024-06-15 16:02:09 -03:00
|
|
|
reg = <0x5002400 0x400>;
|
|
|
|
|
interrupts = <0x00 0x05 0x04>;
|
|
|
|
|
clocks = <0x02 0x4b>;
|
|
|
|
|
resets = <0x02 0x1a>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <0x19>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
#address-cells = <0x01>;
|
|
|
|
|
#size-cells = <0x00>;
|
|
|
|
|
phandle = <0x54>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c@5002800 {
|
2024-06-15 16:25:47 -03:00
|
|
|
compatible = "allwinner,sun50i-h6-i2c", "allwinner,sun6i-a31-i2c";
|
2024-06-15 16:02:09 -03:00
|
|
|
reg = <0x5002800 0x400>;
|
|
|
|
|
interrupts = <0x00 0x06 0x04>;
|
|
|
|
|
clocks = <0x02 0x4c>;
|
|
|
|
|
resets = <0x02 0x1b>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <0x1a>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
#address-cells = <0x01>;
|
|
|
|
|
#size-cells = <0x00>;
|
|
|
|
|
phandle = <0x55>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
spi@5010000 {
|
2024-06-15 16:25:47 -03:00
|
|
|
compatible = "allwinner,sun50i-h6-spi", "allwinner,sun8i-h3-spi";
|
2024-06-15 16:02:09 -03:00
|
|
|
reg = <0x5010000 0x1000>;
|
|
|
|
|
interrupts = <0x00 0x0a 0x04>;
|
|
|
|
|
clocks = <0x02 0x52 0x02 0x50>;
|
2024-06-15 16:25:47 -03:00
|
|
|
clock-names = "ahb", "mod";
|
2024-06-15 16:02:09 -03:00
|
|
|
dmas = <0x1b 0x16 0x1b 0x16>;
|
2024-06-15 16:25:47 -03:00
|
|
|
dma-names = "rx", "tx";
|
2024-06-15 16:02:09 -03:00
|
|
|
resets = <0x02 0x1f>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
#address-cells = <0x01>;
|
|
|
|
|
#size-cells = <0x00>;
|
|
|
|
|
phandle = <0x56>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
spi@5011000 {
|
2024-06-15 16:25:47 -03:00
|
|
|
compatible = "allwinner,sun50i-h6-spi", "allwinner,sun8i-h3-spi";
|
2024-06-15 16:02:09 -03:00
|
|
|
reg = <0x5011000 0x1000>;
|
|
|
|
|
interrupts = <0x00 0x0b 0x04>;
|
|
|
|
|
clocks = <0x02 0x53 0x02 0x51>;
|
2024-06-15 16:25:47 -03:00
|
|
|
clock-names = "ahb", "mod";
|
2024-06-15 16:02:09 -03:00
|
|
|
dmas = <0x1b 0x17 0x1b 0x17>;
|
2024-06-15 16:25:47 -03:00
|
|
|
dma-names = "rx", "tx";
|
2024-06-15 16:02:09 -03:00
|
|
|
resets = <0x02 0x20>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
#address-cells = <0x01>;
|
|
|
|
|
#size-cells = <0x00>;
|
|
|
|
|
phandle = <0x57>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ethernet@5020000 {
|
2024-06-15 16:25:47 -03:00
|
|
|
compatible = "allwinner,sun50i-h6-emac", "allwinner,sun50i-a64-emac";
|
2024-06-15 16:02:09 -03:00
|
|
|
syscon = <0x1c>;
|
|
|
|
|
reg = <0x5020000 0x10000>;
|
|
|
|
|
interrupts = <0x00 0x0c 0x04>;
|
|
|
|
|
interrupt-names = "macirq";
|
|
|
|
|
resets = <0x02 0x21>;
|
|
|
|
|
reset-names = "stmmaceth";
|
|
|
|
|
clocks = <0x02 0x54>;
|
|
|
|
|
clock-names = "stmmaceth";
|
|
|
|
|
status = "okay";
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <0x1d>;
|
|
|
|
|
phy-mode = "rgmii-id";
|
|
|
|
|
phy-handle = <0x1e>;
|
|
|
|
|
phy-supply = <0x1f>;
|
|
|
|
|
allwinner,rx-delay-ps = <0xc8>;
|
|
|
|
|
allwinner,tx-delay-ps = <0xc8>;
|
|
|
|
|
phandle = <0x58>;
|
|
|
|
|
|
|
|
|
|
mdio {
|
|
|
|
|
compatible = "snps,dwmac-mdio";
|
|
|
|
|
#address-cells = <0x01>;
|
|
|
|
|
#size-cells = <0x00>;
|
|
|
|
|
phandle = <0x59>;
|
|
|
|
|
|
|
|
|
|
ethernet-phy@1 {
|
|
|
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
|
|
|
reg = <0x01>;
|
|
|
|
|
phandle = <0x1e>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
spdif@5093000 {
|
|
|
|
|
#sound-dai-cells = <0x00>;
|
|
|
|
|
compatible = "allwinner,sun50i-h6-spdif";
|
|
|
|
|
reg = <0x5093000 0x400>;
|
|
|
|
|
interrupts = <0x00 0x15 0x04>;
|
|
|
|
|
clocks = <0x02 0x63 0x02 0x62>;
|
2024-06-15 16:25:47 -03:00
|
|
|
clock-names = "apb", "spdif";
|
2024-06-15 16:02:09 -03:00
|
|
|
resets = <0x02 0x29>;
|
|
|
|
|
dmas = <0x1b 0x02>;
|
|
|
|
|
dma-names = "tx";
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <0x20>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
phandle = <0x5a>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb@5100000 {
|
2024-06-15 16:25:47 -03:00
|
|
|
compatible = "allwinner,sun50i-h6-musb", "allwinner,sun8i-a33-musb";
|
2024-06-15 16:02:09 -03:00
|
|
|
reg = <0x5100000 0x400>;
|
|
|
|
|
clocks = <0x02 0x74>;
|
|
|
|
|
resets = <0x02 0x35>;
|
|
|
|
|
interrupts = <0x00 0x17 0x04>;
|
|
|
|
|
interrupt-names = "mc";
|
|
|
|
|
phys = <0x21 0x00>;
|
|
|
|
|
phy-names = "usb";
|
|
|
|
|
extcon = <0x21 0x00>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
dr_mode = "host";
|
|
|
|
|
phandle = <0x5b>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
phy@5100400 {
|
|
|
|
|
compatible = "allwinner,sun50i-h6-usb-phy";
|
|
|
|
|
reg = <0x5100400 0x24 0x5101800 0x04 0x5311800 0x04>;
|
2024-06-15 16:25:47 -03:00
|
|
|
reg-names = "phy_ctrl", "pmu0", "pmu3";
|
2024-06-15 16:02:09 -03:00
|
|
|
clocks = <0x02 0x69 0x02 0x6c>;
|
2024-06-15 16:25:47 -03:00
|
|
|
clock-names = "usb0_phy", "usb3_phy";
|
2024-06-15 16:02:09 -03:00
|
|
|
resets = <0x02 0x2c 0x02 0x2e>;
|
2024-06-15 16:25:47 -03:00
|
|
|
reset-names = "usb0_reset", "usb3_reset";
|
2024-06-15 16:02:09 -03:00
|
|
|
status = "okay";
|
|
|
|
|
#phy-cells = <0x01>;
|
|
|
|
|
usb0_id_det-gpios = <0x14 0x02 0x06 0x00>;
|
|
|
|
|
usb0_vbus-supply = <0x22>;
|
|
|
|
|
usb3_vbus-supply = <0x22>;
|
|
|
|
|
phandle = <0x21>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb@5101000 {
|
2024-06-15 16:25:47 -03:00
|
|
|
compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
|
2024-06-15 16:02:09 -03:00
|
|
|
reg = <0x5101000 0x100>;
|
|
|
|
|
interrupts = <0x00 0x18 0x04>;
|
|
|
|
|
clocks = <0x02 0x6f 0x02 0x71 0x02 0x68>;
|
|
|
|
|
resets = <0x02 0x30 0x02 0x32>;
|
|
|
|
|
phys = <0x21 0x00>;
|
|
|
|
|
phy-names = "usb";
|
|
|
|
|
status = "okay";
|
|
|
|
|
phandle = <0x5c>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb@5101400 {
|
2024-06-15 16:25:47 -03:00
|
|
|
compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
|
2024-06-15 16:02:09 -03:00
|
|
|
reg = <0x5101400 0x100>;
|
|
|
|
|
interrupts = <0x00 0x19 0x04>;
|
|
|
|
|
clocks = <0x02 0x6f 0x02 0x68>;
|
|
|
|
|
resets = <0x02 0x30>;
|
|
|
|
|
phys = <0x21 0x00>;
|
|
|
|
|
phy-names = "usb";
|
|
|
|
|
status = "okay";
|
|
|
|
|
phandle = <0x5d>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
dwc3@5200000 {
|
|
|
|
|
compatible = "snps,dwc3";
|
|
|
|
|
reg = <0x5200000 0x10000>;
|
|
|
|
|
interrupts = <0x00 0x1a 0x04>;
|
|
|
|
|
clocks = <0x02 0x72 0x02 0x72 0x0f 0x00>;
|
2024-06-15 16:25:47 -03:00
|
|
|
clock-names = "ref", "bus_early", "suspend";
|
2024-06-15 16:02:09 -03:00
|
|
|
resets = <0x02 0x33>;
|
|
|
|
|
dr_mode = "host";
|
|
|
|
|
phys = <0x23>;
|
|
|
|
|
phy-names = "usb3-phy";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
phandle = <0x5e>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
phy@5210000 {
|
|
|
|
|
compatible = "allwinner,sun50i-h6-usb3-phy";
|
|
|
|
|
reg = <0x5210000 0x10000>;
|
|
|
|
|
clocks = <0x02 0x6a>;
|
|
|
|
|
resets = <0x02 0x2d>;
|
|
|
|
|
#phy-cells = <0x00>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
phandle = <0x23>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb@5311000 {
|
2024-06-15 16:25:47 -03:00
|
|
|
compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
|
2024-06-15 16:02:09 -03:00
|
|
|
reg = <0x5311000 0x100>;
|
|
|
|
|
interrupts = <0x00 0x1c 0x04>;
|
|
|
|
|
clocks = <0x02 0x70 0x02 0x73 0x02 0x6b>;
|
|
|
|
|
resets = <0x02 0x31 0x02 0x34>;
|
|
|
|
|
phys = <0x21 0x03>;
|
|
|
|
|
phy-names = "usb";
|
|
|
|
|
status = "okay";
|
|
|
|
|
phandle = <0x5f>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb@5311400 {
|
2024-06-15 16:25:47 -03:00
|
|
|
compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
|
2024-06-15 16:02:09 -03:00
|
|
|
reg = <0x5311400 0x100>;
|
|
|
|
|
interrupts = <0x00 0x1d 0x04>;
|
|
|
|
|
clocks = <0x02 0x70 0x02 0x6b>;
|
|
|
|
|
resets = <0x02 0x31>;
|
|
|
|
|
phys = <0x21 0x03>;
|
|
|
|
|
phy-names = "usb";
|
|
|
|
|
status = "okay";
|
|
|
|
|
phandle = <0x60>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
hdmi@6000000 {
|
|
|
|
|
compatible = "allwinner,sun50i-h6-dw-hdmi";
|
|
|
|
|
reg = <0x6000000 0x10000>;
|
|
|
|
|
reg-io-width = <0x01>;
|
|
|
|
|
interrupts = <0x00 0x40 0x04>;
|
|
|
|
|
clocks = <0x02 0x7e 0x02 0x7c 0x02 0x7b 0x02 0x7d 0x02 0x88 0x02 0x89>;
|
2024-06-15 16:25:47 -03:00
|
|
|
clock-names = "iahb", "isfr", "tmds", "cec", "hdcp", "hdcp-bus";
|
2024-06-15 16:02:09 -03:00
|
|
|
resets = <0x02 0x39 0x02 0x3e>;
|
2024-06-15 16:25:47 -03:00
|
|
|
reset-names = "ctrl", "hdcp";
|
2024-06-15 16:02:09 -03:00
|
|
|
phys = <0x24>;
|
|
|
|
|
phy-names = "phy";
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <0x25>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
phandle = <0x61>;
|
|
|
|
|
|
|
|
|
|
ports {
|
|
|
|
|
#address-cells = <0x01>;
|
|
|
|
|
#size-cells = <0x00>;
|
|
|
|
|
|
|
|
|
|
port@0 {
|
|
|
|
|
reg = <0x00>;
|
|
|
|
|
phandle = <0x62>;
|
|
|
|
|
|
|
|
|
|
endpoint {
|
|
|
|
|
remote-endpoint = <0x26>;
|
|
|
|
|
phandle = <0x2b>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
port@1 {
|
|
|
|
|
reg = <0x01>;
|
|
|
|
|
phandle = <0x63>;
|
|
|
|
|
|
|
|
|
|
endpoint {
|
|
|
|
|
remote-endpoint = <0x27>;
|
|
|
|
|
phandle = <0x38>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
hdmi-phy@6010000 {
|
|
|
|
|
compatible = "allwinner,sun50i-h6-hdmi-phy";
|
|
|
|
|
reg = <0x6010000 0x10000>;
|
|
|
|
|
clocks = <0x02 0x7e 0x02 0x7c>;
|
2024-06-15 16:25:47 -03:00
|
|
|
clock-names = "bus", "mod";
|
2024-06-15 16:02:09 -03:00
|
|
|
resets = <0x02 0x38>;
|
|
|
|
|
reset-names = "phy";
|
|
|
|
|
#phy-cells = <0x00>;
|
|
|
|
|
phandle = <0x24>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
tcon-top@6510000 {
|
|
|
|
|
compatible = "allwinner,sun50i-h6-tcon-top";
|
|
|
|
|
reg = <0x6510000 0x1000>;
|
|
|
|
|
clocks = <0x02 0x7f 0x02 0x82>;
|
2024-06-15 16:25:47 -03:00
|
|
|
clock-names = "bus", "tcon-tv0";
|
2024-06-15 16:02:09 -03:00
|
|
|
clock-output-names = "tcon-top-tv0";
|
|
|
|
|
resets = <0x02 0x3a>;
|
|
|
|
|
#clock-cells = <0x01>;
|
|
|
|
|
phandle = <0x2c>;
|
|
|
|
|
|
|
|
|
|
ports {
|
|
|
|
|
#address-cells = <0x01>;
|
|
|
|
|
#size-cells = <0x00>;
|
|
|
|
|
|
|
|
|
|
port@0 {
|
|
|
|
|
#address-cells = <0x01>;
|
|
|
|
|
#size-cells = <0x00>;
|
|
|
|
|
reg = <0x00>;
|
|
|
|
|
phandle = <0x64>;
|
|
|
|
|
|
|
|
|
|
endpoint@0 {
|
|
|
|
|
reg = <0x00>;
|
|
|
|
|
remote-endpoint = <0x28>;
|
|
|
|
|
phandle = <0x0b>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
port@1 {
|
|
|
|
|
#address-cells = <0x01>;
|
|
|
|
|
#size-cells = <0x00>;
|
|
|
|
|
reg = <0x01>;
|
|
|
|
|
phandle = <0x65>;
|
|
|
|
|
|
|
|
|
|
endpoint@2 {
|
|
|
|
|
reg = <0x02>;
|
|
|
|
|
remote-endpoint = <0x29>;
|
|
|
|
|
phandle = <0x2d>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
port@4 {
|
|
|
|
|
#address-cells = <0x01>;
|
|
|
|
|
#size-cells = <0x00>;
|
|
|
|
|
reg = <0x04>;
|
|
|
|
|
phandle = <0x66>;
|
|
|
|
|
|
|
|
|
|
endpoint@0 {
|
|
|
|
|
reg = <0x00>;
|
|
|
|
|
remote-endpoint = <0x2a>;
|
|
|
|
|
phandle = <0x2e>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
port@5 {
|
|
|
|
|
reg = <0x05>;
|
|
|
|
|
phandle = <0x67>;
|
|
|
|
|
|
|
|
|
|
endpoint {
|
|
|
|
|
remote-endpoint = <0x2b>;
|
|
|
|
|
phandle = <0x26>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
lcd-controller@6515000 {
|
2024-06-15 16:25:47 -03:00
|
|
|
compatible = "allwinner,sun50i-h6-tcon-tv", "allwinner,sun8i-r40-tcon-tv";
|
2024-06-15 16:02:09 -03:00
|
|
|
reg = <0x6515000 0x1000>;
|
|
|
|
|
interrupts = <0x00 0x42 0x04>;
|
|
|
|
|
clocks = <0x02 0x83 0x2c 0x00>;
|
2024-06-15 16:25:47 -03:00
|
|
|
clock-names = "ahb", "tcon-ch1";
|
2024-06-15 16:02:09 -03:00
|
|
|
resets = <0x02 0x3c>;
|
|
|
|
|
reset-names = "lcd";
|
|
|
|
|
phandle = <0x68>;
|
|
|
|
|
|
|
|
|
|
ports {
|
|
|
|
|
#address-cells = <0x01>;
|
|
|
|
|
#size-cells = <0x00>;
|
|
|
|
|
|
|
|
|
|
port@0 {
|
|
|
|
|
reg = <0x00>;
|
|
|
|
|
phandle = <0x69>;
|
|
|
|
|
|
|
|
|
|
endpoint {
|
|
|
|
|
remote-endpoint = <0x2d>;
|
|
|
|
|
phandle = <0x29>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
port@1 {
|
|
|
|
|
#address-cells = <0x01>;
|
|
|
|
|
#size-cells = <0x00>;
|
|
|
|
|
reg = <0x01>;
|
|
|
|
|
phandle = <0x6a>;
|
|
|
|
|
|
|
|
|
|
endpoint@1 {
|
|
|
|
|
reg = <0x01>;
|
|
|
|
|
remote-endpoint = <0x2e>;
|
|
|
|
|
phandle = <0x2a>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
rtc@7000000 {
|
|
|
|
|
compatible = "allwinner,sun50i-h6-rtc";
|
|
|
|
|
reg = <0x7000000 0x400>;
|
|
|
|
|
interrupts = <0x00 0x65 0x04 0x00 0x66 0x04>;
|
2024-06-15 16:25:47 -03:00
|
|
|
clock-output-names = "osc32k", "osc32k-out", "iosc";
|
2024-06-15 16:02:09 -03:00
|
|
|
#clock-cells = <0x01>;
|
|
|
|
|
clocks = <0x2f>;
|
|
|
|
|
phandle = <0x0f>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
clock@7010000 {
|
|
|
|
|
compatible = "allwinner,sun50i-h6-r-ccu";
|
|
|
|
|
reg = <0x7010000 0x400>;
|
|
|
|
|
clocks = <0x0e 0x0f 0x00 0x0f 0x02 0x02 0x03>;
|
2024-06-15 16:25:47 -03:00
|
|
|
clock-names = "hosc", "losc", "iosc", "pll-periph";
|
2024-06-15 16:02:09 -03:00
|
|
|
#clock-cells = <0x01>;
|
|
|
|
|
#reset-cells = <0x01>;
|
|
|
|
|
phandle = <0x30>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
watchdog@7020400 {
|
2024-06-15 16:25:47 -03:00
|
|
|
compatible = "allwinner,sun50i-h6-wdt", "allwinner,sun6i-a31-wdt";
|
2024-06-15 16:02:09 -03:00
|
|
|
reg = <0x7020400 0x20>;
|
|
|
|
|
interrupts = <0x00 0x67 0x04>;
|
|
|
|
|
clocks = <0x0e>;
|
|
|
|
|
phandle = <0x6b>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
interrupt-controller@7021000 {
|
2024-06-15 16:25:47 -03:00
|
|
|
compatible = "allwinner,sun50i-h6-r-intc", "allwinner,sun6i-a31-r-intc";
|
2024-06-15 16:02:09 -03:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <0x02>;
|
|
|
|
|
reg = <0x7021000 0x400>;
|
|
|
|
|
interrupts = <0x00 0x60 0x04>;
|
|
|
|
|
phandle = <0x34>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl@7022000 {
|
|
|
|
|
compatible = "allwinner,sun50i-h6-r-pinctrl";
|
|
|
|
|
reg = <0x7022000 0x400>;
|
|
|
|
|
interrupts = <0x00 0x69 0x04 0x00 0x6f 0x04>;
|
|
|
|
|
clocks = <0x30 0x02 0x0e 0x0f 0x00>;
|
2024-06-15 16:25:47 -03:00
|
|
|
clock-names = "apb", "hosc", "losc";
|
2024-06-15 16:02:09 -03:00
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <0x03>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <0x03>;
|
|
|
|
|
vcc-pm-supply = <0x31>;
|
|
|
|
|
phandle = <0x39>;
|
|
|
|
|
|
|
|
|
|
r-i2c-pins {
|
2024-06-15 16:25:47 -03:00
|
|
|
pins = "PL0", "PL1";
|
2024-06-15 16:02:09 -03:00
|
|
|
function = "s_i2c";
|
|
|
|
|
phandle = <0x33>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
r-ir-rx-pin {
|
|
|
|
|
pins = "PL9";
|
|
|
|
|
function = "s_cir_rx";
|
|
|
|
|
phandle = <0x32>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ir@7040000 {
|
2024-06-15 16:25:47 -03:00
|
|
|
compatible = "allwinner,sun50i-h6-ir", "allwinner,sun6i-a31-ir";
|
2024-06-15 16:02:09 -03:00
|
|
|
reg = <0x7040000 0x400>;
|
|
|
|
|
interrupts = <0x00 0x6d 0x04>;
|
|
|
|
|
clocks = <0x30 0x09 0x30 0x0b>;
|
2024-06-15 16:25:47 -03:00
|
|
|
clock-names = "apb", "ir";
|
2024-06-15 16:02:09 -03:00
|
|
|
resets = <0x30 0x05>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <0x32>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
phandle = <0x6c>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c@7081400 {
|
2024-06-15 16:25:47 -03:00
|
|
|
compatible = "allwinner,sun50i-h6-i2c", "allwinner,sun6i-a31-i2c";
|
2024-06-15 16:02:09 -03:00
|
|
|
reg = <0x7081400 0x400>;
|
|
|
|
|
interrupts = <0x00 0x6b 0x04>;
|
|
|
|
|
clocks = <0x30 0x08>;
|
|
|
|
|
resets = <0x30 0x04>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <0x33>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
#address-cells = <0x01>;
|
|
|
|
|
#size-cells = <0x00>;
|
|
|
|
|
phandle = <0x6d>;
|
|
|
|
|
|
|
|
|
|
pmic@36 {
|
2024-06-15 16:25:47 -03:00
|
|
|
compatible = "x-powers,axp805", "x-powers,axp806";
|
2024-06-15 16:02:09 -03:00
|
|
|
reg = <0x36>;
|
|
|
|
|
interrupt-parent = <0x34>;
|
|
|
|
|
interrupts = <0x00 0x08>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <0x01>;
|
|
|
|
|
x-powers,self-working-mode;
|
|
|
|
|
vina-supply = <0x22>;
|
|
|
|
|
vinb-supply = <0x22>;
|
|
|
|
|
vinc-supply = <0x22>;
|
|
|
|
|
vind-supply = <0x22>;
|
|
|
|
|
vine-supply = <0x22>;
|
|
|
|
|
aldoin-supply = <0x22>;
|
|
|
|
|
bldoin-supply = <0x22>;
|
|
|
|
|
cldoin-supply = <0x22>;
|
|
|
|
|
phandle = <0x6e>;
|
|
|
|
|
|
|
|
|
|
regulators {
|
|
|
|
|
|
|
|
|
|
aldo1 {
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
regulator-min-microvolt = <0x325aa0>;
|
|
|
|
|
regulator-max-microvolt = <0x325aa0>;
|
|
|
|
|
regulator-name = "vcc-pl";
|
|
|
|
|
phandle = <0x12>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
aldo2 {
|
|
|
|
|
regulator-min-microvolt = <0x325aa0>;
|
|
|
|
|
regulator-max-microvolt = <0x325aa0>;
|
|
|
|
|
regulator-name = "vcc-ac200";
|
|
|
|
|
phandle = <0x3a>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
aldo3 {
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
regulator-min-microvolt = <0x325aa0>;
|
|
|
|
|
regulator-max-microvolt = <0x325aa0>;
|
|
|
|
|
regulator-name = "vcc25-dram";
|
|
|
|
|
phandle = <0x6f>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
bldo1 {
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
regulator-min-microvolt = <0x1b7740>;
|
|
|
|
|
regulator-max-microvolt = <0x1b7740>;
|
|
|
|
|
regulator-name = "vcc-bias-pll";
|
|
|
|
|
phandle = <0x70>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
bldo2 {
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
regulator-min-microvolt = <0x1b7740>;
|
|
|
|
|
regulator-max-microvolt = <0x1b7740>;
|
|
|
|
|
regulator-name = "vcc-efuse-pcie-hdmi-io";
|
|
|
|
|
phandle = <0x10>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
bldo3 {
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
regulator-min-microvolt = <0x1b7740>;
|
|
|
|
|
regulator-max-microvolt = <0x1b7740>;
|
|
|
|
|
regulator-name = "vcc-dcxoio";
|
|
|
|
|
phandle = <0x31>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
bldo4 {
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
cldo1 {
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
regulator-min-microvolt = <0x325aa0>;
|
|
|
|
|
regulator-max-microvolt = <0x325aa0>;
|
|
|
|
|
regulator-name = "vcc-3v3";
|
|
|
|
|
phandle = <0x11>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
cldo2 {
|
|
|
|
|
regulator-min-microvolt = <0x325aa0>;
|
|
|
|
|
regulator-max-microvolt = <0x325aa0>;
|
|
|
|
|
regulator-name = "vcc-wifi-1";
|
|
|
|
|
phandle = <0x71>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
cldo3 {
|
|
|
|
|
regulator-min-microvolt = <0x325aa0>;
|
|
|
|
|
regulator-max-microvolt = <0x325aa0>;
|
|
|
|
|
regulator-name = "vcc-wifi-2";
|
|
|
|
|
phandle = <0x72>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
dcdca {
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
regulator-min-microvolt = <0xc5c10>;
|
|
|
|
|
regulator-max-microvolt = <0x107ac0>;
|
|
|
|
|
regulator-name = "vdd-cpu";
|
|
|
|
|
phandle = <0x73>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
dcdcc {
|
|
|
|
|
regulator-enable-ramp-delay = <0x7d00>;
|
|
|
|
|
regulator-min-microvolt = <0xc5c10>;
|
|
|
|
|
regulator-max-microvolt = <0x107ac0>;
|
|
|
|
|
regulator-name = "vdd-gpu";
|
|
|
|
|
phandle = <0x0d>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
dcdcd {
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
regulator-min-microvolt = <0xea600>;
|
|
|
|
|
regulator-max-microvolt = <0xea600>;
|
|
|
|
|
regulator-name = "vdd-sys";
|
|
|
|
|
phandle = <0x74>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
dcdce {
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
regulator-min-microvolt = <0x124f80>;
|
|
|
|
|
regulator-max-microvolt = <0x124f80>;
|
|
|
|
|
regulator-name = "vcc-dram";
|
|
|
|
|
phandle = <0x75>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
sw {
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
thermal-sensor@5070400 {
|
|
|
|
|
compatible = "allwinner,sun50i-h6-ths";
|
|
|
|
|
reg = <0x5070400 0x100>;
|
|
|
|
|
interrupts = <0x00 0x0f 0x04>;
|
|
|
|
|
clocks = <0x02 0x59>;
|
|
|
|
|
clock-names = "bus";
|
|
|
|
|
resets = <0x02 0x24>;
|
|
|
|
|
nvmem-cells = <0x35>;
|
|
|
|
|
nvmem-cell-names = "calibration";
|
|
|
|
|
#thermal-sensor-cells = <0x01>;
|
|
|
|
|
phandle = <0x36>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
thermal-zones {
|
|
|
|
|
|
|
|
|
|
cpu-thermal {
|
|
|
|
|
polling-delay-passive = <0x00>;
|
|
|
|
|
polling-delay = <0x00>;
|
|
|
|
|
thermal-sensors = <0x36 0x00>;
|
|
|
|
|
|
|
|
|
|
trips {
|
|
|
|
|
|
|
|
|
|
cpu-alert {
|
|
|
|
|
temperature = <0x14c08>;
|
|
|
|
|
hysteresis = <0x7d0>;
|
|
|
|
|
type = "passive";
|
|
|
|
|
phandle = <0x37>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
cpu-crit {
|
|
|
|
|
temperature = <0x186a0>;
|
|
|
|
|
hysteresis = <0x00>;
|
|
|
|
|
type = "critical";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
cooling-maps {
|
|
|
|
|
|
|
|
|
|
map0 {
|
|
|
|
|
trip = <0x37>;
|
|
|
|
|
cooling-device = <0x04 0xffffffff 0xffffffff 0x05 0xffffffff 0xffffffff 0x06 0xffffffff 0xffffffff 0x07 0xffffffff 0xffffffff>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpu-thermal {
|
|
|
|
|
polling-delay-passive = <0x00>;
|
|
|
|
|
polling-delay = <0x00>;
|
|
|
|
|
thermal-sensors = <0x36 0x01>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
aliases {
|
|
|
|
|
serial0 = "/soc/serial@5000000";
|
|
|
|
|
ethernet0 = "/soc/ethernet@5020000";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
chosen {
|
|
|
|
|
stdout-path = "serial0:115200n8";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
connector {
|
|
|
|
|
compatible = "hdmi-connector";
|
|
|
|
|
type = "a";
|
|
|
|
|
ddc-en-gpios = <0x14 0x07 0x02 0x00>;
|
|
|
|
|
|
|
|
|
|
port {
|
|
|
|
|
|
|
|
|
|
endpoint {
|
|
|
|
|
remote-endpoint = <0x38>;
|
|
|
|
|
phandle = <0x27>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ext_osc32k_clk {
|
|
|
|
|
#clock-cells = <0x00>;
|
|
|
|
|
compatible = "fixed-clock";
|
|
|
|
|
clock-frequency = <0x8000>;
|
|
|
|
|
clock-output-names = "ext_osc32k";
|
|
|
|
|
phandle = <0x2f>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
leds {
|
|
|
|
|
compatible = "gpio-leds";
|
|
|
|
|
|
|
|
|
|
power {
|
|
|
|
|
label = "orangepi:red:power";
|
|
|
|
|
gpios = <0x39 0x00 0x04 0x00>;
|
|
|
|
|
default-state = "on";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
status {
|
|
|
|
|
label = "orangepi:green:status";
|
|
|
|
|
gpios = <0x39 0x00 0x07 0x00>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
vcc5v {
|
|
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
regulator-name = "vcc-5v";
|
|
|
|
|
regulator-min-microvolt = <0x4c4b40>;
|
|
|
|
|
regulator-max-microvolt = <0x4c4b40>;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
phandle = <0x22>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gmac-3v3 {
|
|
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
regulator-name = "vcc-gmac-3v3";
|
|
|
|
|
regulator-min-microvolt = <0x325aa0>;
|
|
|
|
|
regulator-max-microvolt = <0x325aa0>;
|
|
|
|
|
startup-delay-us = <0x186a0>;
|
|
|
|
|
enable-active-high;
|
|
|
|
|
gpio = <0x14 0x03 0x06 0x00>;
|
|
|
|
|
vin-supply = <0x3a>;
|
|
|
|
|
phandle = <0x1f>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
__symbols__ {
|
|
|
|
|
cpu0 = "/cpus/cpu@0";
|
|
|
|
|
cpu1 = "/cpus/cpu@1";
|
|
|
|
|
cpu2 = "/cpus/cpu@2";
|
|
|
|
|
cpu3 = "/cpus/cpu@3";
|
|
|
|
|
de = "/display-engine";
|
|
|
|
|
osc24M = "/osc24M_clk";
|
|
|
|
|
display_clocks = "/soc/bus@1000000/clock@0";
|
|
|
|
|
mixer0 = "/soc/bus@1000000/mixer@100000";
|
|
|
|
|
mixer0_out = "/soc/bus@1000000/mixer@100000/ports/port@1";
|
|
|
|
|
mixer0_out_tcon_top_mixer0 = "/soc/bus@1000000/mixer@100000/ports/port@1/endpoint";
|
|
|
|
|
gpu = "/soc/gpu@1800000";
|
|
|
|
|
crypto = "/soc/crypto@1904000";
|
|
|
|
|
syscon = "/soc/syscon@3000000";
|
|
|
|
|
sram_c = "/soc/syscon@3000000/sram@28000";
|
|
|
|
|
de2_sram = "/soc/syscon@3000000/sram@28000/sram-section@0";
|
|
|
|
|
sram_c1 = "/soc/syscon@3000000/sram@1a00000";
|
|
|
|
|
ve_sram = "/soc/syscon@3000000/sram@1a00000/sram-section@0";
|
|
|
|
|
ccu = "/soc/clock@3001000";
|
|
|
|
|
dma = "/soc/dma-controller@3002000";
|
|
|
|
|
msgbox = "/soc/mailbox@3003000";
|
|
|
|
|
sid = "/soc/efuse@3006000";
|
|
|
|
|
ths_calibration = "/soc/efuse@3006000/thermal-sensor-calibration@14";
|
|
|
|
|
cpu_speed_grade = "/soc/efuse@3006000/cpu-speed-grade@1c";
|
|
|
|
|
watchdog = "/soc/watchdog@30090a0";
|
|
|
|
|
pwm = "/soc/pwm@300a000";
|
|
|
|
|
pio = "/soc/pinctrl@300b000";
|
|
|
|
|
ext_rgmii_pins = "/soc/pinctrl@300b000/rgmii-pins";
|
|
|
|
|
hdmi_pins = "/soc/pinctrl@300b000/hdmi-pins";
|
|
|
|
|
i2c0_pins = "/soc/pinctrl@300b000/i2c0-pins";
|
|
|
|
|
i2c1_pins = "/soc/pinctrl@300b000/i2c1-pins";
|
|
|
|
|
i2c2_pins = "/soc/pinctrl@300b000/i2c2-pins";
|
|
|
|
|
mmc0_pins = "/soc/pinctrl@300b000/mmc0-pins";
|
|
|
|
|
mmc1_pins = "/soc/pinctrl@300b000/mmc1-pins";
|
|
|
|
|
mmc2_pins = "/soc/pinctrl@300b000/mmc2-pins";
|
|
|
|
|
spi0_pins = "/soc/pinctrl@300b000/spi0-pins";
|
|
|
|
|
spi0_cs_pin = "/soc/pinctrl@300b000/spi0-cs-pin";
|
|
|
|
|
spi1_pins = "/soc/pinctrl@300b000/spi1-pins";
|
|
|
|
|
spi1_cs_pin = "/soc/pinctrl@300b000/spi1-cs-pin";
|
|
|
|
|
spdif_tx_pin = "/soc/pinctrl@300b000/spdif-tx-pin";
|
|
|
|
|
uart0_ph_pins = "/soc/pinctrl@300b000/uart0-ph-pins";
|
|
|
|
|
uart1_pins = "/soc/pinctrl@300b000/uart1-pins";
|
|
|
|
|
uart1_rts_cts_pins = "/soc/pinctrl@300b000/uart1-rts-cts-pins";
|
|
|
|
|
gic = "/soc/interrupt-controller@3021000";
|
|
|
|
|
iommu = "/soc/iommu@30f0000";
|
|
|
|
|
mmc0 = "/soc/mmc@4020000";
|
|
|
|
|
mmc1 = "/soc/mmc@4021000";
|
|
|
|
|
mmc2 = "/soc/mmc@4022000";
|
|
|
|
|
uart0 = "/soc/serial@5000000";
|
|
|
|
|
uart1 = "/soc/serial@5000400";
|
|
|
|
|
uart2 = "/soc/serial@5000800";
|
|
|
|
|
uart3 = "/soc/serial@5000c00";
|
|
|
|
|
i2c0 = "/soc/i2c@5002000";
|
|
|
|
|
i2c1 = "/soc/i2c@5002400";
|
|
|
|
|
i2c2 = "/soc/i2c@5002800";
|
|
|
|
|
spi0 = "/soc/spi@5010000";
|
|
|
|
|
spi1 = "/soc/spi@5011000";
|
|
|
|
|
emac = "/soc/ethernet@5020000";
|
|
|
|
|
mdio = "/soc/ethernet@5020000/mdio";
|
|
|
|
|
ext_rgmii_phy = "/soc/ethernet@5020000/mdio/ethernet-phy@1";
|
|
|
|
|
spdif = "/soc/spdif@5093000";
|
|
|
|
|
usb2otg = "/soc/usb@5100000";
|
|
|
|
|
usb2phy = "/soc/phy@5100400";
|
|
|
|
|
ehci0 = "/soc/usb@5101000";
|
|
|
|
|
ohci0 = "/soc/usb@5101400";
|
|
|
|
|
dwc3 = "/soc/dwc3@5200000";
|
|
|
|
|
usb3phy = "/soc/phy@5210000";
|
|
|
|
|
ehci3 = "/soc/usb@5311000";
|
|
|
|
|
ohci3 = "/soc/usb@5311400";
|
|
|
|
|
hdmi = "/soc/hdmi@6000000";
|
|
|
|
|
hdmi_in = "/soc/hdmi@6000000/ports/port@0";
|
|
|
|
|
hdmi_in_tcon_top = "/soc/hdmi@6000000/ports/port@0/endpoint";
|
|
|
|
|
hdmi_out = "/soc/hdmi@6000000/ports/port@1";
|
|
|
|
|
hdmi_out_con = "/soc/hdmi@6000000/ports/port@1/endpoint";
|
|
|
|
|
hdmi_phy = "/soc/hdmi-phy@6010000";
|
|
|
|
|
tcon_top = "/soc/tcon-top@6510000";
|
|
|
|
|
tcon_top_mixer0_in = "/soc/tcon-top@6510000/ports/port@0";
|
|
|
|
|
tcon_top_mixer0_in_mixer0 = "/soc/tcon-top@6510000/ports/port@0/endpoint@0";
|
|
|
|
|
tcon_top_mixer0_out = "/soc/tcon-top@6510000/ports/port@1";
|
|
|
|
|
tcon_top_mixer0_out_tcon_tv = "/soc/tcon-top@6510000/ports/port@1/endpoint@2";
|
|
|
|
|
tcon_top_hdmi_in = "/soc/tcon-top@6510000/ports/port@4";
|
|
|
|
|
tcon_top_hdmi_in_tcon_tv = "/soc/tcon-top@6510000/ports/port@4/endpoint@0";
|
|
|
|
|
tcon_top_hdmi_out = "/soc/tcon-top@6510000/ports/port@5";
|
|
|
|
|
tcon_top_hdmi_out_hdmi = "/soc/tcon-top@6510000/ports/port@5/endpoint";
|
|
|
|
|
tcon_tv = "/soc/lcd-controller@6515000";
|
|
|
|
|
tcon_tv_in = "/soc/lcd-controller@6515000/ports/port@0";
|
|
|
|
|
tcon_tv_in_tcon_top_mixer0 = "/soc/lcd-controller@6515000/ports/port@0/endpoint";
|
|
|
|
|
tcon_tv_out = "/soc/lcd-controller@6515000/ports/port@1";
|
|
|
|
|
tcon_tv_out_tcon_top = "/soc/lcd-controller@6515000/ports/port@1/endpoint@1";
|
|
|
|
|
rtc = "/soc/rtc@7000000";
|
|
|
|
|
r_ccu = "/soc/clock@7010000";
|
|
|
|
|
r_watchdog = "/soc/watchdog@7020400";
|
|
|
|
|
r_intc = "/soc/interrupt-controller@7021000";
|
|
|
|
|
r_pio = "/soc/pinctrl@7022000";
|
|
|
|
|
r_i2c_pins = "/soc/pinctrl@7022000/r-i2c-pins";
|
|
|
|
|
r_ir_rx_pin = "/soc/pinctrl@7022000/r-ir-rx-pin";
|
|
|
|
|
r_ir = "/soc/ir@7040000";
|
|
|
|
|
r_i2c = "/soc/i2c@7081400";
|
|
|
|
|
axp805 = "/soc/i2c@7081400/pmic@36";
|
|
|
|
|
reg_aldo1 = "/soc/i2c@7081400/pmic@36/regulators/aldo1";
|
|
|
|
|
reg_aldo2 = "/soc/i2c@7081400/pmic@36/regulators/aldo2";
|
|
|
|
|
reg_aldo3 = "/soc/i2c@7081400/pmic@36/regulators/aldo3";
|
|
|
|
|
reg_bldo1 = "/soc/i2c@7081400/pmic@36/regulators/bldo1";
|
|
|
|
|
reg_bldo2 = "/soc/i2c@7081400/pmic@36/regulators/bldo2";
|
|
|
|
|
reg_bldo3 = "/soc/i2c@7081400/pmic@36/regulators/bldo3";
|
|
|
|
|
reg_cldo1 = "/soc/i2c@7081400/pmic@36/regulators/cldo1";
|
|
|
|
|
reg_cldo2 = "/soc/i2c@7081400/pmic@36/regulators/cldo2";
|
|
|
|
|
reg_cldo3 = "/soc/i2c@7081400/pmic@36/regulators/cldo3";
|
|
|
|
|
reg_dcdca = "/soc/i2c@7081400/pmic@36/regulators/dcdca";
|
|
|
|
|
reg_dcdcc = "/soc/i2c@7081400/pmic@36/regulators/dcdcc";
|
|
|
|
|
reg_dcdcd = "/soc/i2c@7081400/pmic@36/regulators/dcdcd";
|
|
|
|
|
reg_dcdce = "/soc/i2c@7081400/pmic@36/regulators/dcdce";
|
|
|
|
|
ths = "/soc/thermal-sensor@5070400";
|
|
|
|
|
cpu_alert = "/thermal-zones/cpu-thermal/trips/cpu-alert";
|
|
|
|
|
hdmi_con_in = "/connector/port/endpoint";
|
|
|
|
|
ext_osc32k = "/ext_osc32k_clk";
|
|
|
|
|
reg_vcc5v = "/vcc5v";
|
|
|
|
|
reg_gmac_3v3 = "/gmac-3v3";
|
|
|
|
|
};
|
|
|
|
|
};
|
