2024-06-15 16:02:09 -03:00
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/dts-v1/;
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/ {
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interrupt-parent = <0x01>;
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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model = "Libre Computer Board ALL-H3-IT H5";
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2024-06-15 16:25:47 -03:00
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compatible = "libretech,all-h3-it-h5", "allwinner,sun50i-h5";
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2024-06-15 16:02:09 -03:00
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chosen {
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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ranges;
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stdout-path = "serial0:115200n8";
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framebuffer-hdmi {
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2024-06-15 16:25:47 -03:00
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compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
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2024-06-15 16:02:09 -03:00
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allwinner,pipeline = "mixer0-lcd0-hdmi";
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clocks = <0x02 0x06 0x03 0x66 0x03 0x6f>;
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status = "disabled";
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};
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framebuffer-tve {
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2024-06-15 16:25:47 -03:00
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compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
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2024-06-15 16:02:09 -03:00
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allwinner,pipeline = "mixer1-lcd1-tve";
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clocks = <0x02 0x07 0x03 0x67>;
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status = "disabled";
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};
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};
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clocks {
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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ranges;
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osc24M_clk {
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#clock-cells = <0x00>;
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compatible = "fixed-clock";
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clock-frequency = <0x16e3600>;
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clock-accuracy = <0xc350>;
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clock-output-names = "osc24M";
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phandle = <0x0e>;
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};
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osc32k_clk {
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#clock-cells = <0x00>;
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compatible = "fixed-clock";
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clock-frequency = <0x8000>;
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clock-accuracy = <0xc350>;
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clock-output-names = "ext_osc32k";
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phandle = <0x1e>;
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};
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};
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display-engine {
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compatible = "allwinner,sun8i-h3-display-engine";
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allwinner,pipelines = <0x04>;
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status = "okay";
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phandle = <0x2f>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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dma-ranges;
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ranges;
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clock@1000000 {
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reg = <0x1000000 0x10000>;
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clocks = <0x03 0x30 0x03 0x65>;
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2024-06-15 16:25:47 -03:00
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clock-names = "bus", "mod";
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2024-06-15 16:02:09 -03:00
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resets = <0x03 0x22>;
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#clock-cells = <0x01>;
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#reset-cells = <0x01>;
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compatible = "allwinner,sun50i-h5-de2-clk";
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phandle = <0x02>;
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};
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mixer@1100000 {
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compatible = "allwinner,sun8i-h3-de2-mixer-0";
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reg = <0x1100000 0x100000>;
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clocks = <0x02 0x00 0x02 0x06>;
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2024-06-15 16:25:47 -03:00
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clock-names = "bus", "mod";
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2024-06-15 16:02:09 -03:00
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resets = <0x02 0x00>;
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phandle = <0x04>;
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ports {
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#address-cells = <0x01>;
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#size-cells = <0x00>;
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port@1 {
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reg = <0x01>;
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phandle = <0x30>;
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endpoint {
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remote-endpoint = <0x05>;
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phandle = <0x06>;
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};
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};
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};
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};
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dma-controller@1c02000 {
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compatible = "allwinner,sun8i-h3-dma";
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reg = <0x1c02000 0x1000>;
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interrupts = <0x00 0x32 0x04>;
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clocks = <0x03 0x15>;
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resets = <0x03 0x06>;
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#dma-cells = <0x01>;
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phandle = <0x12>;
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};
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lcd-controller@1c0c000 {
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2024-06-15 16:25:47 -03:00
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compatible = "allwinner,sun8i-h3-tcon-tv", "allwinner,sun8i-a83t-tcon-tv";
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2024-06-15 16:02:09 -03:00
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reg = <0x1c0c000 0x1000>;
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interrupts = <0x00 0x56 0x04>;
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clocks = <0x03 0x2a 0x03 0x66>;
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2024-06-15 16:25:47 -03:00
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clock-names = "ahb", "tcon-ch1";
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2024-06-15 16:02:09 -03:00
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resets = <0x03 0x1b>;
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reset-names = "lcd";
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phandle = <0x31>;
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ports {
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#address-cells = <0x01>;
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#size-cells = <0x00>;
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port@0 {
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reg = <0x00>;
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phandle = <0x32>;
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endpoint {
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remote-endpoint = <0x06>;
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phandle = <0x05>;
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};
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};
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port@1 {
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#address-cells = <0x01>;
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#size-cells = <0x00>;
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reg = <0x01>;
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phandle = <0x33>;
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endpoint@1 {
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reg = <0x01>;
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remote-endpoint = <0x07>;
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phandle = <0x1c>;
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};
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};
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};
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};
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mmc@1c0f000 {
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reg = <0x1c0f000 0x1000>;
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pinctrl-names = "default";
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pinctrl-0 = <0x08>;
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resets = <0x03 0x07>;
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reset-names = "ahb";
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interrupts = <0x00 0x3c 0x04>;
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status = "okay";
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#address-cells = <0x01>;
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#size-cells = <0x00>;
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2024-06-15 16:25:47 -03:00
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compatible = "allwinner,sun50i-h5-mmc", "allwinner,sun50i-a64-mmc";
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2024-06-15 16:02:09 -03:00
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clocks = <0x03 0x16 0x03 0x47>;
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2024-06-15 16:25:47 -03:00
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clock-names = "ahb", "mmc";
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2024-06-15 16:02:09 -03:00
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vmmc-supply = <0x09>;
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bus-width = <0x04>;
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cd-gpios = <0x0a 0x05 0x06 0x01>;
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phandle = <0x34>;
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};
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mmc@1c10000 {
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reg = <0x1c10000 0x1000>;
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pinctrl-names = "default";
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pinctrl-0 = <0x0b>;
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resets = <0x03 0x08>;
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reset-names = "ahb";
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interrupts = <0x00 0x3d 0x04>;
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status = "disabled";
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#address-cells = <0x01>;
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#size-cells = <0x00>;
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2024-06-15 16:25:47 -03:00
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compatible = "allwinner,sun50i-h5-mmc", "allwinner,sun50i-a64-mmc";
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2024-06-15 16:02:09 -03:00
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clocks = <0x03 0x17 0x03 0x4a>;
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2024-06-15 16:25:47 -03:00
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clock-names = "ahb", "mmc";
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2024-06-15 16:02:09 -03:00
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phandle = <0x35>;
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};
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mmc@1c11000 {
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reg = <0x1c11000 0x1000>;
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resets = <0x03 0x09>;
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reset-names = "ahb";
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interrupts = <0x00 0x3e 0x04>;
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status = "disabled";
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#address-cells = <0x01>;
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#size-cells = <0x00>;
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2024-06-15 16:25:47 -03:00
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compatible = "allwinner,sun50i-h5-emmc", "allwinner,sun50i-a64-emmc";
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2024-06-15 16:02:09 -03:00
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clocks = <0x03 0x18 0x03 0x4d>;
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2024-06-15 16:25:47 -03:00
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clock-names = "ahb", "mmc";
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2024-06-15 16:02:09 -03:00
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phandle = <0x36>;
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};
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eeprom@1c14000 {
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reg = <0x1c14000 0x400>;
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#address-cells = <0x01>;
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#size-cells = <0x01>;
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compatible = "allwinner,sun50i-h5-sid";
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phandle = <0x37>;
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thermal-sensor-calibration@34 {
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reg = <0x34 0x04>;
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phandle = <0x24>;
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};
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};
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mailbox@1c17000 {
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2024-06-15 16:25:47 -03:00
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compatible = "allwinner,sun8i-h3-msgbox", "allwinner,sun6i-a31-msgbox";
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2024-06-15 16:02:09 -03:00
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reg = <0x1c17000 0x1000>;
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clocks = <0x03 0x32>;
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resets = <0x03 0x24>;
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interrupts = <0x00 0x31 0x04>;
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#mbox-cells = <0x01>;
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phandle = <0x38>;
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};
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usb@1c19000 {
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compatible = "allwinner,sun8i-h3-musb";
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reg = <0x1c19000 0x400>;
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clocks = <0x03 0x20>;
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resets = <0x03 0x11>;
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interrupts = <0x00 0x47 0x04>;
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interrupt-names = "mc";
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phys = <0x0c 0x00>;
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phy-names = "usb";
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extcon = <0x0c 0x00>;
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dr_mode = "peripheral";
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status = "okay";
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phandle = <0x39>;
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};
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phy@1c19400 {
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compatible = "allwinner,sun8i-h3-usb-phy";
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reg = <0x1c19400 0x2c 0x1c1a800 0x04 0x1c1b800 0x04 0x1c1c800 0x04 0x1c1d800 0x04>;
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2024-06-15 16:25:47 -03:00
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reg-names = "phy_ctrl", "pmu0", "pmu1", "pmu2", "pmu3";
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2024-06-15 16:02:09 -03:00
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clocks = <0x03 0x58 0x03 0x59 0x03 0x5a 0x03 0x5b>;
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2024-06-15 16:25:47 -03:00
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clock-names = "usb0_phy", "usb1_phy", "usb2_phy", "usb3_phy";
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2024-06-15 16:02:09 -03:00
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resets = <0x03 0x00 0x03 0x01 0x03 0x02 0x03 0x03>;
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2024-06-15 16:25:47 -03:00
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reset-names = "usb0_reset", "usb1_reset", "usb2_reset", "usb3_reset";
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2024-06-15 16:02:09 -03:00
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status = "okay";
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#phy-cells = <0x01>;
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usb1_vbus-supply = <0x0d>;
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phandle = <0x0c>;
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};
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usb@1c1a000 {
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2024-06-15 16:25:47 -03:00
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compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
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2024-06-15 16:02:09 -03:00
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reg = <0x1c1a000 0x100>;
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interrupts = <0x00 0x48 0x04>;
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clocks = <0x03 0x21 0x03 0x25>;
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resets = <0x03 0x12 0x03 0x16>;
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status = "disabled";
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phandle = <0x3a>;
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};
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usb@1c1a400 {
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2024-06-15 16:25:47 -03:00
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compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
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2024-06-15 16:02:09 -03:00
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reg = <0x1c1a400 0x100>;
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interrupts = <0x00 0x49 0x04>;
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clocks = <0x03 0x21 0x03 0x25 0x03 0x5c>;
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resets = <0x03 0x12 0x03 0x16>;
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status = "disabled";
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phandle = <0x3b>;
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};
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usb@1c1b000 {
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2024-06-15 16:25:47 -03:00
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compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
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2024-06-15 16:02:09 -03:00
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reg = <0x1c1b000 0x100>;
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interrupts = <0x00 0x4a 0x04>;
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clocks = <0x03 0x22 0x03 0x26>;
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resets = <0x03 0x13 0x03 0x17>;
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phys = <0x0c 0x01>;
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phy-names = "usb";
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status = "okay";
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phandle = <0x3c>;
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};
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usb@1c1b400 {
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2024-06-15 16:25:47 -03:00
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compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
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2024-06-15 16:02:09 -03:00
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reg = <0x1c1b400 0x100>;
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interrupts = <0x00 0x4b 0x04>;
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clocks = <0x03 0x22 0x03 0x26 0x03 0x5d>;
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resets = <0x03 0x13 0x03 0x17>;
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phys = <0x0c 0x01>;
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phy-names = "usb";
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status = "disabled";
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phandle = <0x3d>;
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};
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usb@1c1c000 {
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2024-06-15 16:25:47 -03:00
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compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
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2024-06-15 16:02:09 -03:00
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reg = <0x1c1c000 0x100>;
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interrupts = <0x00 0x4c 0x04>;
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clocks = <0x03 0x23 0x03 0x27>;
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resets = <0x03 0x14 0x03 0x18>;
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phys = <0x0c 0x02>;
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phy-names = "usb";
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status = "disabled";
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phandle = <0x3e>;
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};
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usb@1c1c400 {
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2024-06-15 16:25:47 -03:00
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compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
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2024-06-15 16:02:09 -03:00
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reg = <0x1c1c400 0x100>;
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interrupts = <0x00 0x4d 0x04>;
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clocks = <0x03 0x23 0x03 0x27 0x03 0x5e>;
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resets = <0x03 0x14 0x03 0x18>;
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phys = <0x0c 0x02>;
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phy-names = "usb";
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|
status = "disabled";
|
|
|
|
phandle = <0x3f>;
|
|
|
|
};
|
|
|
|
|
|
|
|
usb@1c1d000 {
|
2024-06-15 16:25:47 -03:00
|
|
|
compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
|
2024-06-15 16:02:09 -03:00
|
|
|
reg = <0x1c1d000 0x100>;
|
|
|
|
interrupts = <0x00 0x4e 0x04>;
|
|
|
|
clocks = <0x03 0x24 0x03 0x28>;
|
|
|
|
resets = <0x03 0x15 0x03 0x19>;
|
|
|
|
phys = <0x0c 0x03>;
|
|
|
|
phy-names = "usb";
|
|
|
|
status = "disabled";
|
|
|
|
phandle = <0x40>;
|
|
|
|
};
|
|
|
|
|
|
|
|
usb@1c1d400 {
|
2024-06-15 16:25:47 -03:00
|
|
|
compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
|
2024-06-15 16:02:09 -03:00
|
|
|
reg = <0x1c1d400 0x100>;
|
|
|
|
interrupts = <0x00 0x4f 0x04>;
|
|
|
|
clocks = <0x03 0x24 0x03 0x28 0x03 0x5f>;
|
|
|
|
resets = <0x03 0x15 0x03 0x19>;
|
|
|
|
phys = <0x0c 0x03>;
|
|
|
|
phy-names = "usb";
|
|
|
|
status = "disabled";
|
|
|
|
phandle = <0x41>;
|
|
|
|
};
|
|
|
|
|
|
|
|
clock@1c20000 {
|
|
|
|
reg = <0x1c20000 0x400>;
|
|
|
|
clocks = <0x0e 0x0f 0x00>;
|
2024-06-15 16:25:47 -03:00
|
|
|
clock-names = "hosc", "losc";
|
2024-06-15 16:02:09 -03:00
|
|
|
#clock-cells = <0x01>;
|
|
|
|
#reset-cells = <0x01>;
|
|
|
|
compatible = "allwinner,sun50i-h5-ccu";
|
|
|
|
phandle = <0x03>;
|
|
|
|
};
|
|
|
|
|
|
|
|
pinctrl@1c20800 {
|
|
|
|
reg = <0x1c20800 0x400>;
|
|
|
|
interrupts = <0x00 0x0b 0x04 0x00 0x11 0x04 0x00 0x17 0x04>;
|
|
|
|
clocks = <0x03 0x36 0x0e 0x0f 0x00>;
|
2024-06-15 16:25:47 -03:00
|
|
|
clock-names = "apb", "hosc", "losc";
|
2024-06-15 16:02:09 -03:00
|
|
|
gpio-controller;
|
|
|
|
#gpio-cells = <0x03>;
|
|
|
|
interrupt-controller;
|
|
|
|
#interrupt-cells = <0x03>;
|
|
|
|
compatible = "allwinner,sun50i-h5-pinctrl";
|
|
|
|
vcc-pa-supply = <0x09>;
|
|
|
|
vcc-pc-supply = <0x09>;
|
|
|
|
vcc-pd-supply = <0x09>;
|
|
|
|
vcc-pe-supply = <0x09>;
|
|
|
|
vcc-pf-supply = <0x09>;
|
|
|
|
vcc-pg-supply = <0x09>;
|
|
|
|
phandle = <0x0a>;
|
|
|
|
|
|
|
|
csi-pins {
|
2024-06-15 16:25:47 -03:00
|
|
|
pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7", "PE8", "PE9", "PE10", "PE11";
|
2024-06-15 16:02:09 -03:00
|
|
|
function = "csi";
|
|
|
|
phandle = <0x1a>;
|
|
|
|
};
|
|
|
|
|
|
|
|
emac-rgmii-pins {
|
2024-06-15 16:25:47 -03:00
|
|
|
pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD7", "PD8", "PD9", "PD10", "PD12", "PD13", "PD15", "PD16", "PD17";
|
2024-06-15 16:02:09 -03:00
|
|
|
function = "emac";
|
|
|
|
drive-strength = <0x28>;
|
|
|
|
phandle = <0x42>;
|
|
|
|
};
|
|
|
|
|
|
|
|
i2c0-pins {
|
2024-06-15 16:25:47 -03:00
|
|
|
pins = "PA11", "PA12";
|
2024-06-15 16:02:09 -03:00
|
|
|
function = "i2c0";
|
|
|
|
phandle = <0x17>;
|
|
|
|
};
|
|
|
|
|
|
|
|
i2c1-pins {
|
2024-06-15 16:25:47 -03:00
|
|
|
pins = "PA18", "PA19";
|
2024-06-15 16:02:09 -03:00
|
|
|
function = "i2c1";
|
|
|
|
phandle = <0x18>;
|
|
|
|
};
|
|
|
|
|
|
|
|
i2c2-pins {
|
2024-06-15 16:25:47 -03:00
|
|
|
pins = "PE12", "PE13";
|
2024-06-15 16:02:09 -03:00
|
|
|
function = "i2c2";
|
|
|
|
phandle = <0x19>;
|
|
|
|
};
|
|
|
|
|
|
|
|
mmc0-pins {
|
2024-06-15 16:25:47 -03:00
|
|
|
pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
|
2024-06-15 16:02:09 -03:00
|
|
|
function = "mmc0";
|
|
|
|
drive-strength = <0x1e>;
|
|
|
|
bias-pull-up;
|
|
|
|
phandle = <0x08>;
|
|
|
|
};
|
|
|
|
|
|
|
|
mmc1-pins {
|
2024-06-15 16:25:47 -03:00
|
|
|
pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
|
2024-06-15 16:02:09 -03:00
|
|
|
function = "mmc1";
|
|
|
|
drive-strength = <0x1e>;
|
|
|
|
bias-pull-up;
|
|
|
|
phandle = <0x0b>;
|
|
|
|
};
|
|
|
|
|
|
|
|
mmc2-8bit-pins {
|
2024-06-15 16:25:47 -03:00
|
|
|
pins = "PC5", "PC6", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14", "PC15", "PC16";
|
2024-06-15 16:02:09 -03:00
|
|
|
function = "mmc2";
|
|
|
|
drive-strength = <0x1e>;
|
|
|
|
bias-pull-up;
|
|
|
|
phandle = <0x43>;
|
|
|
|
};
|
|
|
|
|
|
|
|
spdif-tx-pin {
|
|
|
|
pins = "PA17";
|
|
|
|
function = "spdif";
|
|
|
|
phandle = <0x44>;
|
|
|
|
};
|
|
|
|
|
|
|
|
spi0-pins {
|
2024-06-15 16:25:47 -03:00
|
|
|
pins = "PC0", "PC1", "PC2", "PC3";
|
2024-06-15 16:02:09 -03:00
|
|
|
function = "spi0";
|
|
|
|
phandle = <0x13>;
|
|
|
|
};
|
|
|
|
|
|
|
|
spi1-pins {
|
2024-06-15 16:25:47 -03:00
|
|
|
pins = "PA15", "PA16", "PA14", "PA13";
|
2024-06-15 16:02:09 -03:00
|
|
|
function = "spi1";
|
|
|
|
phandle = <0x14>;
|
|
|
|
};
|
|
|
|
|
|
|
|
uart0-pa-pins {
|
2024-06-15 16:25:47 -03:00
|
|
|
pins = "PA4", "PA5";
|
2024-06-15 16:02:09 -03:00
|
|
|
function = "uart0";
|
|
|
|
phandle = <0x16>;
|
|
|
|
};
|
|
|
|
|
|
|
|
uart1-pins {
|
2024-06-15 16:25:47 -03:00
|
|
|
pins = "PG6", "PG7";
|
2024-06-15 16:02:09 -03:00
|
|
|
function = "uart1";
|
|
|
|
phandle = <0x45>;
|
|
|
|
};
|
|
|
|
|
|
|
|
uart1-rts-cts-pins {
|
2024-06-15 16:25:47 -03:00
|
|
|
pins = "PG8", "PG9";
|
2024-06-15 16:02:09 -03:00
|
|
|
function = "uart1";
|
|
|
|
phandle = <0x46>;
|
|
|
|
};
|
|
|
|
|
|
|
|
uart2-pins {
|
2024-06-15 16:25:47 -03:00
|
|
|
pins = "PA0", "PA1";
|
2024-06-15 16:02:09 -03:00
|
|
|
function = "uart2";
|
|
|
|
phandle = <0x47>;
|
|
|
|
};
|
|
|
|
|
|
|
|
uart2-rts-cts-pins {
|
2024-06-15 16:25:47 -03:00
|
|
|
pins = "PA2", "PA3";
|
2024-06-15 16:02:09 -03:00
|
|
|
function = "uart2";
|
|
|
|
phandle = <0x48>;
|
|
|
|
};
|
|
|
|
|
|
|
|
uart3-pins {
|
2024-06-15 16:25:47 -03:00
|
|
|
pins = "PA13", "PA14";
|
2024-06-15 16:02:09 -03:00
|
|
|
function = "uart3";
|
|
|
|
phandle = <0x49>;
|
|
|
|
};
|
|
|
|
|
|
|
|
uart3-rts-cts-pins {
|
2024-06-15 16:25:47 -03:00
|
|
|
pins = "PA15", "PA16";
|
2024-06-15 16:02:09 -03:00
|
|
|
function = "uart3";
|
|
|
|
phandle = <0x4a>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
timer@1c20c00 {
|
|
|
|
compatible = "allwinner,sun8i-a23-timer";
|
|
|
|
reg = <0x1c20c00 0xa0>;
|
|
|
|
interrupts = <0x00 0x12 0x04 0x00 0x13 0x04>;
|
|
|
|
clocks = <0x0e>;
|
|
|
|
};
|
|
|
|
|
|
|
|
ethernet@1c30000 {
|
|
|
|
compatible = "allwinner,sun8i-h3-emac";
|
|
|
|
syscon = <0x10>;
|
|
|
|
reg = <0x1c30000 0x10000>;
|
|
|
|
interrupts = <0x00 0x52 0x04>;
|
|
|
|
interrupt-names = "macirq";
|
|
|
|
resets = <0x03 0x0c>;
|
|
|
|
reset-names = "stmmaceth";
|
|
|
|
clocks = <0x03 0x1b>;
|
|
|
|
clock-names = "stmmaceth";
|
|
|
|
status = "disabled";
|
|
|
|
phandle = <0x4b>;
|
|
|
|
|
|
|
|
mdio {
|
|
|
|
#address-cells = <0x01>;
|
|
|
|
#size-cells = <0x00>;
|
|
|
|
compatible = "snps,dwmac-mdio";
|
|
|
|
phandle = <0x11>;
|
|
|
|
};
|
|
|
|
|
|
|
|
mdio-mux {
|
|
|
|
compatible = "allwinner,sun8i-h3-mdio-mux";
|
|
|
|
#address-cells = <0x01>;
|
|
|
|
#size-cells = <0x00>;
|
|
|
|
mdio-parent-bus = <0x11>;
|
|
|
|
|
|
|
|
mdio@1 {
|
|
|
|
compatible = "allwinner,sun8i-h3-mdio-internal";
|
|
|
|
reg = <0x01>;
|
|
|
|
#address-cells = <0x01>;
|
|
|
|
#size-cells = <0x00>;
|
|
|
|
phandle = <0x4c>;
|
|
|
|
|
|
|
|
ethernet-phy@1 {
|
|
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
|
|
reg = <0x01>;
|
|
|
|
clocks = <0x03 0x43>;
|
|
|
|
resets = <0x03 0x27>;
|
|
|
|
phandle = <0x4d>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
mdio@2 {
|
|
|
|
reg = <0x02>;
|
|
|
|
#address-cells = <0x01>;
|
|
|
|
#size-cells = <0x00>;
|
|
|
|
phandle = <0x4e>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
dram-controller@1c62000 {
|
|
|
|
compatible = "allwinner,sun8i-h3-mbus";
|
|
|
|
reg = <0x1c62000 0x1000>;
|
|
|
|
clocks = <0x03 0x71>;
|
|
|
|
#address-cells = <0x01>;
|
|
|
|
#size-cells = <0x01>;
|
|
|
|
dma-ranges = <0x00 0x40000000 0xc0000000>;
|
|
|
|
#interconnect-cells = <0x01>;
|
|
|
|
phandle = <0x4f>;
|
|
|
|
};
|
|
|
|
|
|
|
|
spi@1c68000 {
|
|
|
|
compatible = "allwinner,sun8i-h3-spi";
|
|
|
|
reg = <0x1c68000 0x1000>;
|
|
|
|
interrupts = <0x00 0x41 0x04>;
|
|
|
|
clocks = <0x03 0x1e 0x03 0x52>;
|
2024-06-15 16:25:47 -03:00
|
|
|
clock-names = "ahb", "mod";
|
2024-06-15 16:02:09 -03:00
|
|
|
dmas = <0x12 0x17 0x12 0x17>;
|
2024-06-15 16:25:47 -03:00
|
|
|
dma-names = "rx", "tx";
|
2024-06-15 16:02:09 -03:00
|
|
|
pinctrl-names = "default";
|
|
|
|
pinctrl-0 = <0x13>;
|
|
|
|
resets = <0x03 0x0f>;
|
|
|
|
status = "okay";
|
|
|
|
#address-cells = <0x01>;
|
|
|
|
#size-cells = <0x00>;
|
|
|
|
phandle = <0x50>;
|
|
|
|
|
|
|
|
spiflash@0 {
|
|
|
|
compatible = "jedec,spi-nor";
|
|
|
|
reg = <0x00>;
|
|
|
|
spi-max-frequency = <0x2faf080>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
spi@1c69000 {
|
|
|
|
compatible = "allwinner,sun8i-h3-spi";
|
|
|
|
reg = <0x1c69000 0x1000>;
|
|
|
|
interrupts = <0x00 0x42 0x04>;
|
|
|
|
clocks = <0x03 0x1f 0x03 0x53>;
|
2024-06-15 16:25:47 -03:00
|
|
|
clock-names = "ahb", "mod";
|
2024-06-15 16:02:09 -03:00
|
|
|
dmas = <0x12 0x18 0x12 0x18>;
|
2024-06-15 16:25:47 -03:00
|
|
|
dma-names = "rx", "tx";
|
2024-06-15 16:02:09 -03:00
|
|
|
pinctrl-names = "default";
|
|
|
|
pinctrl-0 = <0x14>;
|
|
|
|
resets = <0x03 0x10>;
|
|
|
|
status = "disabled";
|
|
|
|
#address-cells = <0x01>;
|
|
|
|
#size-cells = <0x00>;
|
|
|
|
phandle = <0x51>;
|
|
|
|
};
|
|
|
|
|
|
|
|
watchdog@1c20ca0 {
|
|
|
|
compatible = "allwinner,sun6i-a31-wdt";
|
|
|
|
reg = <0x1c20ca0 0x20>;
|
|
|
|
interrupts = <0x00 0x19 0x04>;
|
|
|
|
clocks = <0x0e>;
|
|
|
|
phandle = <0x52>;
|
|
|
|
};
|
|
|
|
|
|
|
|
spdif@1c21000 {
|
|
|
|
#sound-dai-cells = <0x00>;
|
|
|
|
compatible = "allwinner,sun8i-h3-spdif";
|
|
|
|
reg = <0x1c21000 0x400>;
|
|
|
|
interrupts = <0x00 0x0c 0x04>;
|
|
|
|
clocks = <0x03 0x35 0x03 0x57>;
|
|
|
|
resets = <0x03 0x29>;
|
2024-06-15 16:25:47 -03:00
|
|
|
clock-names = "apb", "spdif";
|
2024-06-15 16:02:09 -03:00
|
|
|
dmas = <0x12 0x02>;
|
|
|
|
dma-names = "tx";
|
|
|
|
status = "disabled";
|
|
|
|
phandle = <0x53>;
|
|
|
|
};
|
|
|
|
|
|
|
|
pwm@1c21400 {
|
|
|
|
compatible = "allwinner,sun8i-h3-pwm";
|
|
|
|
reg = <0x1c21400 0x08>;
|
|
|
|
clocks = <0x0e>;
|
|
|
|
#pwm-cells = <0x03>;
|
|
|
|
status = "disabled";
|
|
|
|
phandle = <0x54>;
|
|
|
|
};
|
|
|
|
|
|
|
|
i2s@1c22000 {
|
|
|
|
#sound-dai-cells = <0x00>;
|
|
|
|
compatible = "allwinner,sun8i-h3-i2s";
|
|
|
|
reg = <0x1c22000 0x400>;
|
|
|
|
interrupts = <0x00 0x0d 0x04>;
|
|
|
|
clocks = <0x03 0x38 0x03 0x54>;
|
2024-06-15 16:25:47 -03:00
|
|
|
clock-names = "apb", "mod";
|
2024-06-15 16:02:09 -03:00
|
|
|
dmas = <0x12 0x03 0x12 0x03>;
|
|
|
|
resets = <0x03 0x2b>;
|
2024-06-15 16:25:47 -03:00
|
|
|
dma-names = "rx", "tx";
|
2024-06-15 16:02:09 -03:00
|
|
|
status = "disabled";
|
|
|
|
phandle = <0x55>;
|
|
|
|
};
|
|
|
|
|
|
|
|
i2s@1c22400 {
|
|
|
|
#sound-dai-cells = <0x00>;
|
|
|
|
compatible = "allwinner,sun8i-h3-i2s";
|
|
|
|
reg = <0x1c22400 0x400>;
|
|
|
|
interrupts = <0x00 0x0e 0x04>;
|
|
|
|
clocks = <0x03 0x39 0x03 0x55>;
|
2024-06-15 16:25:47 -03:00
|
|
|
clock-names = "apb", "mod";
|
2024-06-15 16:02:09 -03:00
|
|
|
dmas = <0x12 0x04 0x12 0x04>;
|
|
|
|
resets = <0x03 0x2c>;
|
2024-06-15 16:25:47 -03:00
|
|
|
dma-names = "rx", "tx";
|
2024-06-15 16:02:09 -03:00
|
|
|
status = "disabled";
|
|
|
|
phandle = <0x56>;
|
|
|
|
};
|
|
|
|
|
|
|
|
codec@1c22c00 {
|
|
|
|
#sound-dai-cells = <0x00>;
|
|
|
|
compatible = "allwinner,sun8i-h3-codec";
|
|
|
|
reg = <0x1c22c00 0x400>;
|
|
|
|
interrupts = <0x00 0x1d 0x04>;
|
|
|
|
clocks = <0x03 0x34 0x03 0x6d>;
|
2024-06-15 16:25:47 -03:00
|
|
|
clock-names = "apb", "codec";
|
2024-06-15 16:02:09 -03:00
|
|
|
resets = <0x03 0x28>;
|
|
|
|
dmas = <0x12 0x0f 0x12 0x0f>;
|
2024-06-15 16:25:47 -03:00
|
|
|
dma-names = "rx", "tx";
|
2024-06-15 16:02:09 -03:00
|
|
|
allwinner,codec-analog-controls = <0x15>;
|
|
|
|
status = "disabled";
|
|
|
|
phandle = <0x57>;
|
|
|
|
};
|
|
|
|
|
|
|
|
serial@1c28000 {
|
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
|
reg = <0x1c28000 0x400>;
|
|
|
|
interrupts = <0x00 0x00 0x04>;
|
|
|
|
reg-shift = <0x02>;
|
|
|
|
reg-io-width = <0x04>;
|
|
|
|
clocks = <0x03 0x3e>;
|
|
|
|
resets = <0x03 0x31>;
|
|
|
|
dmas = <0x12 0x06 0x12 0x06>;
|
2024-06-15 16:25:47 -03:00
|
|
|
dma-names = "rx", "tx";
|
2024-06-15 16:02:09 -03:00
|
|
|
status = "okay";
|
|
|
|
pinctrl-names = "default";
|
|
|
|
pinctrl-0 = <0x16>;
|
|
|
|
phandle = <0x58>;
|
|
|
|
};
|
|
|
|
|
|
|
|
serial@1c28400 {
|
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
|
reg = <0x1c28400 0x400>;
|
|
|
|
interrupts = <0x00 0x01 0x04>;
|
|
|
|
reg-shift = <0x02>;
|
|
|
|
reg-io-width = <0x04>;
|
|
|
|
clocks = <0x03 0x3f>;
|
|
|
|
resets = <0x03 0x32>;
|
|
|
|
dmas = <0x12 0x07 0x12 0x07>;
|
2024-06-15 16:25:47 -03:00
|
|
|
dma-names = "rx", "tx";
|
2024-06-15 16:02:09 -03:00
|
|
|
status = "disabled";
|
|
|
|
phandle = <0x59>;
|
|
|
|
};
|
|
|
|
|
|
|
|
serial@1c28800 {
|
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
|
reg = <0x1c28800 0x400>;
|
|
|
|
interrupts = <0x00 0x02 0x04>;
|
|
|
|
reg-shift = <0x02>;
|
|
|
|
reg-io-width = <0x04>;
|
|
|
|
clocks = <0x03 0x40>;
|
|
|
|
resets = <0x03 0x33>;
|
|
|
|
dmas = <0x12 0x08 0x12 0x08>;
|
2024-06-15 16:25:47 -03:00
|
|
|
dma-names = "rx", "tx";
|
2024-06-15 16:02:09 -03:00
|
|
|
status = "disabled";
|
|
|
|
phandle = <0x5a>;
|
|
|
|
};
|
|
|
|
|
|
|
|
serial@1c28c00 {
|
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
|
reg = <0x1c28c00 0x400>;
|
|
|
|
interrupts = <0x00 0x03 0x04>;
|
|
|
|
reg-shift = <0x02>;
|
|
|
|
reg-io-width = <0x04>;
|
|
|
|
clocks = <0x03 0x41>;
|
|
|
|
resets = <0x03 0x34>;
|
|
|
|
dmas = <0x12 0x09 0x12 0x09>;
|
2024-06-15 16:25:47 -03:00
|
|
|
dma-names = "rx", "tx";
|
2024-06-15 16:02:09 -03:00
|
|
|
status = "disabled";
|
|
|
|
phandle = <0x5b>;
|
|
|
|
};
|
|
|
|
|
|
|
|
i2c@1c2ac00 {
|
|
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
|
|
reg = <0x1c2ac00 0x400>;
|
|
|
|
interrupts = <0x00 0x06 0x04>;
|
|
|
|
clocks = <0x03 0x3b>;
|
|
|
|
resets = <0x03 0x2e>;
|
|
|
|
pinctrl-names = "default";
|
|
|
|
pinctrl-0 = <0x17>;
|
|
|
|
status = "disabled";
|
|
|
|
#address-cells = <0x01>;
|
|
|
|
#size-cells = <0x00>;
|
|
|
|
phandle = <0x5c>;
|
|
|
|
};
|
|
|
|
|
|
|
|
i2c@1c2b000 {
|
|
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
|
|
reg = <0x1c2b000 0x400>;
|
|
|
|
interrupts = <0x00 0x07 0x04>;
|
|
|
|
clocks = <0x03 0x3c>;
|
|
|
|
resets = <0x03 0x2f>;
|
|
|
|
pinctrl-names = "default";
|
|
|
|
pinctrl-0 = <0x18>;
|
|
|
|
status = "disabled";
|
|
|
|
#address-cells = <0x01>;
|
|
|
|
#size-cells = <0x00>;
|
|
|
|
phandle = <0x5d>;
|
|
|
|
};
|
|
|
|
|
|
|
|
i2c@1c2b400 {
|
|
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
|
|
reg = <0x1c2b400 0x400>;
|
|
|
|
interrupts = <0x00 0x08 0x04>;
|
|
|
|
clocks = <0x03 0x3d>;
|
|
|
|
resets = <0x03 0x30>;
|
|
|
|
pinctrl-names = "default";
|
|
|
|
pinctrl-0 = <0x19>;
|
|
|
|
status = "disabled";
|
|
|
|
#address-cells = <0x01>;
|
|
|
|
#size-cells = <0x00>;
|
|
|
|
phandle = <0x5e>;
|
|
|
|
};
|
|
|
|
|
|
|
|
interrupt-controller@1c81000 {
|
|
|
|
compatible = "arm,gic-400";
|
|
|
|
reg = <0x1c81000 0x1000 0x1c82000 0x2000 0x1c84000 0x2000 0x1c86000 0x2000>;
|
|
|
|
interrupt-controller;
|
|
|
|
#interrupt-cells = <0x03>;
|
|
|
|
interrupts = <0x01 0x09 0xf04>;
|
|
|
|
phandle = <0x01>;
|
|
|
|
};
|
|
|
|
|
|
|
|
camera@1cb0000 {
|
|
|
|
compatible = "allwinner,sun8i-h3-csi";
|
|
|
|
reg = <0x1cb0000 0x1000>;
|
|
|
|
interrupts = <0x00 0x54 0x04>;
|
|
|
|
clocks = <0x03 0x2d 0x03 0x6a 0x03 0x62>;
|
2024-06-15 16:25:47 -03:00
|
|
|
clock-names = "bus", "mod", "ram";
|
2024-06-15 16:02:09 -03:00
|
|
|
resets = <0x03 0x1e>;
|
|
|
|
pinctrl-names = "default";
|
|
|
|
pinctrl-0 = <0x1a>;
|
|
|
|
status = "disabled";
|
|
|
|
phandle = <0x5f>;
|
|
|
|
};
|
|
|
|
|
|
|
|
hdmi@1ee0000 {
|
2024-06-15 16:25:47 -03:00
|
|
|
compatible = "allwinner,sun8i-h3-dw-hdmi", "allwinner,sun8i-a83t-dw-hdmi";
|
2024-06-15 16:02:09 -03:00
|
|
|
reg = <0x1ee0000 0x10000>;
|
|
|
|
reg-io-width = <0x01>;
|
|
|
|
interrupts = <0x00 0x58 0x04>;
|
|
|
|
clocks = <0x03 0x2f 0x03 0x70 0x03 0x6f>;
|
2024-06-15 16:25:47 -03:00
|
|
|
clock-names = "iahb", "isfr", "tmds";
|
2024-06-15 16:02:09 -03:00
|
|
|
resets = <0x03 0x21>;
|
|
|
|
reset-names = "ctrl";
|
|
|
|
phys = <0x1b>;
|
|
|
|
phy-names = "phy";
|
|
|
|
status = "okay";
|
|
|
|
phandle = <0x60>;
|
|
|
|
|
|
|
|
ports {
|
|
|
|
#address-cells = <0x01>;
|
|
|
|
#size-cells = <0x00>;
|
|
|
|
|
|
|
|
port@0 {
|
|
|
|
reg = <0x00>;
|
|
|
|
phandle = <0x61>;
|
|
|
|
|
|
|
|
endpoint {
|
|
|
|
remote-endpoint = <0x1c>;
|
|
|
|
phandle = <0x07>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
port@1 {
|
|
|
|
reg = <0x01>;
|
|
|
|
phandle = <0x62>;
|
|
|
|
|
|
|
|
endpoint {
|
|
|
|
remote-endpoint = <0x1d>;
|
|
|
|
phandle = <0x2c>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
hdmi-phy@1ef0000 {
|
|
|
|
compatible = "allwinner,sun8i-h3-hdmi-phy";
|
|
|
|
reg = <0x1ef0000 0x10000>;
|
|
|
|
clocks = <0x03 0x2f 0x03 0x70 0x03 0x06>;
|
2024-06-15 16:25:47 -03:00
|
|
|
clock-names = "bus", "mod", "pll-0";
|
2024-06-15 16:02:09 -03:00
|
|
|
resets = <0x03 0x20>;
|
|
|
|
reset-names = "phy";
|
|
|
|
#phy-cells = <0x00>;
|
|
|
|
phandle = <0x1b>;
|
|
|
|
};
|
|
|
|
|
|
|
|
rtc@1f00000 {
|
|
|
|
reg = <0x1f00000 0x400>;
|
|
|
|
interrupts = <0x00 0x28 0x04 0x00 0x29 0x04>;
|
2024-06-15 16:25:47 -03:00
|
|
|
clock-output-names = "osc32k", "osc32k-out", "iosc";
|
2024-06-15 16:02:09 -03:00
|
|
|
clocks = <0x1e>;
|
|
|
|
#clock-cells = <0x01>;
|
|
|
|
compatible = "allwinner,sun50i-h5-rtc";
|
|
|
|
phandle = <0x0f>;
|
|
|
|
};
|
|
|
|
|
|
|
|
clock@1f01400 {
|
|
|
|
compatible = "allwinner,sun8i-h3-r-ccu";
|
|
|
|
reg = <0x1f01400 0x100>;
|
|
|
|
clocks = <0x0e 0x0f 0x00 0x0f 0x02 0x03 0x09>;
|
2024-06-15 16:25:47 -03:00
|
|
|
clock-names = "hosc", "losc", "iosc", "pll-periph";
|
2024-06-15 16:02:09 -03:00
|
|
|
#clock-cells = <0x01>;
|
|
|
|
#reset-cells = <0x01>;
|
|
|
|
phandle = <0x1f>;
|
|
|
|
};
|
|
|
|
|
|
|
|
codec-analog@1f015c0 {
|
|
|
|
compatible = "allwinner,sun8i-h3-codec-analog";
|
|
|
|
reg = <0x1f015c0 0x04>;
|
|
|
|
phandle = <0x15>;
|
|
|
|
};
|
|
|
|
|
|
|
|
ir@1f02000 {
|
|
|
|
compatible = "allwinner,sun6i-a31-ir";
|
|
|
|
clocks = <0x1f 0x04 0x1f 0x0b>;
|
2024-06-15 16:25:47 -03:00
|
|
|
clock-names = "apb", "ir";
|
2024-06-15 16:02:09 -03:00
|
|
|
resets = <0x1f 0x00>;
|
|
|
|
interrupts = <0x00 0x25 0x04>;
|
|
|
|
reg = <0x1f02000 0x400>;
|
|
|
|
status = "disabled";
|
|
|
|
phandle = <0x63>;
|
|
|
|
};
|
|
|
|
|
|
|
|
i2c@1f02400 {
|
|
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
|
|
reg = <0x1f02400 0x400>;
|
|
|
|
interrupts = <0x00 0x2c 0x04>;
|
|
|
|
pinctrl-names = "default";
|
|
|
|
pinctrl-0 = <0x20>;
|
|
|
|
clocks = <0x1f 0x09>;
|
|
|
|
resets = <0x1f 0x05>;
|
|
|
|
status = "disabled";
|
|
|
|
#address-cells = <0x01>;
|
|
|
|
#size-cells = <0x00>;
|
|
|
|
phandle = <0x64>;
|
|
|
|
};
|
|
|
|
|
|
|
|
pinctrl@1f02c00 {
|
|
|
|
compatible = "allwinner,sun8i-h3-r-pinctrl";
|
|
|
|
reg = <0x1f02c00 0x400>;
|
|
|
|
interrupts = <0x00 0x2d 0x04>;
|
|
|
|
clocks = <0x1f 0x03 0x0e 0x0f 0x00>;
|
2024-06-15 16:25:47 -03:00
|
|
|
clock-names = "apb", "hosc", "losc";
|
2024-06-15 16:02:09 -03:00
|
|
|
gpio-controller;
|
|
|
|
#gpio-cells = <0x03>;
|
|
|
|
interrupt-controller;
|
|
|
|
#interrupt-cells = <0x03>;
|
|
|
|
vcc-pl-supply = <0x21>;
|
|
|
|
phandle = <0x2e>;
|
|
|
|
|
|
|
|
r-ir-rx-pin {
|
|
|
|
pins = "PL11";
|
|
|
|
function = "s_cir_rx";
|
|
|
|
phandle = <0x65>;
|
|
|
|
};
|
|
|
|
|
|
|
|
r-i2c-pins {
|
2024-06-15 16:25:47 -03:00
|
|
|
pins = "PL0", "PL1";
|
2024-06-15 16:02:09 -03:00
|
|
|
function = "s_i2c";
|
|
|
|
phandle = <0x20>;
|
|
|
|
};
|
|
|
|
|
|
|
|
r-pwm-pin {
|
|
|
|
pins = "PL10";
|
|
|
|
function = "s_pwm";
|
|
|
|
phandle = <0x22>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
pwm@1f03800 {
|
|
|
|
compatible = "allwinner,sun8i-h3-pwm";
|
|
|
|
reg = <0x1f03800 0x08>;
|
|
|
|
pinctrl-names = "default";
|
|
|
|
pinctrl-0 = <0x22>;
|
|
|
|
clocks = <0x0e>;
|
|
|
|
#pwm-cells = <0x03>;
|
|
|
|
status = "disabled";
|
|
|
|
phandle = <0x66>;
|
|
|
|
};
|
|
|
|
|
|
|
|
system-control@1c00000 {
|
|
|
|
compatible = "allwinner,sun50i-h5-system-control";
|
|
|
|
reg = <0x1c00000 0x1000>;
|
|
|
|
#address-cells = <0x01>;
|
|
|
|
#size-cells = <0x01>;
|
|
|
|
ranges;
|
|
|
|
phandle = <0x10>;
|
|
|
|
|
|
|
|
sram@18000 {
|
|
|
|
compatible = "mmio-sram";
|
|
|
|
reg = <0x18000 0x1c000>;
|
|
|
|
#address-cells = <0x01>;
|
|
|
|
#size-cells = <0x01>;
|
|
|
|
ranges = <0x00 0x18000 0x1c000>;
|
|
|
|
phandle = <0x67>;
|
|
|
|
|
|
|
|
sram-section@0 {
|
2024-06-15 16:25:47 -03:00
|
|
|
compatible = "allwinner,sun50i-h5-sram-c1", "allwinner,sun4i-a10-sram-c1";
|
2024-06-15 16:02:09 -03:00
|
|
|
reg = <0x00 0x1c000>;
|
|
|
|
phandle = <0x23>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
video-codec@1c0e000 {
|
|
|
|
compatible = "allwinner,sun50i-h5-video-engine";
|
|
|
|
reg = <0x1c0e000 0x1000>;
|
|
|
|
clocks = <0x03 0x29 0x03 0x6c 0x03 0x61>;
|
2024-06-15 16:25:47 -03:00
|
|
|
clock-names = "ahb", "mod", "ram";
|
2024-06-15 16:02:09 -03:00
|
|
|
resets = <0x03 0x1a>;
|
|
|
|
interrupts = <0x00 0x3a 0x04>;
|
|
|
|
allwinner,sram = <0x23 0x01>;
|
|
|
|
};
|
|
|
|
|
|
|
|
crypto@1c15000 {
|
|
|
|
compatible = "allwinner,sun50i-h5-crypto";
|
|
|
|
reg = <0x1c15000 0x1000>;
|
|
|
|
interrupts = <0x00 0x5e 0x04>;
|
|
|
|
clocks = <0x03 0x14 0x03 0x51>;
|
2024-06-15 16:25:47 -03:00
|
|
|
clock-names = "bus", "mod";
|
2024-06-15 16:02:09 -03:00
|
|
|
resets = <0x03 0x05>;
|
|
|
|
phandle = <0x68>;
|
|
|
|
};
|
|
|
|
|
|
|
|
gpu@1e80000 {
|
2024-06-15 16:25:47 -03:00
|
|
|
compatible = "allwinner,sun50i-h5-mali", "arm,mali-450";
|
2024-06-15 16:02:09 -03:00
|
|
|
reg = <0x1e80000 0x30000>;
|
|
|
|
interrupts = <0x00 0x60 0x04 0x00 0x61 0x04 0x00 0x63 0x04 0x00 0x64 0x04 0x00 0x65 0x04 0x00 0x66 0x04 0x00 0x67 0x04 0x00 0x68 0x04 0x00 0x69 0x04 0x00 0x6a 0x04 0x00 0x6b 0x04>;
|
2024-06-15 16:25:47 -03:00
|
|
|
interrupt-names = "gp", "gpmmu", "pp", "pp0", "ppmmu0", "pp1", "ppmmu1", "pp2", "ppmmu2", "pp3", "ppmmu3";
|
2024-06-15 16:02:09 -03:00
|
|
|
clocks = <0x03 0x31 0x03 0x72>;
|
2024-06-15 16:25:47 -03:00
|
|
|
clock-names = "bus", "core";
|
2024-06-15 16:02:09 -03:00
|
|
|
resets = <0x03 0x23>;
|
|
|
|
assigned-clocks = <0x03 0x72>;
|
|
|
|
assigned-clock-rates = <0x16e36000>;
|
|
|
|
phandle = <0x69>;
|
|
|
|
};
|
|
|
|
|
|
|
|
thermal-sensor@1c25000 {
|
|
|
|
compatible = "allwinner,sun50i-h5-ths";
|
|
|
|
reg = <0x1c25000 0x400>;
|
|
|
|
interrupts = <0x00 0x1f 0x04>;
|
|
|
|
resets = <0x03 0x2a>;
|
|
|
|
clocks = <0x03 0x37 0x03 0x45>;
|
2024-06-15 16:25:47 -03:00
|
|
|
clock-names = "bus", "mod";
|
2024-06-15 16:02:09 -03:00
|
|
|
nvmem-cells = <0x24>;
|
|
|
|
nvmem-cell-names = "calibration";
|
|
|
|
#thermal-sensor-cells = <0x01>;
|
|
|
|
phandle = <0x2a>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
cpus {
|
|
|
|
#address-cells = <0x01>;
|
|
|
|
#size-cells = <0x00>;
|
|
|
|
|
|
|
|
cpu@0 {
|
|
|
|
compatible = "arm,cortex-a53";
|
|
|
|
device_type = "cpu";
|
|
|
|
reg = <0x00>;
|
|
|
|
enable-method = "psci";
|
|
|
|
clocks = <0x03 0x0e>;
|
|
|
|
clock-latency-ns = <0x3b9b0>;
|
|
|
|
#cooling-cells = <0x02>;
|
|
|
|
cpu-supply = <0x25>;
|
|
|
|
phandle = <0x26>;
|
|
|
|
};
|
|
|
|
|
|
|
|
cpu@1 {
|
|
|
|
compatible = "arm,cortex-a53";
|
|
|
|
device_type = "cpu";
|
|
|
|
reg = <0x01>;
|
|
|
|
enable-method = "psci";
|
|
|
|
clocks = <0x03 0x0e>;
|
|
|
|
clock-latency-ns = <0x3b9b0>;
|
|
|
|
#cooling-cells = <0x02>;
|
|
|
|
cpu-supply = <0x25>;
|
|
|
|
phandle = <0x27>;
|
|
|
|
};
|
|
|
|
|
|
|
|
cpu@2 {
|
|
|
|
compatible = "arm,cortex-a53";
|
|
|
|
device_type = "cpu";
|
|
|
|
reg = <0x02>;
|
|
|
|
enable-method = "psci";
|
|
|
|
clocks = <0x03 0x0e>;
|
|
|
|
clock-latency-ns = <0x3b9b0>;
|
|
|
|
#cooling-cells = <0x02>;
|
|
|
|
cpu-supply = <0x25>;
|
|
|
|
phandle = <0x28>;
|
|
|
|
};
|
|
|
|
|
|
|
|
cpu@3 {
|
|
|
|
compatible = "arm,cortex-a53";
|
|
|
|
device_type = "cpu";
|
|
|
|
reg = <0x03>;
|
|
|
|
enable-method = "psci";
|
|
|
|
clocks = <0x03 0x0e>;
|
|
|
|
clock-latency-ns = <0x3b9b0>;
|
|
|
|
#cooling-cells = <0x02>;
|
|
|
|
cpu-supply = <0x25>;
|
|
|
|
phandle = <0x29>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
pmu {
|
|
|
|
compatible = "arm,cortex-a53-pmu";
|
|
|
|
interrupts = <0x00 0x74 0x04 0x00 0x75 0x04 0x00 0x76 0x04 0x00 0x77 0x04>;
|
|
|
|
interrupt-affinity = <0x26 0x27 0x28 0x29>;
|
|
|
|
};
|
|
|
|
|
|
|
|
psci {
|
|
|
|
compatible = "arm,psci-0.2";
|
|
|
|
method = "smc";
|
|
|
|
};
|
|
|
|
|
|
|
|
timer {
|
|
|
|
compatible = "arm,armv8-timer";
|
|
|
|
arm,no-tick-in-suspend;
|
|
|
|
interrupts = <0x01 0x0d 0xf08 0x01 0x0e 0xf08 0x01 0x0b 0xf08 0x01 0x0a 0xf08>;
|
|
|
|
};
|
|
|
|
|
|
|
|
thermal-zones {
|
|
|
|
|
|
|
|
cpu-thermal {
|
|
|
|
polling-delay-passive = <0x00>;
|
|
|
|
polling-delay = <0x00>;
|
|
|
|
thermal-sensors = <0x2a 0x00>;
|
|
|
|
phandle = <0x6a>;
|
|
|
|
|
|
|
|
trips {
|
|
|
|
|
|
|
|
cpu-hot {
|
|
|
|
temperature = <0x13880>;
|
|
|
|
hysteresis = <0x7d0>;
|
|
|
|
type = "passive";
|
|
|
|
phandle = <0x2b>;
|
|
|
|
};
|
|
|
|
|
|
|
|
cpu-very-hot {
|
|
|
|
temperature = <0x186a0>;
|
|
|
|
hysteresis = <0x00>;
|
|
|
|
type = "critical";
|
|
|
|
phandle = <0x6b>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
cooling-maps {
|
|
|
|
|
|
|
|
cpu-hot-limit {
|
|
|
|
trip = <0x2b>;
|
|
|
|
cooling-device = <0x26 0xffffffff 0xffffffff 0x27 0xffffffff 0xffffffff 0x28 0xffffffff 0xffffffff 0x29 0xffffffff 0xffffffff>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
gpu-thermal {
|
|
|
|
polling-delay-passive = <0x00>;
|
|
|
|
polling-delay = <0x00>;
|
|
|
|
thermal-sensors = <0x2a 0x01>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
aliases {
|
|
|
|
serial0 = "/soc/serial@1c28000";
|
|
|
|
spi0 = "/soc/spi@1c68000";
|
|
|
|
};
|
|
|
|
|
|
|
|
connector {
|
|
|
|
compatible = "hdmi-connector";
|
|
|
|
type = "d";
|
|
|
|
|
|
|
|
port {
|
|
|
|
|
|
|
|
endpoint {
|
|
|
|
remote-endpoint = <0x2c>;
|
|
|
|
phandle = <0x1d>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
leds {
|
|
|
|
compatible = "gpio-leds";
|
|
|
|
|
|
|
|
status_led {
|
|
|
|
label = "librecomputer:blue:status";
|
|
|
|
gpios = <0x0a 0x00 0x07 0x00>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
vcc3v3 {
|
|
|
|
compatible = "regulator-fixed";
|
|
|
|
regulator-name = "vcc3v3";
|
|
|
|
regulator-min-microvolt = <0x325aa0>;
|
|
|
|
regulator-max-microvolt = <0x325aa0>;
|
|
|
|
regulator-always-on;
|
|
|
|
regulator-boot-on;
|
|
|
|
vin-supply = <0x2d>;
|
|
|
|
phandle = <0x21>;
|
|
|
|
};
|
|
|
|
|
|
|
|
vcc5v0 {
|
|
|
|
compatible = "regulator-fixed";
|
|
|
|
regulator-name = "vcc5v0";
|
|
|
|
regulator-min-microvolt = <0x4c4b40>;
|
|
|
|
regulator-max-microvolt = <0x4c4b40>;
|
|
|
|
regulator-always-on;
|
|
|
|
regulator-boot-on;
|
|
|
|
phandle = <0x2d>;
|
|
|
|
};
|
|
|
|
|
|
|
|
vcc-dram {
|
|
|
|
compatible = "regulator-fixed";
|
|
|
|
regulator-name = "vcc-dram";
|
|
|
|
regulator-min-microvolt = <0x16e360>;
|
|
|
|
regulator-max-microvolt = <0x16e360>;
|
|
|
|
regulator-always-on;
|
|
|
|
regulator-boot-on;
|
|
|
|
vin-supply = <0x2d>;
|
|
|
|
gpio = <0x2e 0x00 0x09 0x00>;
|
|
|
|
enable-active-high;
|
|
|
|
phandle = <0x6c>;
|
|
|
|
};
|
|
|
|
|
|
|
|
vcc-io {
|
|
|
|
compatible = "regulator-fixed";
|
|
|
|
regulator-name = "vcc-io";
|
|
|
|
regulator-always-on;
|
|
|
|
regulator-boot-on;
|
|
|
|
vin-supply = <0x21>;
|
|
|
|
gpio = <0x2e 0x00 0x05 0x01>;
|
|
|
|
phandle = <0x09>;
|
|
|
|
};
|
|
|
|
|
|
|
|
vcc-usbwifi {
|
|
|
|
compatible = "regulator-fixed";
|
|
|
|
regulator-name = "vcc-usbwifi";
|
|
|
|
regulator-min-microvolt = <0x325aa0>;
|
|
|
|
regulator-max-microvolt = <0x325aa0>;
|
|
|
|
vin-supply = <0x2d>;
|
|
|
|
gpio = <0x0a 0x06 0x04 0x00>;
|
|
|
|
enable-active-high;
|
|
|
|
phandle = <0x0d>;
|
|
|
|
};
|
|
|
|
|
|
|
|
vdd-cpux {
|
|
|
|
compatible = "regulator-fixed";
|
|
|
|
regulator-name = "vdd-cpux";
|
|
|
|
regulator-min-microvolt = <0x10c8e0>;
|
|
|
|
regulator-max-microvolt = <0x10c8e0>;
|
|
|
|
regulator-always-on;
|
|
|
|
regulator-boot-on;
|
|
|
|
vin-supply = <0x2d>;
|
|
|
|
gpio = <0x2e 0x00 0x08 0x00>;
|
|
|
|
enable-active-high;
|
|
|
|
phandle = <0x25>;
|
|
|
|
};
|
|
|
|
|
|
|
|
__symbols__ {
|
|
|
|
osc24M = "/clocks/osc24M_clk";
|
|
|
|
osc32k = "/clocks/osc32k_clk";
|
|
|
|
de = "/display-engine";
|
|
|
|
display_clocks = "/soc/clock@1000000";
|
|
|
|
mixer0 = "/soc/mixer@1100000";
|
|
|
|
mixer0_out = "/soc/mixer@1100000/ports/port@1";
|
|
|
|
mixer0_out_tcon0 = "/soc/mixer@1100000/ports/port@1/endpoint";
|
|
|
|
dma = "/soc/dma-controller@1c02000";
|
|
|
|
tcon0 = "/soc/lcd-controller@1c0c000";
|
|
|
|
tcon0_in = "/soc/lcd-controller@1c0c000/ports/port@0";
|
|
|
|
tcon0_in_mixer0 = "/soc/lcd-controller@1c0c000/ports/port@0/endpoint";
|
|
|
|
tcon0_out = "/soc/lcd-controller@1c0c000/ports/port@1";
|
|
|
|
tcon0_out_hdmi = "/soc/lcd-controller@1c0c000/ports/port@1/endpoint@1";
|
|
|
|
mmc0 = "/soc/mmc@1c0f000";
|
|
|
|
mmc1 = "/soc/mmc@1c10000";
|
|
|
|
mmc2 = "/soc/mmc@1c11000";
|
|
|
|
sid = "/soc/eeprom@1c14000";
|
|
|
|
ths_calibration = "/soc/eeprom@1c14000/thermal-sensor-calibration@34";
|
|
|
|
msgbox = "/soc/mailbox@1c17000";
|
|
|
|
usb_otg = "/soc/usb@1c19000";
|
|
|
|
usbphy = "/soc/phy@1c19400";
|
|
|
|
ehci0 = "/soc/usb@1c1a000";
|
|
|
|
ohci0 = "/soc/usb@1c1a400";
|
|
|
|
ehci1 = "/soc/usb@1c1b000";
|
|
|
|
ohci1 = "/soc/usb@1c1b400";
|
|
|
|
ehci2 = "/soc/usb@1c1c000";
|
|
|
|
ohci2 = "/soc/usb@1c1c400";
|
|
|
|
ehci3 = "/soc/usb@1c1d000";
|
|
|
|
ohci3 = "/soc/usb@1c1d400";
|
|
|
|
ccu = "/soc/clock@1c20000";
|
|
|
|
pio = "/soc/pinctrl@1c20800";
|
|
|
|
csi_pins = "/soc/pinctrl@1c20800/csi-pins";
|
|
|
|
emac_rgmii_pins = "/soc/pinctrl@1c20800/emac-rgmii-pins";
|
|
|
|
i2c0_pins = "/soc/pinctrl@1c20800/i2c0-pins";
|
|
|
|
i2c1_pins = "/soc/pinctrl@1c20800/i2c1-pins";
|
|
|
|
i2c2_pins = "/soc/pinctrl@1c20800/i2c2-pins";
|
|
|
|
mmc0_pins = "/soc/pinctrl@1c20800/mmc0-pins";
|
|
|
|
mmc1_pins = "/soc/pinctrl@1c20800/mmc1-pins";
|
|
|
|
mmc2_8bit_pins = "/soc/pinctrl@1c20800/mmc2-8bit-pins";
|
|
|
|
spdif_tx_pin = "/soc/pinctrl@1c20800/spdif-tx-pin";
|
|
|
|
spi0_pins = "/soc/pinctrl@1c20800/spi0-pins";
|
|
|
|
spi1_pins = "/soc/pinctrl@1c20800/spi1-pins";
|
|
|
|
uart0_pa_pins = "/soc/pinctrl@1c20800/uart0-pa-pins";
|
|
|
|
uart1_pins = "/soc/pinctrl@1c20800/uart1-pins";
|
|
|
|
uart1_rts_cts_pins = "/soc/pinctrl@1c20800/uart1-rts-cts-pins";
|
|
|
|
uart2_pins = "/soc/pinctrl@1c20800/uart2-pins";
|
|
|
|
uart2_rts_cts_pins = "/soc/pinctrl@1c20800/uart2-rts-cts-pins";
|
|
|
|
uart3_pins = "/soc/pinctrl@1c20800/uart3-pins";
|
|
|
|
uart3_rts_cts_pins = "/soc/pinctrl@1c20800/uart3-rts-cts-pins";
|
|
|
|
emac = "/soc/ethernet@1c30000";
|
|
|
|
mdio = "/soc/ethernet@1c30000/mdio";
|
|
|
|
internal_mdio = "/soc/ethernet@1c30000/mdio-mux/mdio@1";
|
|
|
|
int_mii_phy = "/soc/ethernet@1c30000/mdio-mux/mdio@1/ethernet-phy@1";
|
|
|
|
external_mdio = "/soc/ethernet@1c30000/mdio-mux/mdio@2";
|
|
|
|
mbus = "/soc/dram-controller@1c62000";
|
|
|
|
spi0 = "/soc/spi@1c68000";
|
|
|
|
spi1 = "/soc/spi@1c69000";
|
|
|
|
wdt0 = "/soc/watchdog@1c20ca0";
|
|
|
|
spdif = "/soc/spdif@1c21000";
|
|
|
|
pwm = "/soc/pwm@1c21400";
|
|
|
|
i2s0 = "/soc/i2s@1c22000";
|
|
|
|
i2s1 = "/soc/i2s@1c22400";
|
|
|
|
codec = "/soc/codec@1c22c00";
|
|
|
|
uart0 = "/soc/serial@1c28000";
|
|
|
|
uart1 = "/soc/serial@1c28400";
|
|
|
|
uart2 = "/soc/serial@1c28800";
|
|
|
|
uart3 = "/soc/serial@1c28c00";
|
|
|
|
i2c0 = "/soc/i2c@1c2ac00";
|
|
|
|
i2c1 = "/soc/i2c@1c2b000";
|
|
|
|
i2c2 = "/soc/i2c@1c2b400";
|
|
|
|
gic = "/soc/interrupt-controller@1c81000";
|
|
|
|
csi = "/soc/camera@1cb0000";
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hdmi = "/soc/hdmi@1ee0000";
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hdmi_in = "/soc/hdmi@1ee0000/ports/port@0";
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hdmi_in_tcon0 = "/soc/hdmi@1ee0000/ports/port@0/endpoint";
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hdmi_out = "/soc/hdmi@1ee0000/ports/port@1";
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hdmi_out_con = "/soc/hdmi@1ee0000/ports/port@1/endpoint";
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hdmi_phy = "/soc/hdmi-phy@1ef0000";
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rtc = "/soc/rtc@1f00000";
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r_ccu = "/soc/clock@1f01400";
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codec_analog = "/soc/codec-analog@1f015c0";
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ir = "/soc/ir@1f02000";
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r_i2c = "/soc/i2c@1f02400";
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r_pio = "/soc/pinctrl@1f02c00";
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r_ir_rx_pin = "/soc/pinctrl@1f02c00/r-ir-rx-pin";
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r_i2c_pins = "/soc/pinctrl@1f02c00/r-i2c-pins";
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r_pwm_pin = "/soc/pinctrl@1f02c00/r-pwm-pin";
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r_pwm = "/soc/pwm@1f03800";
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syscon = "/soc/system-control@1c00000";
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sram_c1 = "/soc/system-control@1c00000/sram@18000";
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ve_sram = "/soc/system-control@1c00000/sram@18000/sram-section@0";
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crypto = "/soc/crypto@1c15000";
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mali = "/soc/gpu@1e80000";
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ths = "/soc/thermal-sensor@1c25000";
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cpu0 = "/cpus/cpu@0";
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cpu1 = "/cpus/cpu@1";
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cpu2 = "/cpus/cpu@2";
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cpu3 = "/cpus/cpu@3";
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cpu_thermal = "/thermal-zones/cpu-thermal";
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cpu_hot_trip = "/thermal-zones/cpu-thermal/trips/cpu-hot";
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cpu_very_hot_trip = "/thermal-zones/cpu-thermal/trips/cpu-very-hot";
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hdmi_con_in = "/connector/port/endpoint";
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reg_vcc3v3 = "/vcc3v3";
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reg_vcc5v0 = "/vcc5v0";
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reg_vcc_dram = "/vcc-dram";
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reg_vcc_io = "/vcc-io";
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reg_vcc_usbwifi = "/vcc-usbwifi";
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reg_vdd_cpux = "/vdd-cpux";
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};
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};
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