2986 lines
125 KiB
C
2986 lines
125 KiB
C
|
#ifndef __CMUCAL_NODE_H__
|
||
|
|
#define __CMUCAL_NODE_H__
|
||
|
|
|
||
|
|
#include "../../cmucal.h"
|
||
|
|
|
||
|
|
enum clk_id {
|
||
|
|
OSCCLK_RCO_ALIVE = FIXED_RATE_TYPE,
|
||
|
|
CLK_RCO_ALIVE,
|
||
|
|
CLK_RCO_I3C_PMIC,
|
||
|
|
RCO_400,
|
||
|
|
RTCCLK_ALIVE,
|
||
|
|
FREE_OSCCLK_ALIVE,
|
||
|
|
FREE_OSCCLK_ALLCSIS,
|
||
|
|
IOCLK_AUDIOCDCLK0,
|
||
|
|
IOCLK_AUDIOCDCLK1,
|
||
|
|
IOCLK_AUDIOCDCLK2,
|
||
|
|
CLKIO_AUD_DSIF,
|
||
|
|
CLK_RCO_AUD,
|
||
|
|
IOCLK_AUDIOCDCLK3,
|
||
|
|
IOCLK_AUDIOCDCLK6,
|
||
|
|
OSCCLK_PLL_AUD,
|
||
|
|
FREE_OSCCLK_AUD,
|
||
|
|
FREE_OSCCLK_BRP,
|
||
|
|
RTCCLK_CHUB,
|
||
|
|
FREE_OSCCLK_CHUB,
|
||
|
|
FREE_OSCCLK_CHUBVTS,
|
||
|
|
OSCCLK_CMGP,
|
||
|
|
FREE_OSCCLK_CMGP,
|
||
|
|
OSCCLK_CMU,
|
||
|
|
FREE_OSCCLK_CMU,
|
||
|
|
OSCCLK_PLL_CMU,
|
||
|
|
OSCCLK_CPUCL0,
|
||
|
|
STRETCHER_CLK_CPUCL0,
|
||
|
|
OSCCLK_PLL_CPUCL0,
|
||
|
|
FREE_OSCCLK_CPUCL0,
|
||
|
|
FREE_OSCCLK_CPUCL0_GLB,
|
||
|
|
OSCCLK_CPUCL1,
|
||
|
|
STRETCHER_CLK_CPUCL1,
|
||
|
|
OSCCLK_PLL_CPUCL1,
|
||
|
|
FREE_OSCCLK_CPUCL1,
|
||
|
|
OSCCLK_CPUCL2,
|
||
|
|
STRETCHER_CLK_CPUCL2,
|
||
|
|
OSCCLK_PLL_CPUCL2,
|
||
|
|
FREE_OSCCLK_CPUCL2,
|
||
|
|
FREE_OSCCLK_CSIS,
|
||
|
|
FREE_OSCCLK_CSTAT,
|
||
|
|
OSCCLK_DBGCORE,
|
||
|
|
TCXO_IN,
|
||
|
|
FREE_OSCCLK_DBGCORE,
|
||
|
|
FREE_OSCCLK_DNC,
|
||
|
|
FREE_OSCCLK_DPUB,
|
||
|
|
FREE_OSCCLK_DPUF,
|
||
|
|
OSCCLK_DPUF1,
|
||
|
|
FREE_OSCCLK_DPUF1,
|
||
|
|
FREE_OSCCLK_DRCP,
|
||
|
|
FREE_OSCCLK_DSP,
|
||
|
|
OSCCLK_DSU,
|
||
|
|
STRETCHER_CLK_DSU,
|
||
|
|
OSCCLK_PLL_DSU,
|
||
|
|
FREE_OSCCLK_DSU,
|
||
|
|
FREE_OSCCLK_G3D,
|
||
|
|
OSCCLK_PLL_G3DCORE,
|
||
|
|
FREE_OSCCLK_G3DCORE,
|
||
|
|
FREE_OSCCLK_GNPU,
|
||
|
|
OSCCLK_19_2,
|
||
|
|
OSCCLK_HSI0,
|
||
|
|
RTCCLK_HSI0,
|
||
|
|
FREE_OSCCLK_HSI0,
|
||
|
|
FREE_OSCCLK_HSI1,
|
||
|
|
FREE_OSCCLK_LME,
|
||
|
|
FREE_OSCCLK_M2M,
|
||
|
|
FREE_OSCCLK_MCSC,
|
||
|
|
FREE_OSCCLK_MFC0,
|
||
|
|
FREE_OSCCLK_MFC1,
|
||
|
|
OSCCLK_MIF,
|
||
|
|
I_CLK_MIF_NOCD_DBG,
|
||
|
|
FREE_OSCCLK_MIF,
|
||
|
|
OSCCLK_PLL_MIF,
|
||
|
|
OSCCLK_NOCL0,
|
||
|
|
FREE_OSCCLK_NOCL0,
|
||
|
|
OSCCLK_NOCL1A,
|
||
|
|
FREE_OSCCLK_NOCL1A,
|
||
|
|
OSCCLK_NOCL1B,
|
||
|
|
FREE_OSCCLK_NOCL1B,
|
||
|
|
OSCCLK_NOCL1C,
|
||
|
|
FREE_OSCCLK_NOCL1C,
|
||
|
|
FREE_OSCCLK_PERIC0,
|
||
|
|
FREE_OSCCLK_PERIC1,
|
||
|
|
FREE_OSCCLK_PERIC2,
|
||
|
|
OSCCLK_PERIS,
|
||
|
|
FREE_OSCCLK_PERIS,
|
||
|
|
OSCCLK_S2D,
|
||
|
|
I_SCLK_S2D,
|
||
|
|
FREE_OSCCLK_S2D,
|
||
|
|
OSCCLK_PLL_S2D,
|
||
|
|
FREE_OSCCLK_SDMA,
|
||
|
|
FREE_OSCCLK_SSP,
|
||
|
|
FREE_OSCCLK_STRONG,
|
||
|
|
FREE_OSCCLK_UFD,
|
||
|
|
FREE_OSCCLK_UFS,
|
||
|
|
DMIC_CLK0_IN,
|
||
|
|
DMCI_CLK1_IN,
|
||
|
|
DMIC_CLK2_IN,
|
||
|
|
FREE_OSCCLK_VTS,
|
||
|
|
FREE_OSCCLK_YUVP,
|
||
|
|
end_of_fixed_rate,
|
||
|
|
num_of_fixed_rate = (end_of_fixed_rate - FIXED_RATE_TYPE) & MASK_OF_ID,
|
||
|
|
|
||
|
|
CLKCMU_HSI1_PCIE = FIXED_FACTOR_TYPE,
|
||
|
|
CLK_CPUCL0_DDD_CTRL,
|
||
|
|
CLK_CPUCL1_DDD_CTRL_0,
|
||
|
|
CLK_CPUCL1_DDD_CTRL_1,
|
||
|
|
CLK_CPUCL1_DDD_CTRL_2,
|
||
|
|
CLK_CPUCL2_DDD_CTRL,
|
||
|
|
DIV_CLK_DNC_DDD_CTRL,
|
||
|
|
CLK_DSU_DDD_CTRL,
|
||
|
|
CLK_G3D_DDD_CTRL,
|
||
|
|
DIV_CLK_MIF_NOCD,
|
||
|
|
DIV_CLK_MIF_DDD_CTRL,
|
||
|
|
CLKCMU_OTP,
|
||
|
|
DIV_CLK_PERIS_DDD_CTRL,
|
||
|
|
CLK_MIF_NOCD_S2D,
|
||
|
|
DIV_CLK_YUVP_DDD_CTRL,
|
||
|
|
PLL_AUD_D1,
|
||
|
|
PLL_AUD_D2,
|
||
|
|
PLL_AUD_D4,
|
||
|
|
PLL_MMC_D1,
|
||
|
|
PLL_MMC_D2,
|
||
|
|
PLL_MMC_D4,
|
||
|
|
PLL_SHARED0_D1,
|
||
|
|
PLL_SHARED0_D2,
|
||
|
|
PLL_SHARED0_D4,
|
||
|
|
PLL_SHARED1_D1,
|
||
|
|
PLL_SHARED1_D2,
|
||
|
|
PLL_SHARED1_D4,
|
||
|
|
PLL_SHARED2_D1,
|
||
|
|
PLL_SHARED2_D2,
|
||
|
|
PLL_SHARED2_D4,
|
||
|
|
PLL_SHARED3_D1,
|
||
|
|
PLL_SHARED3_D2,
|
||
|
|
PLL_SHARED3_D4,
|
||
|
|
PLL_SHARED4_D1,
|
||
|
|
PLL_SHARED4_D2,
|
||
|
|
PLL_SHARED4_D4,
|
||
|
|
PLL_SHARED_MIF_D1,
|
||
|
|
PLL_SHARED_MIF_D2,
|
||
|
|
PLL_SHARED_MIF_D4,
|
||
|
|
PLL_CPUCL0_D1,
|
||
|
|
PLL_CPUCL0_D2,
|
||
|
|
PLL_CPUCL0_D4,
|
||
|
|
PLL_CPUCL1_D1,
|
||
|
|
PLL_CPUCL1_D2,
|
||
|
|
PLL_CPUCL1_D4,
|
||
|
|
PLL_CPUCL2_D1,
|
||
|
|
PLL_CPUCL2_D2,
|
||
|
|
PLL_CPUCL2_D4,
|
||
|
|
PLL_DSU_D1,
|
||
|
|
PLL_DSU_D2,
|
||
|
|
PLL_DSU_D4,
|
||
|
|
PLL_G3D_D1,
|
||
|
|
PLL_G3D_D2,
|
||
|
|
PLL_G3D_D4,
|
||
|
|
PLL_G3D1_D1,
|
||
|
|
PLL_G3D1_D2,
|
||
|
|
PLL_G3D1_D4,
|
||
|
|
PLL_MIF_MAIN_D1,
|
||
|
|
PLL_MIF_MAIN_D2,
|
||
|
|
PLL_MIF_MAIN_D4,
|
||
|
|
PLL_MIF_SUB_D1,
|
||
|
|
PLL_MIF_SUB_D2,
|
||
|
|
PLL_MIF_SUB_D4,
|
||
|
|
PLL_MIF_S2D_D1,
|
||
|
|
PLL_MIF_S2D_D2,
|
||
|
|
PLL_MIF_S2D_D4,
|
||
|
|
end_of_fixed_factor,
|
||
|
|
num_of_fixed_factor = (end_of_fixed_factor - FIXED_FACTOR_TYPE) & MASK_OF_ID,
|
||
|
|
|
||
|
|
PLL_AUD = PLL_TYPE,
|
||
|
|
PLL_MMC,
|
||
|
|
PLL_SHARED0,
|
||
|
|
PLL_SHARED1,
|
||
|
|
PLL_SHARED2,
|
||
|
|
PLL_SHARED3,
|
||
|
|
PLL_SHARED4,
|
||
|
|
PLL_SHARED_MIF,
|
||
|
|
PLL_CPUCL0,
|
||
|
|
PLL_CPUCL1,
|
||
|
|
PLL_CPUCL2,
|
||
|
|
PLL_DSU,
|
||
|
|
PLL_G3D,
|
||
|
|
PLL_G3D1,
|
||
|
|
PLL_MIF_MAIN,
|
||
|
|
PLL_MIF_SUB,
|
||
|
|
PLL_MIF_S2D,
|
||
|
|
end_of_pll,
|
||
|
|
num_of_pll = (end_of_pll - PLL_TYPE) & MASK_OF_ID,
|
||
|
|
|
||
|
|
MUX_CLKALIVE_UFD_NOC = MUX_TYPE,
|
||
|
|
MUX_CLKALIVE_CMGP_NOC,
|
||
|
|
MUX_CLK_ALIVE_NOC,
|
||
|
|
MUX_CLKALIVE_CMGP_PERI,
|
||
|
|
MUX_CLKALIVE_CHUB_PERI,
|
||
|
|
MUX_CLKALIVE_DBGCORE_NOC,
|
||
|
|
MUX_CLKALIVE_DNC_NOC,
|
||
|
|
MUX_CLK_ALIVE_TIMER,
|
||
|
|
MUX_CLK_ALIVE_SPMI,
|
||
|
|
MUX_CLK_ALIVE_DBGCORE_UART,
|
||
|
|
MUX_CLKALIVE_GNPU_NOC,
|
||
|
|
MUX_CLKALIVE_GNSS_NOC,
|
||
|
|
MUX_CLKALIVE_SDMA_NOC,
|
||
|
|
MUX_CLK_ALIVE_PMU_SUB,
|
||
|
|
MUX_CLKALIVE_CHUBVTS_NOC,
|
||
|
|
MUX_CLKALIVE_CSIS_NOC,
|
||
|
|
MUX_CLKALIVE_DSP_NOC,
|
||
|
|
MUX_CLK_AUD_UAIF3,
|
||
|
|
MUX_CLK_AUD_UAIF2,
|
||
|
|
MUX_CLK_AUD_UAIF1,
|
||
|
|
MUX_CLK_AUD_UAIF0,
|
||
|
|
MUX_CLK_AUD_CPU,
|
||
|
|
MUX_CLK_AUD_DSIF,
|
||
|
|
MUX_CLK_AUD_UAIF4,
|
||
|
|
MUX_CLK_AUD_UAIF5,
|
||
|
|
MUX_CLK_AUD_UAIF6,
|
||
|
|
MUX_CLK_AUD_NOC,
|
||
|
|
MUX_CLK_AUD_PCMC,
|
||
|
|
MUX_CLK_AUD_AUDIF,
|
||
|
|
MUX_CLK_AUD_SCLK,
|
||
|
|
MUX_CLK_AUD_SERIAL_LIF,
|
||
|
|
MUX_CLK_AUD_SERIAL_LIF_CORE,
|
||
|
|
MUX_CHUB_TIMER,
|
||
|
|
MUX_CLK_CHUB_USI0,
|
||
|
|
MUX_CLK_CHUB_USI1,
|
||
|
|
MUX_CLK_CHUB_USI3,
|
||
|
|
MUX_CLK_CHUB_I2C,
|
||
|
|
MUX_CLK_CHUB_USI2,
|
||
|
|
MUX_CLK_CHUB_SPI_MS_CTRL,
|
||
|
|
MUX_CLK_CHUB_SPI_I2C0,
|
||
|
|
MUX_CLK_CHUB_SPI_I2C1,
|
||
|
|
MUX_CLK_CHUB_NOC,
|
||
|
|
MUX_CLK_CHUBVTS_DMAILBOX_CCLK,
|
||
|
|
MUX_CLK_CHUBVTS_NOC,
|
||
|
|
MUX_CLK_CMGP_USI4,
|
||
|
|
MUX_CLK_CMGP_USI0,
|
||
|
|
MUX_CLK_CMGP_USI1,
|
||
|
|
MUX_CLK_CMGP_USI2,
|
||
|
|
MUX_CLK_CMGP_USI3,
|
||
|
|
MUX_CLK_CMGP_USI5,
|
||
|
|
MUX_CLK_CMGP_USI6,
|
||
|
|
MUX_CLK_CMGP_I2C,
|
||
|
|
MUX_CLK_CMGP_SPI_MS_CTRL,
|
||
|
|
MUX_CLK_CMGP_SPI_I2C0,
|
||
|
|
MUX_CLK_CMGP_SPI_I2C1,
|
||
|
|
MUX_CLKCMU_HSI0_DPOSC,
|
||
|
|
MUX_CLKCMU_MFC0_MFC0,
|
||
|
|
MUX_CLKCMU_DSP_NOC,
|
||
|
|
MUX_CLKCMU_CPUCL0_SWITCH,
|
||
|
|
MUX_CLKCMU_NOCL0_NOC,
|
||
|
|
MUX_CLKCMU_MIF_SWITCH,
|
||
|
|
MUX_CLKCMU_BRP_NOC,
|
||
|
|
MUX_CLKCMU_YUVP_NOC,
|
||
|
|
MUX_CLKCMU_AUD_CPU,
|
||
|
|
MUX_CLKCMU_CPUCL0_DBG_NOC,
|
||
|
|
MUX_CLKCMU_CIS_CLK0,
|
||
|
|
MUX_CLKCMU_CIS_CLK1,
|
||
|
|
MUX_CLKCMU_CIS_CLK2,
|
||
|
|
MUX_CLKCMU_CIS_CLK3,
|
||
|
|
MUX_CMU_CMUREF,
|
||
|
|
MUX_CLKCMU_PERIC0_NOC,
|
||
|
|
MUX_CLKCMU_PERIC1_NOC,
|
||
|
|
MUX_CLKCMU_PERIS_NOC,
|
||
|
|
MUX_CLKCMU_HSI1_PCIE,
|
||
|
|
MUX_CLKCMU_GNPU_NOC,
|
||
|
|
MUX_CLKCMU_ALIVE_NOC,
|
||
|
|
MUX_CLKCMU_HSI1_NOC,
|
||
|
|
MUX_CLKCMU_MFC0_WFD,
|
||
|
|
MUX_CLKCMU_MIF_NOCP,
|
||
|
|
MUX_CLKCMU_PERIC0_IP0,
|
||
|
|
MUX_CLKCMU_PERIC1_IP0,
|
||
|
|
CLKCMU_DPUF_NOC,
|
||
|
|
MUX_CLKCMU_DPUF_ALT,
|
||
|
|
MUX_CLKCMU_CPUCL1_SWITCH,
|
||
|
|
MUX_CLKCMU_HSI0_NOC,
|
||
|
|
MUX_CLKCMU_CMU_BOOST_MIF,
|
||
|
|
MUX_CLKCMU_CIS_CLK4,
|
||
|
|
MUX_CLKCMU_DPUF,
|
||
|
|
MUX_CLKCMU_CMU_BOOST,
|
||
|
|
MUX_CLKCMU_CSIS_NOC,
|
||
|
|
MUX_CLKCMU_MCSC_NOC,
|
||
|
|
MUX_CLKCMU_CSIS_OIS_MCU,
|
||
|
|
MUX_CLKCMU_CIS_CLK5,
|
||
|
|
MUX_CLKCMU_CMU_BOOST_CPU,
|
||
|
|
MUX_CLKCMU_M2M_NOC,
|
||
|
|
MUX_CLKCMU_DPUB_ALT,
|
||
|
|
CLKCMU_DPUB_NOC,
|
||
|
|
MUX_CLKCMU_DPUB,
|
||
|
|
MUX_CLKCMU_MFC1_MFC1,
|
||
|
|
MUX_CLKCMU_LME_NOC,
|
||
|
|
MUX_CLKCMU_HSI0_USB32DRD,
|
||
|
|
MUX_CLKCMU_HSI0_DPGTC,
|
||
|
|
MUX_CLKCMU_AUD_NOC,
|
||
|
|
MUX_CLKCMU_CSIS_DCPHY,
|
||
|
|
MUX_CP_HISPEEDY_CLK,
|
||
|
|
MUX_CLKCMU_PERIC0_IP1,
|
||
|
|
MUX_CLKCMU_PERIC1_IP1,
|
||
|
|
MUX_CLKCMU_SSP_NOC,
|
||
|
|
MUX_CLKCMU_G3D_SWITCH,
|
||
|
|
MUX_CLKCMU_PERIC2_IP0,
|
||
|
|
MUX_CLKCMU_PERIC2_NOC,
|
||
|
|
MUX_CLKCMU_PERIC2_IP1,
|
||
|
|
MUX_CLKCMU_CPUCL0_NOCP,
|
||
|
|
MUX_CLKCMU_DSU_SWITCH,
|
||
|
|
MUX_CLKCMU_G3D_NOCP,
|
||
|
|
MUX_CLKCMU_CSTAT_NOC,
|
||
|
|
MUX_CLKCMU_DPUB_DSIM,
|
||
|
|
MUX_CLKCMU_DNC_NOC,
|
||
|
|
MUX_CLKCMU_CPUCL2_SWITCH,
|
||
|
|
MUX_CLKCMU_SDMA_NOC,
|
||
|
|
MUX_CLKCMU_CIS_CLK6,
|
||
|
|
MUX_CLKCMU_NOCL1C_NOC,
|
||
|
|
MUX_CP_SHARED0_CLK,
|
||
|
|
MUX_CP_SHARED1_CLK,
|
||
|
|
MUX_CP_SHARED2_CLK,
|
||
|
|
MUX_CLKCMU_CMU_BOOST_CAM,
|
||
|
|
MUX_CLKCMU_VTS_DMIC,
|
||
|
|
MUX_CLKCMU_AUD_AUDIF0,
|
||
|
|
MUX_CLKCMU_AUD_AUDIF1,
|
||
|
|
MUX_CLKCMU_PERIS_GIC,
|
||
|
|
MUX_CLKCMU_CIS_CLK7,
|
||
|
|
MUX_CLKCMU_NOCL1B_NOC0,
|
||
|
|
MUX_CLKCMU_NOCL1A_NOC,
|
||
|
|
MUX_CLKCMU_NOCL1B_NOC1,
|
||
|
|
MUX_CLKCMU_LME_LME,
|
||
|
|
MUX_CLKCMU_M2M_FRC,
|
||
|
|
MUX_CLKCMU_MCSC_MCSC,
|
||
|
|
MUX_CLKCMU_UFS_UFS_EMBD,
|
||
|
|
MUX_CLKCMU_UFS_NOC,
|
||
|
|
MUX_CLKCMU_UFS_MMC_CARD,
|
||
|
|
CLKCMU_AUD_CPU,
|
||
|
|
CLKCMU_AUD_AUDIF0,
|
||
|
|
CLKCMU_AUD_AUDIF1,
|
||
|
|
CLKCMU_CPUCL0_SWITCH,
|
||
|
|
CLKCMU_CPUCL1_SWITCH,
|
||
|
|
CLKCMU_CPUCL2_SWITCH,
|
||
|
|
CLKCMU_DSU_SWITCH,
|
||
|
|
CLKCMU_CPUCL0_DBG_NOC,
|
||
|
|
CLKCMU_DNC_NOC,
|
||
|
|
CLKCMU_SDMA_NOC,
|
||
|
|
CLKCMU_DSP_NOC,
|
||
|
|
CLKCMU_G3D_SWITCH,
|
||
|
|
CLKCMU_GNPU_NOC,
|
||
|
|
CLKCMU_M2M_NOC,
|
||
|
|
CLKCMU_M2M_FRC,
|
||
|
|
CLKCMU_MCSC_NOC,
|
||
|
|
CLKCMU_MCSC_MCSC,
|
||
|
|
CLKCMU_NOCL0_NOC,
|
||
|
|
CLKCMU_NOCL1A_NOC,
|
||
|
|
CLKCMU_NOCL1B_NOC0,
|
||
|
|
CLKCMU_NOCL1C_NOC,
|
||
|
|
CP_SHARED0_CLK,
|
||
|
|
CP_SHARED2_CLK,
|
||
|
|
CP_HISPEEDY_CLK,
|
||
|
|
CLKCMU_UFS_MMC_CARD,
|
||
|
|
MUX_CPUCL0_CMUREF,
|
||
|
|
MUX_CLK_CPUCL0_IDLECLKDOWN,
|
||
|
|
MUX_CLK_CPUCL0_DELAYMUX,
|
||
|
|
MUX_CLK_CPUCL0_DELAYCHAIN,
|
||
|
|
MUX_CLK_CPUCL0_POWERIP,
|
||
|
|
MUX_CLK_CPUCL0_DDD,
|
||
|
|
MUX_CLK_CPUCL0_HTU,
|
||
|
|
MUX_CLK_CPUCL1_IDLECLKDOWN_0,
|
||
|
|
MUX_CPUCL1_CMUREF,
|
||
|
|
MUX_CLK_CPUCL1_DELAYCHAIN_0,
|
||
|
|
MUX_CLK_CPUCL1_DELAYMUX_0,
|
||
|
|
MUX_CLK_CPUCL1_POWERIP,
|
||
|
|
MUX_CLK_CPUCL1_DDD_0,
|
||
|
|
MUX_CLK_CPUCL1_IDLECLKDOWN_1,
|
||
|
|
MUX_CLK_CPUCL1_DELAYMUX_1,
|
||
|
|
MUX_CLK_CPUCL1_DDD_1,
|
||
|
|
MUX_CLK_CPUCL1_DELAYCHAIN_1,
|
||
|
|
MUX_CLK_CPUCL1_IDLECLKDOWN_2,
|
||
|
|
MUX_CLK_CPUCL1_DELAYMUX_2,
|
||
|
|
MUX_CLK_CPUCL1_DDD_2,
|
||
|
|
MUX_CLK_CPUCL1_DELAYCHAIN_2,
|
||
|
|
MUX_CLK_CPUCL1_HTU,
|
||
|
|
MUX_CPUCL2_CMUREF,
|
||
|
|
MUX_CLK_CPUCL2_IDLECLKDOWN,
|
||
|
|
MUX_CLK_CPUCL2_DELAYCHAIN,
|
||
|
|
MUX_CLK_CPUCL2_DELAYMUX,
|
||
|
|
MUX_CLK_CPUCL2_POWERIP,
|
||
|
|
MUX_CLK_CPUCL2_DDD,
|
||
|
|
MUX_CLK_CPUCL2_HTU,
|
||
|
|
MUX_CLK_CSIS_NOC,
|
||
|
|
MUX_CLK_CSIS_DCPHY,
|
||
|
|
MUX_CLK_DNC_NOC,
|
||
|
|
MUX_CLK_DSP_NOC,
|
||
|
|
MUX_CLK_DSU_IDLECLKDOWN,
|
||
|
|
MUX_DSU_CMUREF,
|
||
|
|
MUX_CLK_DSU_DELAYCHAIN,
|
||
|
|
MUX_CLK_DSU_DELAYMUX,
|
||
|
|
MUX_CLK_DSU_POWERIP,
|
||
|
|
MUX_CLK_DSU_DDD,
|
||
|
|
MUX_CLK_DSU_HTU,
|
||
|
|
MUX_CLK_G3D_CORE,
|
||
|
|
MUX_CLK_G3D_DDD,
|
||
|
|
MUX_CLK_G3D_DELAYCHAIN,
|
||
|
|
MUX_CLK_G3D_DELAYMUX,
|
||
|
|
MUX_CLK_G3D_PLL,
|
||
|
|
MUX_CLK_GNPU_NOC,
|
||
|
|
MUX_CLK_HSI0_USB32DRD,
|
||
|
|
MUX_CLK_HSI0_NOC,
|
||
|
|
MUX_CLK_HSI0_RTCCLK,
|
||
|
|
MUX_MIF_CMUREF,
|
||
|
|
MUX_NOCL0_CMUREF,
|
||
|
|
MUX_NOCL1A_CMUREF,
|
||
|
|
MUX_NOCL1B_CMUREF,
|
||
|
|
MUX_NOCL1C_CMUREF,
|
||
|
|
MUX_CLK_PERIC0_USI04,
|
||
|
|
MUX_CLK_PERIC0_I2C,
|
||
|
|
MUX_CLK_PERIC1_UART_BT,
|
||
|
|
MUX_CLK_PERIC1_I2C,
|
||
|
|
MUX_CLK_PERIC1_USI07,
|
||
|
|
MUX_CLK_PERIC1_USI08,
|
||
|
|
MUX_CLK_PERIC1_USI09,
|
||
|
|
MUX_CLK_PERIC1_USI10,
|
||
|
|
MUX_CLK_PERIC1_SPI_MS_CTRL,
|
||
|
|
MUX_CLK_PERIC1_USI07_SPI_I2C,
|
||
|
|
MUX_CLK_PERIC1_USI08_SPI_I2C,
|
||
|
|
MUX_CLK_PERIC2_I2C,
|
||
|
|
MUX_CLK_PERIC2_USI00,
|
||
|
|
MUX_CLK_PERIC2_USI01,
|
||
|
|
MUX_CLK_PERIC2_USI02,
|
||
|
|
MUX_CLK_PERIC2_USI03,
|
||
|
|
MUX_CLK_PERIC2_USI05,
|
||
|
|
MUX_CLK_PERIC2_USI06,
|
||
|
|
MUX_CLK_PERIC2_SPI_MS_CTRL,
|
||
|
|
MUX_CLK_PERIC2_USI11,
|
||
|
|
MUX_CLK_PERIC2_UART_DBG,
|
||
|
|
MUX_CLK_PERIC2_USI00_SPI_I2C,
|
||
|
|
MUX_CLK_PERIC2_USI01_SPI_I2C,
|
||
|
|
MUX_CLK_S2D_CORE,
|
||
|
|
MUX_CLK_SDMA_NOC,
|
||
|
|
MUX_CLK_UFD_NOC,
|
||
|
|
MUX_CLK_VTS_DMIC_PAD,
|
||
|
|
MUX_CLKVTS_AUD_DMIC1,
|
||
|
|
MUX_CLK_VTS_NOC,
|
||
|
|
ALIVE_CMU_ALIVE_CLKOUT,
|
||
|
|
ALLCSIS_CMU_ALLCSIS_CLKOUT,
|
||
|
|
AUD_CMU_AUD_CLKOUT,
|
||
|
|
BRP_CMU_BRP_CLKOUT,
|
||
|
|
CHUB_CMU_CHUB_CLKOUT,
|
||
|
|
CHUBVTS_CMU_CHUBVTS_CLKOUT,
|
||
|
|
CMGP_CMU_CMGP_CLKOUT,
|
||
|
|
CMU_CMU_TOP_CLKOUT,
|
||
|
|
CPUCL0_CMU_CPUCL0_CLKOUT,
|
||
|
|
CPUCL0_GLB_CMU_CPUCL0_GLB_CLKOUT,
|
||
|
|
CPUCL1_CMU_CPUCL1_CLKOUT,
|
||
|
|
CPUCL2_CMU_CPUCL2_CLKOUT,
|
||
|
|
CSIS_CMU_CSIS_CLKOUT,
|
||
|
|
CSTAT_CMU_CSTAT_CLKOUT,
|
||
|
|
DBGCORE_CMU_DBGCORE_CLKOUT,
|
||
|
|
DNC_CMU_DNC_CLKOUT,
|
||
|
|
DPUB_CMU_DPUB_CLKOUT,
|
||
|
|
DPUF_CMU_DPUF_CLKOUT,
|
||
|
|
DPUF1_CMU_DPUF1_CLKOUT,
|
||
|
|
DRCP_CMU_DRCP_CLKOUT,
|
||
|
|
DSP_CMU_DSP_CLKOUT,
|
||
|
|
DSU_CMU_DSU_CLKOUT,
|
||
|
|
G3D_CMU_G3D_CLKOUT,
|
||
|
|
G3DCORE_CMU_G3DCORE_CLKOUT,
|
||
|
|
GNPU_CMU_GNPU_CLKOUT,
|
||
|
|
HSI0_CMU_HSI0_CLKOUT,
|
||
|
|
HSI1_CMU_HSI1_CLKOUT,
|
||
|
|
LME_CMU_LME_CLKOUT,
|
||
|
|
M2M_CMU_M2M_CLKOUT,
|
||
|
|
MCSC_CMU_MCSC_CLKOUT,
|
||
|
|
MFC0_CMU_MFC0_CLKOUT,
|
||
|
|
MFC1_CMU_MFC1_CLKOUT,
|
||
|
|
MIF_CMU_MIF_CLKOUT,
|
||
|
|
NOCL0_CMU_NOCL0_CLKOUT,
|
||
|
|
NOCL1A_CMU_NOCL1A_CLKOUT,
|
||
|
|
NOCL1B_CMU_NOCL1B_CLKOUT,
|
||
|
|
NOCL1C_CMU_NOCL1C_CLKOUT,
|
||
|
|
PERIC0_CMU_PERIC0_CLKOUT,
|
||
|
|
PERIC1_CMU_PERIC1_CLKOUT,
|
||
|
|
PERIC2_CMU_PERIC2_CLKOUT,
|
||
|
|
PERIS_CMU_PERIS_CLKOUT,
|
||
|
|
SDMA_CMU_SDMA_CLKOUT,
|
||
|
|
SSP_CMU_SSP_CLKOUT,
|
||
|
|
STRONG_CMU_STRONG_CLKOUT,
|
||
|
|
UFD_CMU_UFD_CLKOUT,
|
||
|
|
UFS_CMU_UFS_CLKOUT,
|
||
|
|
VTS_CMU_VTS_CLKOUT,
|
||
|
|
YUVP_CMU_YUVP_CLKOUT,
|
||
|
|
MUX_CLKCMU_ALIVE_NOC_USER = ((MASK_OF_ID & YUVP_CMU_YUVP_CLKOUT) | USER_MUX_TYPE) + 1,
|
||
|
|
MUX_CLK_RCO_ALIVE_USER,
|
||
|
|
MUX_CLKMUX_ALIVE_RCO_SPMI_USER,
|
||
|
|
MUX_CLKCMU_AUD_CPU_USER,
|
||
|
|
MUX_CLKCMU_AUD_NOC_USER,
|
||
|
|
MUX_CP_PCMC_CLK_USER,
|
||
|
|
MUX_CLK_AUD_RCO_USER,
|
||
|
|
MUX_CLKCMU_AUD_AUDIF0_USER,
|
||
|
|
MUX_CLKCMU_AUD_AUDIF1_USER,
|
||
|
|
MUX_CLKVTS_AUD_DMIC0_USER,
|
||
|
|
MUX_CLKVTS_AUD_DMIC1_USER,
|
||
|
|
MUX_CLKCMU_BRP_NOC_USER,
|
||
|
|
MUX_CLKALIVE_CHUB_NOC_USER,
|
||
|
|
MUX_CLKALIVE_CHUB_PERI_USER,
|
||
|
|
MUX_CLKALIVE_CHUB_RCO_USER,
|
||
|
|
MUX_CLKALIVE_CHUBVTS_NOC_USER,
|
||
|
|
MUX_CLKALIVE_CHUBVTS_RCO_USER,
|
||
|
|
MUX_CLKALIVE_CMGP_NOC_USER,
|
||
|
|
MUX_CLKALIVE_CMGP_PERI_USER,
|
||
|
|
MUX_CP_MPLL_CLK_USER,
|
||
|
|
MUX_CP_MPLL_CLK_D2_USER,
|
||
|
|
MUX_CLKCMU_CPUCL0_SWITCH_USER,
|
||
|
|
MUX_CLKCMU_CPUCL0_DBG_NOC_USER,
|
||
|
|
MUX_CLKCMU_CPUCL0_GLB_NOCP_USER,
|
||
|
|
MUX_CLKCMU_CPUCL1_SWITCH_USER,
|
||
|
|
MUX_CLKCMU_CPUCL2_SWITCH_USER,
|
||
|
|
MUX_CLKCMU_CSIS_DCPHY_USER,
|
||
|
|
MUX_CLKALIVE_CSIS_RCO_USER,
|
||
|
|
MUX_CLKCMU_CSIS_NOC_USER,
|
||
|
|
MUX_CLKALIVE_CSIS_NOC_USER,
|
||
|
|
MUX_CLKCMU_CSIS_OIS_MCU_USER,
|
||
|
|
MUX_CLKCMU_CSTAT_NOC_USER,
|
||
|
|
MUX_CLKALIVE_DBGCORE_NOC_USER,
|
||
|
|
MUX_CLKCMU_DNC_NOC_USER,
|
||
|
|
MUX_CLKALIVE_DNC_RCO_USER,
|
||
|
|
MUX_CLKALIVE_DNC_NOC_USER,
|
||
|
|
MUX_CLKCMU_DPUB_NOC_USER,
|
||
|
|
MUX_CLKCMU_DPUB_DSIM_USER,
|
||
|
|
MUX_CLKCMU_DPUF_NOC_USER,
|
||
|
|
MUX_CLKCMU_DPUF1_NOC_USER,
|
||
|
|
MUX_CLKCMU_DRCP_NOC_USER,
|
||
|
|
MUX_CLKCMU_DSP_NOC_USER,
|
||
|
|
MUX_CLKALIVE_SDMA_RCO_USER_CPY,
|
||
|
|
MUX_CLKALIVE_SDMA_NOC_USER_CPY,
|
||
|
|
MUX_CLKCMU_DSU_SWITCH_USER,
|
||
|
|
MUX_CLKCMU_G3D_NOCP_USER,
|
||
|
|
MUX_CLKCMU_G3D_SWITCH_USER,
|
||
|
|
MUX_CLKCMU_GNPU_NOC_USER,
|
||
|
|
MUX_CLKALIVE_GNPU_NOC_USER,
|
||
|
|
MUX_CLKALIVE_GNPU_RCO_USER,
|
||
|
|
MUX_CLKCMU_HSI0_DPOSC_USER,
|
||
|
|
MUX_CLKCMU_HSI0_NOC_USER,
|
||
|
|
MUX_CLKCMU_HSI0_USB32DRD_USER,
|
||
|
|
MUX_CLKCMU_HSI0_DPGTC_USER,
|
||
|
|
MUX_CLKAUD_HSI0_NOC_USER,
|
||
|
|
MUX_CLKCMU_HSI1_NOC_USER,
|
||
|
|
MUX_CLKCMU_HSI1_PCIE_USER,
|
||
|
|
MUX_CLKCMU_LME_NOC_USER,
|
||
|
|
MUX_CLKCMU_LME_LME_USER,
|
||
|
|
MUX_CLKCMU_M2M_NOC_USER,
|
||
|
|
MUX_CLKCMU_M2M_FRC_USER,
|
||
|
|
MUX_CLKCMU_MCSC_NOC_USER,
|
||
|
|
MUX_CLKCMU_MCSC_MCSC_USER,
|
||
|
|
MUX_CLKCMU_MFC0_MFC0_USER,
|
||
|
|
MUX_CLKCMU_MFC0_WFD_USER,
|
||
|
|
MUX_CLKCMU_MFC1_MFC1_USER,
|
||
|
|
MUX_CLKCMU_MIF_NOCP_USER,
|
||
|
|
CLKMUX_MIF_DDRPHY2X,
|
||
|
|
MUX_CLKCMU_NOCL0_NOC_USER,
|
||
|
|
MUX_CLKCMU_NOCL1A_NOC_USER,
|
||
|
|
MUX_CLKCMU_NOCL1B_NOC0_USER,
|
||
|
|
MUX_CLKCMU_NOCL1B_NOC1_USER,
|
||
|
|
MUX_CLKCMU_NOCL1C_NOC_USER,
|
||
|
|
MUX_CLKCMU_PERIC0_NOC_USER,
|
||
|
|
MUX_CLKCMU_PERIC0_IP0_USER,
|
||
|
|
MUX_CLKCMU_PERIC0_IP1_USER,
|
||
|
|
MUX_CLKCMU_PERIC1_NOC_USER,
|
||
|
|
MUX_CLKCMU_PERIC1_IP0_USER,
|
||
|
|
MUX_CLKCMU_PERIC1_IP1_USER,
|
||
|
|
MUX_CLKCMU_PERIC2_IP0_USER,
|
||
|
|
MUX_CLKCMU_PERIC2_IP1_USER,
|
||
|
|
MUX_CLKCMU_PERIC2_NOC_USER,
|
||
|
|
MUX_CLKCMU_PERIS_NOC_USER,
|
||
|
|
MUX_CLKCMU_PERIS_GIC_USER,
|
||
|
|
CLKCMU_MIF_DDRPHY2X_S2D,
|
||
|
|
MUX_CLKCMU_SDMA_NOC_USER,
|
||
|
|
MUX_CLKALIVE_SDMA_RCO_USER,
|
||
|
|
MUX_CLKALIVE_SDMA_NOC_USER,
|
||
|
|
MUX_CLKCMU_SSP_NOC_USER,
|
||
|
|
MUX_CLKALIVE_UFD_NOC_USER,
|
||
|
|
MUX_CLKALIVE_UFD_RCO_USER,
|
||
|
|
MUX_CLKCMU_UFS_UFS_EMBD_USER,
|
||
|
|
MUX_CLKCMU_UFS_NOC_USER,
|
||
|
|
MUX_CLKCMU_UFS_MMC_CARD_USER,
|
||
|
|
MUX_CLKALIVE_VTS_NOC_USER,
|
||
|
|
MUX_CLKCMU_VTS_DMIC_USER,
|
||
|
|
MUX_CLKALIVE_VTS_RCO_USER,
|
||
|
|
MUX_CLKCMU_YUVP_NOC_USER,
|
||
|
|
MUX_HCHGEN_CLK_AUD_CPU = ((MASK_OF_ID & MUX_CLKCMU_YUVP_NOC_USER) | CONST_MUX_TYPE) + 1,
|
||
|
|
MUX_CLK_CPUCL0_STRMUX,
|
||
|
|
MUX_CLK_CPUCL1_STRMUX_0,
|
||
|
|
MUX_CLK_CPUCL1_STRMUX_1,
|
||
|
|
MUX_CLK_CPUCL1_STRMUX_2,
|
||
|
|
MUX_CLK_CPUCL2_STRMUX,
|
||
|
|
MUX_CLK_DBGCORE_NOC,
|
||
|
|
MUX_OSCCLK_DBGCORE,
|
||
|
|
MUX_FREE_OSCCLK_DBGCORE,
|
||
|
|
MUX_CLK_DSU_STRMUX,
|
||
|
|
MUX_CLK_G3D_STRMUX,
|
||
|
|
MUX_CLK_PERIS_GIC,
|
||
|
|
end_of_mux,
|
||
|
|
num_of_mux = (end_of_mux - MUX_TYPE) & MASK_OF_ID,
|
||
|
|
|
||
|
|
CLKALIVE_UFD_NOC = DIV_TYPE,
|
||
|
|
DIV_CLK_ALIVE_NOC,
|
||
|
|
CLKALIVE_CMGP_NOC,
|
||
|
|
DIV_CLK_ALIVE_SPMI,
|
||
|
|
CLKALIVE_CMGP_PERI,
|
||
|
|
DIV_CLK_ALIVE_DBGCORE_UART,
|
||
|
|
CLKALIVE_CHUB_PERI,
|
||
|
|
CLKALIVE_DBGCORE_NOC,
|
||
|
|
CLKALIVE_DNC_NOC,
|
||
|
|
CLKALIVE_GNPU_NOC,
|
||
|
|
CLKALIVE_SDMA_NOC,
|
||
|
|
DIV_CLK_ALIVE_PMU_SUB,
|
||
|
|
CLKALIVE_CHUBVTS_NOC,
|
||
|
|
CLKALIVE_CSIS_NOC,
|
||
|
|
CLKALIVE_DSP_NOC,
|
||
|
|
DIV_CLK_AUD_CPU_PCLKDBG,
|
||
|
|
DIV_CLK_AUD_DSIF,
|
||
|
|
DIV_CLK_AUD_UAIF0,
|
||
|
|
DIV_CLK_AUD_UAIF1,
|
||
|
|
DIV_CLK_AUD_UAIF2,
|
||
|
|
DIV_CLK_AUD_UAIF3,
|
||
|
|
DIV_CLK_AUD_CPU_ACLK,
|
||
|
|
DIV_CLK_AUD_NOC,
|
||
|
|
DIV_CLK_AUD_NOCP,
|
||
|
|
DIV_CLK_AUD_CNT,
|
||
|
|
DIV_CLK_AUD_UAIF4,
|
||
|
|
DIV_CLK_AUD_UAIF5,
|
||
|
|
DIV_CLK_AUD_UAIF6,
|
||
|
|
CLKAUD_HSI0_NOC,
|
||
|
|
DIV_CLK_AUD_PCMC,
|
||
|
|
DIV_CLK_AUD_AUDIF,
|
||
|
|
DIV_CLK_AUD_SERIAL_LIF,
|
||
|
|
DIV_CLK_AUD_SERIAL_LIF_CORE,
|
||
|
|
CLK_AUD_MCLK,
|
||
|
|
DIV_CLK_AUD_CPU_ACP,
|
||
|
|
DIV_CLK_BRP_NOCP,
|
||
|
|
CLK_BRP_ADD_CH_CLK,
|
||
|
|
DIV_CLK_CHUB_NOC,
|
||
|
|
DIV_CLK_CHUB_USI0,
|
||
|
|
DIV_CLK_CHUB_USI1,
|
||
|
|
DIV_CLK_CHUB_USI3,
|
||
|
|
DIV_CLK_CHUB_I2C,
|
||
|
|
DIV_CLK_CHUB_USI2,
|
||
|
|
DIV_CLK_CHUB_SPI_MS_CTRL,
|
||
|
|
DIV_CLK_CHUB_SPI_I2C0,
|
||
|
|
DIV_CLK_CHUB_SPI_I2C1,
|
||
|
|
DIV_CLK_CHUBVTS_NOC,
|
||
|
|
DIV_CLK_CHUBVTS_DMAILBOX_CCLK,
|
||
|
|
DIV_CLK_CMGP_USI4,
|
||
|
|
DIV_CLK_CMGP_USI1,
|
||
|
|
DIV_CLK_CMGP_USI0,
|
||
|
|
DIV_CLK_CMGP_USI2,
|
||
|
|
DIV_CLK_CMGP_USI3,
|
||
|
|
DIV_CLK_CMGP_USI5,
|
||
|
|
DIV_CLK_CMGP_USI6,
|
||
|
|
DIV_CLK_CMGP_I2C,
|
||
|
|
DIV_CLK_CMGP_SPI_MS_CTRL,
|
||
|
|
DIV_CLK_CMGP_SPI_I2C0,
|
||
|
|
DIV_CLK_CMGP_SPI_I2C1,
|
||
|
|
CLKCMU_ALIVE_NOC,
|
||
|
|
CLKCMU_HSI0_DPOSC,
|
||
|
|
CLKCMU_PERIC0_NOC,
|
||
|
|
CLKCMU_PERIS_NOC,
|
||
|
|
DIV_CLKCMU_DPUF_ALT,
|
||
|
|
CLKCMU_MFC0_MFC0,
|
||
|
|
DIV_CLKCMU_DSP_NOC_SM,
|
||
|
|
CLKCMU_PERIC1_NOC,
|
||
|
|
DIV_CLKCMU_CPUCL0_SWITCH_SM,
|
||
|
|
DIV_CLKCMU_NOCL0_NOC_SM,
|
||
|
|
CLKCMU_BRP_NOC,
|
||
|
|
CLKCMU_YUVP_NOC,
|
||
|
|
DIV_CLKCMU_AUD_CPU_SM,
|
||
|
|
DIV_CLKCMU_CPUCL0_DBG_NOC_SM,
|
||
|
|
DIV_CLKCMU_CIS_CLK0,
|
||
|
|
DIV_CLKCMU_CIS_CLK1,
|
||
|
|
DIV_CLKCMU_CIS_CLK2,
|
||
|
|
DIV_CLKCMU_CIS_CLK3,
|
||
|
|
CLKCMU_CMU_BOOST_MIF,
|
||
|
|
DIV_CLKCMU_GNPU_NOC_SM,
|
||
|
|
CLKCMU_MFC0_WFD,
|
||
|
|
CLKCMU_MIF_NOCP,
|
||
|
|
CLKCMU_PERIC0_IP0,
|
||
|
|
CLKCMU_PERIC1_IP0,
|
||
|
|
DIV_CLKCMU_DPUF,
|
||
|
|
DIV_CLKCMU_CPUCL1_SWITCH_SM,
|
||
|
|
CLKCMU_HSI0_NOC,
|
||
|
|
DIV_CLKCMU_CIS_CLK4,
|
||
|
|
CLKCMU_CMU_BOOST,
|
||
|
|
CLKCMU_CSIS_NOC,
|
||
|
|
DIV_CLKCMU_MCSC_NOC_SM,
|
||
|
|
CLKCMU_HSI1_NOC,
|
||
|
|
CLKCMU_CSIS_OIS_MCU,
|
||
|
|
DIV_CLKCMU_CIS_CLK5,
|
||
|
|
CLKCMU_CMU_BOOST_CPU,
|
||
|
|
DIV_CLKCMU_M2M_NOC_SM,
|
||
|
|
DIV_CLKCMU_DPUB_ALT,
|
||
|
|
DIV_CLKCMU_DPUB,
|
||
|
|
CLKCMU_MFC1_MFC1,
|
||
|
|
CLKCMU_LME_NOC,
|
||
|
|
DIV_CLKCMU_NOCL1A_NOC_SM,
|
||
|
|
CLKCMU_HSI0_USB32DRD,
|
||
|
|
CLKCMU_HSI0_DPGTC,
|
||
|
|
CLKCMU_AUD_NOC,
|
||
|
|
CLKCMU_CSIS_DCPHY,
|
||
|
|
DIV_CP_SHARED0_CLK_SM,
|
||
|
|
CP_SHARED1_CLK,
|
||
|
|
DIV_CP_HISPEEDY_CLK_SM,
|
||
|
|
CLKCMU_PERIC0_IP1,
|
||
|
|
CLKCMU_PERIC1_IP1,
|
||
|
|
CLKCMU_SSP_NOC,
|
||
|
|
DIV_CLKCMU_G3D_SWITCH_SM,
|
||
|
|
CLKCMU_PERIC2_NOC,
|
||
|
|
CLKCMU_PERIC2_IP0,
|
||
|
|
CLKCMU_PERIC2_IP1,
|
||
|
|
CLKCMU_CPUCL0_NOCP,
|
||
|
|
DIV_CLKCMU_DSU_SWITCH_SM,
|
||
|
|
CLKCMU_G3D_NOCP,
|
||
|
|
CLKCMU_CSTAT_NOC,
|
||
|
|
CLKCMU_DPUB_DSIM,
|
||
|
|
DIV_CLKCMU_DNC_NOC_SM,
|
||
|
|
DIV_CLKCMU_CPUCL2_SWITCH_SM,
|
||
|
|
DIV_CLKCMU_SDMA_NOC_SM,
|
||
|
|
DIV_CP_SHARED2_CLK_SM,
|
||
|
|
DIV_CLKCMU_CIS_CLK6,
|
||
|
|
DIV_CLKCMU_NOCL1C_NOC_SM,
|
||
|
|
DIV_CLKCMU_NOCL1B_NOC0_SM,
|
||
|
|
CLKCMU_CMU_BOOST_CAM,
|
||
|
|
CLKCMU_VTS_DMIC,
|
||
|
|
DIV_CLKCMU_AUD_AUDIF0_SM,
|
||
|
|
DIV_CLKCMU_AUD_AUDIF1_SM,
|
||
|
|
CLKCMU_PERIS_GIC,
|
||
|
|
DIV_CLKCMU_CIS_CLK7,
|
||
|
|
CLKCMU_NOCL1B_NOC1,
|
||
|
|
CLKCMU_LME_LME,
|
||
|
|
DIV_CLKCMU_M2M_FRC_SM,
|
||
|
|
DIV_CLKCMU_MCSC_MCSC_SM,
|
||
|
|
CLKCMU_UFS_UFS_EMBD,
|
||
|
|
DIV_CLKCMU_UFS_MMC_CARD_SM,
|
||
|
|
CLKCMU_UFS_NOC,
|
||
|
|
DIV_CLKCMU_AUD_CPU,
|
||
|
|
DIV_CLKCMU_AUD_AUDIF0,
|
||
|
|
DIV_CLKCMU_AUD_AUDIF1,
|
||
|
|
DIV_CLKCMU_CPUCL0_SWITCH,
|
||
|
|
DIV_CLKCMU_CPUCL1_SWITCH,
|
||
|
|
DIV_CLKCMU_CPUCL2_SWITCH,
|
||
|
|
DIV_CLKCMU_DSU_SWITCH,
|
||
|
|
DIV_CLKCMU_CPUCL0_DBG_NOC,
|
||
|
|
DIV_CLKCMU_DNC_NOC,
|
||
|
|
DIV_CLKCMU_SDMA_NOC,
|
||
|
|
DIV_CLKCMU_DSP_NOC,
|
||
|
|
DIV_CLKCMU_G3D_SWITCH,
|
||
|
|
DIV_CLKCMU_GNPU_NOC,
|
||
|
|
DIV_CLKCMU_M2M_NOC,
|
||
|
|
DIV_CLKCMU_M2M_FRC,
|
||
|
|
DIV_CLKCMU_MCSC_NOC,
|
||
|
|
DIV_CLKCMU_MCSC_MCSC,
|
||
|
|
DIV_CLKCMU_NOCL0_NOC,
|
||
|
|
DIV_CLKCMU_NOCL1A_NOC,
|
||
|
|
DIV_CLKCMU_NOCL1B_NOC0,
|
||
|
|
DIV_CLKCMU_NOCL1C_NOC,
|
||
|
|
DIV_CP_HISPEEDY_CLK,
|
||
|
|
DIV_CP_SHARED2_CLK,
|
||
|
|
DIV_CP_SHARED0_CLK,
|
||
|
|
DIV_CLKCMU_UFS_MMC_CARD,
|
||
|
|
CLK_CPUCL0_ADD_CH_CLK,
|
||
|
|
CLK_CPUCL0_DDD,
|
||
|
|
DIV_CLK_CPUCL0_DBG_NOC,
|
||
|
|
DIV_CLK_CPUCL0_DBG_PCLKDBG,
|
||
|
|
CLK_CPUCL1_ADD_CH_CLK,
|
||
|
|
CLK_CPUCL1_DDD_0,
|
||
|
|
DIV_CLK_CPUCL1_CORE_1,
|
||
|
|
CLK_CPUCL1_DDD_1,
|
||
|
|
DIV_CLK_CPUCL1_CORE_2,
|
||
|
|
CLK_CPUCL1_DDD_2,
|
||
|
|
CLK_CPUCL2_ADD_CH_CLK,
|
||
|
|
CLK_CPUCL2_DDD,
|
||
|
|
DIV_CLK_CSIS_NOCP,
|
||
|
|
DIV_CLK_CSIS_DCPHY,
|
||
|
|
DIV_CLK_CSTAT_NOCP,
|
||
|
|
DIV_CLK_DNC_NOCP,
|
||
|
|
CLK_DNC_ADD_CH_CLK,
|
||
|
|
DIV_CLK_DPUB_NOCP,
|
||
|
|
DIV_CLK_DPUF_NOCP,
|
||
|
|
DIV_CLK_DPUF1_NOCP,
|
||
|
|
DIV_CLK_DRCP_NOCP,
|
||
|
|
DIV_CLK_DSP_NOCP,
|
||
|
|
DIV_CLK_CLUSTER_ACLK,
|
||
|
|
DIV_CLK_CLUSTER_ATCLK,
|
||
|
|
CLK_DSU_DDD,
|
||
|
|
CLK_DSU_STR_DEM_CLK,
|
||
|
|
DIV_CLK_CLUSTER_ACPCLK,
|
||
|
|
DIV_CLK_CLUSTER_MPCLK,
|
||
|
|
DIV_CLK_CLUSTER_MPACTCLK,
|
||
|
|
CLK_G3D_ADD_CH_CLK,
|
||
|
|
CLK_G3D_DDD,
|
||
|
|
DIV_CLK_GNPU_NOCP,
|
||
|
|
DIV_CLK_HSI0_EUSB,
|
||
|
|
DIV_CLK_LME_NOCP,
|
||
|
|
DIV_CLK_M2M_NOCP,
|
||
|
|
DIV_CLK_MCSC_NOCP,
|
||
|
|
DIV_CLK_MFC0_NOCP,
|
||
|
|
DIV_CLK_MFC1_NOCP,
|
||
|
|
DIV_CLK_NOCL0_NOCP,
|
||
|
|
DIV_CLK_NOCL1A_NOCP,
|
||
|
|
DIV_CLK_NOCL1B_NOCP,
|
||
|
|
DIV_CLK_NOCL1C_NOCP,
|
||
|
|
DIV_CLK_PERIC0_USI04,
|
||
|
|
DIV_CLK_PERIC0_I2C,
|
||
|
|
DIV_CLK_PERIC1_UART_BT,
|
||
|
|
DIV_CLK_PERIC1_I2C,
|
||
|
|
DIV_CLK_PERIC1_USI07,
|
||
|
|
DIV_CLK_PERIC1_USI08,
|
||
|
|
DIV_CLK_PERIC1_USI09,
|
||
|
|
DIV_CLK_PERIC1_USI10,
|
||
|
|
DIV_CLK_PERIC1_SPI_MS_CTRL,
|
||
|
|
DIV_CLK_PERIC1_USI07_SPI_I2C,
|
||
|
|
DIV_CLK_PERIC1_USI08_SPI_I2C,
|
||
|
|
DIV_CLK_PERIC2_I2C,
|
||
|
|
DIV_CLK_PERIC2_USI00,
|
||
|
|
DIV_CLK_PERIC2_USI01,
|
||
|
|
DIV_CLK_PERIC2_USI02,
|
||
|
|
DIV_CLK_PERIC2_USI03,
|
||
|
|
DIV_CLK_PERIC2_USI05,
|
||
|
|
DIV_CLK_PERIC2_USI06,
|
||
|
|
DIV_CLK_PERIC2_SPI_MS_CTRL,
|
||
|
|
DIV_CLK_PERIC2_USI11,
|
||
|
|
DIV_CLK_PERIC2_UART_DBG,
|
||
|
|
DIV_CLK_PERIC2_USI00_SPI_I2C,
|
||
|
|
DIV_CLK_PERIC2_USI01_SPI_I2C,
|
||
|
|
DIV_CLK_SDMA_NOCP,
|
||
|
|
DIV_CLK_SSP_NOCP,
|
||
|
|
DIV_CLK_VTS_DMIC_IF,
|
||
|
|
DIV_CLK_VTS_DMIC_IF_DIV2,
|
||
|
|
DIV_CLK_VTS_NOC,
|
||
|
|
DIV_CLK_VTS_SERIAL_LIF,
|
||
|
|
DIV_CLK_VTS_SERIAL_LIF_CORE,
|
||
|
|
DIV_CLK_VTS_CPU,
|
||
|
|
DIV_CLKVTS_AUD_DMIC0,
|
||
|
|
DIV_CLKVTS_AUD_DMIC1,
|
||
|
|
DIV_CLK_YUVP_NOCP,
|
||
|
|
DIV_CLK_BRP_NOC = ((MASK_OF_ID & DIV_CLK_YUVP_NOCP) | CONST_DIV_TYPE) + 1,
|
||
|
|
DIV_CLK_CPUCL0_CORE,
|
||
|
|
DIV_CLK_CPUCL1_CORE_0,
|
||
|
|
DIV_CLK_CPUCL2_CORE,
|
||
|
|
DIV_CLK_DNC_NOC,
|
||
|
|
DIV_CLK_DRCP_NOC,
|
||
|
|
DIV_CLK_DSP_NOC,
|
||
|
|
DIV_CLK_DSU_CLUSTER,
|
||
|
|
DIV_CLK_G3D_CORE,
|
||
|
|
DIV_CLK_GNPU_NOC,
|
||
|
|
DIV_CLK_MCSC_NOC,
|
||
|
|
DIV_CLK_MCSC_MCSC,
|
||
|
|
DIV_CLK_SDMA_NOC,
|
||
|
|
DIV_CLK_YUVP_NOC,
|
||
|
|
end_of_div,
|
||
|
|
num_of_div = (end_of_div - DIV_TYPE) & MASK_OF_ID,
|
||
|
|
|
||
|
|
GATE_CLKALIVE_UFD_NOC = GATE_TYPE,
|
||
|
|
CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK,
|
||
|
|
GATE_CLKALIVE_CMGP_NOC,
|
||
|
|
GATE_CLKALIVE_CMGP_PERI,
|
||
|
|
CLK_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALIVE_UID_RTC_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2AP_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2APM_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2PMU_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALIVE_UID_TOP_RTC_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALIVE_UID_CLKMON_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALIVE_UID_DTZPC_ALIVE_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK,
|
||
|
|
CLK_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_ALIVE_UID_SPMI_MASTER_PMIC_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_ALIVE_UID_SLH_AXI_MI_LP_MODEM_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_ALIVE_UID_SLH_AXI_MI_LD_CHUBVTS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_ALIVE_UID_SLH_AXI_MI_P_APM_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_CMGP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_ALIVE_UID_LH_AXI_SI_D_APM_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_CHUBVTS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_SPMI_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_NOC_IPCLKPORT_CLK,
|
||
|
|
GATE_CLKALIVE_CHUB_PERI,
|
||
|
|
CLK_BLK_ALIVE_UID_CHUB_RTC_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALIVE_UID_SLH_AXI_MI_LD_GNSS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_ALIVE_UID_MAILBOX_APM_CHUB_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALIVE_UID_MAILBOX_APM_GNSS_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALIVE_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALIVE_UID_MAILBOX_AP_CHUB_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALIVE_UID_MAILBOX_AP_GNSS_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALIVE_UID_MAILBOX_CP_CHUB_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALIVE_UID_MAILBOX_CP_GNSS_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALIVE_UID_MAILBOX_GNSS_CHUB_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALIVE_UID_MAILBOX_SHARED_SRAM_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALIVE_UID_MAILBOX_APM_AUD_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_PPU_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_ALIVE_UID_INTMEM_IPCLKPORT_I_ACLK,
|
||
|
|
CLK_BLK_ALIVE_UID_PMU_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_ALIVE_UID_SLH_AXI_SI_IP_APM_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_ALIVE_UID_SLH_AXI_MI_ID_DBGCORE_IPCLKPORT_I_CLK,
|
||
|
|
GATE_CLKALIVE_DBGCORE_NOC,
|
||
|
|
GATE_CLKALIVE_DNC_NOC,
|
||
|
|
CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_TIMER_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_ALIVEDNC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_ALIVE_UID_SPC_ALIVE_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALIVE_UID_APM_DMA_IPCLKPORT_PCLK,
|
||
|
|
GATE_CLKALIVE_GNPU_NOC,
|
||
|
|
CLK_BLK_ALIVE_UID_INTMEM_IPCLKPORT_I_PCLK,
|
||
|
|
CLKALIVE_GNSS_NOC,
|
||
|
|
CLKALIVE_UFD_RCO,
|
||
|
|
CLKALIVE_DNC_RCO,
|
||
|
|
CLKALIVE_GNPU_RCO,
|
||
|
|
GATE_CLKALIVE_SDMA_NOC,
|
||
|
|
CLKALIVE_SDMA_RCO,
|
||
|
|
CLK_BLK_ALIVE_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALIVE_UID_PMU_IPCLKPORT_CLKIN_PMU_SUB,
|
||
|
|
CLK_BLK_ALIVE_UID_MCT_ALIVE_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_ALIVE_UID_TOP_RTC_IPCLKPORT_OSCCLK,
|
||
|
|
CLK_BLK_ALIVE_UID_CHUB_RTC_IPCLKPORT_OSCCLK,
|
||
|
|
CLK_BLK_ALIVE_UID_SPMI_MASTER_PMIC_IPCLKPORT_I_IPCLK,
|
||
|
|
CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_NOC_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_FREE_OSCCLK_IPCLKPORT_CLK,
|
||
|
|
CLKALIVE_CHUBVTS_RCO,
|
||
|
|
GATE_CLKALIVE_CHUBVTS_NOC,
|
||
|
|
GATE_CLKALIVE_CSIS_NOC,
|
||
|
|
CLKALIVE_CSIS_RCO,
|
||
|
|
GATE_CLKALIVE_DSP_NOC,
|
||
|
|
CLKALIVE_DSP_RCO,
|
||
|
|
CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_FREE_OSCCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_ALIVE_UID_MAILBOX_APM_CP_1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_SPMI_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_ALIVE_UID_BLK_ALIVE_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_ALIVE_UID_OTP_DESERIAL_ALIVE_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_ALIVE_UID_OTP_HCU_DESERIAL_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_AD_APB_CSIS_WDMA_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_DMA,
|
||
|
|
CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_MCB_EBUF_BNS,
|
||
|
|
CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF0,
|
||
|
|
CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF1,
|
||
|
|
CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_C2CLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_CLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF_CSISBRP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_LH_AST_MI_OTF0_BRPCSIS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF0_CSISCSTAT_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_LH_AST_MI_OTF1_BRPCSIS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF1_CSISCSTAT_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF2_CSISCSTAT_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF3_CSISCSTAT_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D2_CSIS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_OIS_MCU_TOP_IPCLKPORT_I_ACLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_PPMU_D0_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_PPMU_D0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_PPMU_D1_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_PPMU_D1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_PPMU_D2_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_PPMU_D2_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA0_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA1_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA2_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA2_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA3_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA3_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA4_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA4_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_QE_PDP_D0_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_QE_PDP_D0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_SIU_G_PPMU_CSIS_IPCLKPORT_I_ACLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_SLH_AST_SI_G_PPMU_CSIS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_XIU_P0_CSIS_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_SLH_AXI_SI_LP_CSISPERIC2_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1,
|
||
|
|
CLK_BLK_ALLCSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_ALLCSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1,
|
||
|
|
CLK_BLK_ALLCSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_ALLCSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1,
|
||
|
|
CLK_BLK_ALLCSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_ALLCSIS_UID_VGEN_LITE_D0_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_VGEN_LITE_D1_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_CPU_SW_RESET_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_OIS_MCU_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_LH_AXI_SI_LP_INT_P0OIS_CSIS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_LH_AXI_SI_LP_INT_P0P1_CSIS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_LH_AXI_MI_LP_INT_P0OIS_CSIS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_ALLCSIS_CMU_ALLCSIS_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_ALLCSIS_UID_BLK_CSIS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ,
|
||
|
|
CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT,
|
||
|
|
CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF,
|
||
|
|
CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0,
|
||
|
|
CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1,
|
||
|
|
CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2,
|
||
|
|
CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3,
|
||
|
|
CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4,
|
||
|
|
CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5,
|
||
|
|
CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6,
|
||
|
|
CLK_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK,
|
||
|
|
CLK_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK,
|
||
|
|
CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB,
|
||
|
|
CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32,
|
||
|
|
CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP,
|
||
|
|
CLK_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK,
|
||
|
|
CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK0,
|
||
|
|
CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_NS1_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_S_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_AUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_AUD_UID_BAAW_D_AUDCHUBVTS_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_AUD_UID_SLH_AXI_MI_LD_HSI0AUD_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_AUD_UID_SLH_AXI_MI_P_AUD_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_AUD_UID_LH_QDI_SI_D_AUD_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_AUD_UID_SLH_AXI_SI_LP_AUDCHUBVTS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_AUD_UID_MAILBOX_AUD2_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_AUD_UID_MAILBOX_AUD3_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CNT_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF4_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF5_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF6_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S1,
|
||
|
|
CLK_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_AUD_UID_TREX_AUD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_TREX_AUD_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK1,
|
||
|
|
CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK2,
|
||
|
|
CLK_BLK_AUD_UID_SLH_AXI_SI_LD_AUDHSI0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU2_SW_RESET_IPCLKPORT_CLK,
|
||
|
|
GATE_CLKAUD_HSI0_NOC,
|
||
|
|
CLK_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_AD_APB_VGEN_LITE_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_CCLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SERIAL_LIF_CORE_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SERIAL_LIF_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK,
|
||
|
|
CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_BCLK,
|
||
|
|
CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_AUD_UID_SLH_AST_SI_G_PPMU_AUD_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK,
|
||
|
|
CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK,
|
||
|
|
CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK,
|
||
|
|
CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK,
|
||
|
|
CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_CLK,
|
||
|
|
CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_DIV2_CLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DMIC0_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DMIC1_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DSIF_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF0_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF1_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF2_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF3_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF4_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF5_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF6_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_SERIAL_LIF_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_SERIAL_LIF_CORE_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DMIC0_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DMIC1_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CNT_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FREE_OSCCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_FREE_OSCCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ACP,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_BLK_AUD_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_AUD_UID_LH_AXI_SI_PERI_ASB_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_AUD_UID_LH_AXI_MI_PERI_ASB_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CPU_ACP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ACP,
|
||
|
|
CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ASB,
|
||
|
|
CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_CCLK,
|
||
|
|
CLK_BLK_BRP_UID_BRP_CMU_BRP_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_BRP_UID_AD_APB_BYRP_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_BRP_UID_D_TZPC_BRP_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_BRP_UID_LH_AXI_SI_D0_BRP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_BRP_UID_PPMU_D0_BRP_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_BRP_UID_PPMU_D0_BRP_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_BRP_UID_SYSMMU_D0_BRP_IPCLKPORT_CLK_S1,
|
||
|
|
CLK_BLK_BRP_UID_SYSREG_BRP_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_BRP_UID_XIU_D0_BRP_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_BRP_UID_SLH_AXI_MI_P_BRP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_C2S_ZSL,
|
||
|
|
CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_C2S_BYR,
|
||
|
|
CLK_BLK_BRP_UID_SYSMMU_D0_BRP_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_BRP_UID_VGEN_LITE_BYRP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_BRP_UID_SLH_AST_SI_G_PPMU_BRP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_BRP_UID_AD_APB_RGBP_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_BRP_UID_LH_AXI_SI_D1_BRP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_BRP_UID_LH_AXI_SI_D2_BRP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_BRP_UID_SYSMMU_D2_BRP_IPCLKPORT_CLK_S1,
|
||
|
|
CLK_BLK_BRP_UID_SYSMMU_D2_BRP_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_BRP_UID_SYSMMU_D1_BRP_IPCLKPORT_CLK_S1,
|
||
|
|
CLK_BLK_BRP_UID_SYSMMU_D1_BRP_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_BRP_UID_PPMU_D1_BRP_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_BRP_UID_PPMU_D1_BRP_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_BRP_UID_PPMU_D2_BRP_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_BRP_UID_PPMU_D2_BRP_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_VOTF0,
|
||
|
|
CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_VOTF1,
|
||
|
|
CLK_BLK_BRP_UID_XIU_D1_BRP_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_BRP_UID_XIU_D2_BRP_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_BRP_UID_VGEN_LITE_RGBP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_BRP_UID_LH_AST_SI_OTF0_BRPCSIS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_BRP_UID_LH_AST_MI_OTF_CSISBRP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_BRP_UID_LH_AST_SI_OTF1_BRPCSIS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_BRP_UID_LH_AST_SI_OTF_BRPMCSC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_BRP_UID_L_SIU_BRP_IPCLKPORT_I_ACLK,
|
||
|
|
CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_BRP_UID_BLK_BRP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_POWERIP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_BRP_UID_ADD_BRP_IPCLKPORT_CH_CLK,
|
||
|
|
CLK_BLK_BRP_UID_ADD_BRP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_BRP_UID_BUSIF_ADD_BRP_IPCLKPORT_CLK_CORE,
|
||
|
|
CLK_BLK_BRP_UID_BUSIF_ADD_BRP_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_POWERIP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_FREE_OSCCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CHUB_UID_CHUB_CMU_CHUB_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_RTCCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_TIMER_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CHUB_UID_CM4_CHUB_IPCLKPORT_FCLK,
|
||
|
|
CLK_BLK_CHUB_UID_LH_AXI_MI_IP_VC2CHUB_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CHUB_UID_LH_AXI_SI_ID_CHUB2VC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CHUB_UID_PWM_CHUB_IPCLKPORT_I_PCLK_S0,
|
||
|
|
CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_NOC_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CHUB_UID_SYSREG_CHUB_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CHUB_UID_TIMER_CHUB_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CHUB_UID_WDT_CHUB_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI0_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI1_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI2_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI3_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CHUB_UID_I2C_CHUB_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CHUB_UID_I3C_CHUB_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CHUB_UID_I2C_CHUB_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_CHUB_UID_I3C_CHUB_IPCLKPORT_I_SCLK,
|
||
|
|
CLK_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_CHUB_UID_APBIF_CHUB_COMBINE_WAKEUP_SRC_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CHUB_UID_APBIF_GPIO_CHUB_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2AP_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2APM_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CHUB_UID_ASYNCINTERRUPT_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CHUB_UID_MAILBOX_CHUB_DNC_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CHUB_UID_SPI_I2C_CHUB0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CHUB_UID_SPI_I2C_CHUB1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CHUB_UID_SPI_MULTI_SLV_Q_CTRL_CHUB_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_MS_CTRL_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_FREE_OSCCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CHUB_UID_SPI_I2C_CHUB0_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_CHUB_UID_SPI_I2C_CHUB1_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_I2C0_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_I2C1_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CHUB_UID_AHB_BUSMATRIX_CHUB_IPCLKPORT_HCLK,
|
||
|
|
CLK_BLK_CHUB_UID_AXI2AHB_CHUB_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CHUB_UID_MAILBOX_CHUB_ABOX_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_NOC_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_I2C_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_FREE_OSCCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CHUBVTS_UID_CHUBVTS_CMU_CHUBVTS_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CHUBVTS_UID_LH_AXI_SI_IP_VC2VTS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CHUBVTS_UID_LH_AXI_SI_IP_VC2CHUB_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CHUBVTS_UID_SWEEPER_LD_CHUBVTS_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_DNCCHUBVTS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CHUBVTS_UID_BPS_LP_ALIVECHUBVTS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_CCLK,
|
||
|
|
CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_CHUBVTS_UID_LH_AXI_MI_ID_VTS2VC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CHUBVTS_UID_D_TZPC_CHUBVTS_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CHUBVTS_UID_PDMA_CHUBVTS_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_CHUBVTS_UID_LH_AXI_MI_ID_CHUB2VC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_CHUBVTS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CHUBVTS_UID_XIU_DP_CHUBVTS_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_CHUBVTS_UID_APBIF_UPMU_CHUB_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CHUBVTS_UID_SYSREG_CHUBVTS_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CHUBVTS_UID_CHUB_ALV_IPCLKPORT_UPMU_CHUB_ACLK,
|
||
|
|
CLK_BLK_CHUBVTS_UID_CHUB_ALV_IPCLKPORT_RSTNSYNCH_CLK,
|
||
|
|
CLK_BLK_CHUBVTS_UID_SLH_AXI_SI_LD_CHUBVTS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CHUBVTS_UID_VGEN_LITE_CHUBVTS_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CHUBVTS_UID_BPS_LP_DNCCHUBVTS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_AUDCHUBVTS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CHUBVTS_UID_RSTNSYNC_CLK_CHUBVTS_NOC_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CHUBVTS_UID_APB_SEMA_PDMA_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CHUBVTS_UID_APB_SEMA_DMAILBOX_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_NOC_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_FREE_OSCCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CHUBVTS_UID_BLK_CHUBVTS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_DMAILBOX_CCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CHUBVTS_UID_BAAW_LD_CHUBVTS_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_CHUBVTS_UID_MAILBOX_VTS_CHUB_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CHUBVTS_UID_BAAW_CHUB_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CMGP_UID_APBIF_GPIO_CMGP_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CMGP_UID_SPI_I2C_CMGP0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CMGP_UID_SPI_I2C_CMGP1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CMGP_UID_SLH_AXI_MI_LP_CMGP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_NOC_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI4_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI5_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI6_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI0_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI1_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI2_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI3_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_I2C_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_CMGP_UID_I2C_CMGP5_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CMGP_UID_I2C_CMGP6_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CMGP_UID_I2C_CMGP6_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_CMGP_UID_I2C_CMGP5_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_CMGP_UID_USI_CMGP5_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CMGP_UID_USI_CMGP5_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_CMGP_UID_USI_CMGP6_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CMGP_UID_USI_CMGP6_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_CMGP_UID_SPI_MULTI_SLV_Q_CTRL_CMGP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CMGP_UID_SLH_AXI_SI_LP_CMGPUFD_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_MS_CTRL_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_FREE_OSCCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CMGP_UID_SPI_I2C_CMGP0_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_CMGP_UID_SPI_I2C_CMGP1_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_CMGP_UID_CMGP_I2C_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_CMGP_UID_CMGP_I2C_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_I2C0_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_I2C1_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_NOC_IPCLKPORT_CLK,
|
||
|
|
GATE_CLKCMU_ALIVE_NOC,
|
||
|
|
GATE_CLKCMU_HSI0_DPOSC,
|
||
|
|
CLKCMU_MIF01_SWITCH,
|
||
|
|
GATE_CLKCMU_MFC0_MFC0,
|
||
|
|
GATE_CLKCMU_HSI1_NOC,
|
||
|
|
GATE_CLKCMU_DPUF_ALT,
|
||
|
|
GATE_CLKCMU_PERIS_NOC,
|
||
|
|
GATE_CLKCMU_PERIC0_NOC,
|
||
|
|
GATE_CLKCMU_PERIC1_NOC,
|
||
|
|
GATE_CLKCMU_BRP_NOC,
|
||
|
|
GATE_CLKCMU_YUVP_NOC,
|
||
|
|
GATE_CLKCMU_AUD_CPU_SM,
|
||
|
|
GATE_CLKCMU_HSI1_PCIE,
|
||
|
|
GATE_CLKCMU_CIS_CLK0,
|
||
|
|
GATE_CLKCMU_CIS_CLK1,
|
||
|
|
GATE_CLKCMU_CIS_CLK3,
|
||
|
|
GATE_CLKCMU_CIS_CLK2,
|
||
|
|
GATE_CLKCMU_MFC0_WFD,
|
||
|
|
GATE_CLKCMU_MIF_NOCP,
|
||
|
|
GATE_CLKCMU_PERIC0_IP0,
|
||
|
|
GATE_CLKCMU_PERIC1_IP0,
|
||
|
|
GATE_CLKCMU_DPUF,
|
||
|
|
GATE_CLKCMU_HSI0_NOC,
|
||
|
|
GATE_CLKCMU_CIS_CLK4,
|
||
|
|
GATE_CLKCMU_CSIS_NOC,
|
||
|
|
GATE_CLKCMU_MCSC_NOC_SM,
|
||
|
|
GATE_CLKCMU_CSIS_OIS_MCU,
|
||
|
|
GATE_CLKCMU_CIS_CLK5,
|
||
|
|
GATE_CLKCMU_M2M_NOC_SM,
|
||
|
|
GATE_CLKCMU_DPUB_ALT,
|
||
|
|
GATE_CLKCMU_DPUB,
|
||
|
|
GATE_CLKCMU_MFC1_MFC1,
|
||
|
|
GATE_CLKCMU_LME_NOC,
|
||
|
|
GATE_CLKCMU_HSI0_USB32DRD,
|
||
|
|
GATE_CLKCMU_HSI0_DPGTC,
|
||
|
|
GATE_CLKCMU_AUD_NOC,
|
||
|
|
GATE_CLKCMU_CSIS_DCPHY,
|
||
|
|
GATE_CP_SHARED1_CLK,
|
||
|
|
GATE_CLKCMU_PERIC0_IP1,
|
||
|
|
GATE_CLKCMU_PERIC1_IP1,
|
||
|
|
GATE_CLKCMU_SSP_NOC,
|
||
|
|
GATE_CLKCMU_PERIC2_IP0,
|
||
|
|
GATE_CLKCMU_PERIC2_NOC,
|
||
|
|
GATE_CLKCMU_PERIC2_IP1,
|
||
|
|
CLKCMU_MIF23_SWITCH,
|
||
|
|
GATE_CLKCMU_CPUCL0_NOCP,
|
||
|
|
GATE_CLKCMU_G3D_NOCP,
|
||
|
|
GATE_CLKCMU_CSTAT_NOC,
|
||
|
|
GATE_CLKCMU_DPUB_DSIM,
|
||
|
|
GATE_CLKCMU_CIS_CLK6,
|
||
|
|
GATE_CLKCMU_NOCL1A_NOC_SM,
|
||
|
|
GATE_CLKCMU_NOCL0_NOC_SM,
|
||
|
|
GATE_CLKCMU_CPUCL0_SWITCH_SM,
|
||
|
|
GATE_CLKCMU_CPUCL1_SWITCH_SM,
|
||
|
|
GATE_CLKCMU_CPUCL2_SWITCH_SM,
|
||
|
|
GATE_CLKCMU_DSU_SWITCH_SM,
|
||
|
|
GATE_CLKCMU_CPUCL0_DBG_NOC_SM,
|
||
|
|
GATE_CLKCMU_DNC_NOC_SM,
|
||
|
|
GATE_CLKCMU_SDMA_NOC_SM,
|
||
|
|
GATE_CLKCMU_GNPU_NOC_SM,
|
||
|
|
GATE_CLKCMU_DSP_NOC_SM,
|
||
|
|
GATE_CP_SHARED0_CLK_SM,
|
||
|
|
GATE_CP_HISPEEDY_CLK_SM,
|
||
|
|
GATE_CLKCMU_G3D_SWITCH_SM,
|
||
|
|
GATE_CP_SHARED2_CLK_SM,
|
||
|
|
GATE_CLKCMU_NOCL1C_NOC_SM,
|
||
|
|
GATE_CLKCMU_NOCL1B_NOC0_SM,
|
||
|
|
GATE_CLKCMU_CMU_BOOST,
|
||
|
|
GATE_CLKCMU_CMU_BOOST_CPU,
|
||
|
|
GATE_CLKCMU_CMU_BOOST_CPU_MIF,
|
||
|
|
GATE_CLKCMU_CMU_BOOST_CAM,
|
||
|
|
GATE_CLKCMU_VTS_DMIC,
|
||
|
|
GATE_CLKCMU_AUD_AUDIF0_SM,
|
||
|
|
GATE_CLKCMU_AUD_AUDIF1_SM,
|
||
|
|
GATE_CLKCMU_PERIS_GIC,
|
||
|
|
GATE_CLKCMU_CIS_CLK7,
|
||
|
|
GATE_CLKCMU_NOCL1B_NOC1,
|
||
|
|
GATE_CLKCMU_LME_LME,
|
||
|
|
GATE_CLKCMU_M2M_FRC_SM,
|
||
|
|
GATE_CLKCMU_MCSC_MCSC_SM,
|
||
|
|
GATE_CLKCMU_UFS_MMC_CARD_SM,
|
||
|
|
GATE_CLKCMU_UFS_UFS_EMBD,
|
||
|
|
GATE_CLKCMU_UFS_NOC,
|
||
|
|
GATE_CLKCMU_AUD_CPU,
|
||
|
|
GATE_CLKCMU_AUD_AUDIF0,
|
||
|
|
GATE_CLKCMU_AUD_AUDIF1,
|
||
|
|
GATE_CLKCMU_CPUCL0_SWITCH,
|
||
|
|
GATE_CLKCMU_CPUCL1_SWITCH,
|
||
|
|
GATE_CLKCMU_CPUCL2_SWITCH,
|
||
|
|
GATE_CLKCMU_DSU_SWITCH,
|
||
|
|
GATE_CLKCMU_CPUCL0_DBG_NOC,
|
||
|
|
GATE_CLKCMU_DNC_NOC,
|
||
|
|
GATE_CLKCMU_SDMA_NOC,
|
||
|
|
GATE_CLKCMU_DSP_NOC,
|
||
|
|
GATE_CLKCMU_G3D_SWITCH,
|
||
|
|
GATE_CLKCMU_GNPU_NOC,
|
||
|
|
GATE_CLKCMU_M2M_NOC,
|
||
|
|
GATE_CLKCMU_M2M_FRC,
|
||
|
|
GATE_CLKCMU_MCSC_NOC,
|
||
|
|
GATE_CLKCMU_MCSC_MCSC,
|
||
|
|
GATE_CLKCMU_NOCL0_NOC,
|
||
|
|
GATE_CLKCMU_NOCL1A_NOC,
|
||
|
|
GATE_CLKCMU_NOCL1B_NOC0,
|
||
|
|
GATE_CLKCMU_NOCL1C_NOC,
|
||
|
|
GATE_CP_HISPEEDY_CLK,
|
||
|
|
GATE_CP_SHARED2_CLK,
|
||
|
|
GATE_CP_SHARED0_CLK,
|
||
|
|
GATE_CLKCMU_UFS_MMC_CARD,
|
||
|
|
CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_CLK_CORE,
|
||
|
|
CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_CLK_CORE,
|
||
|
|
CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_POWERIP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CH_CLK,
|
||
|
|
CPUCL0_CPM,
|
||
|
|
CLK_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_COMPLEX0CLK,
|
||
|
|
CLK_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_COMPLEX1CLK,
|
||
|
|
CLK_BLK_CPUCL0_UID_STR_CPUCL0_0_IPCLKPORT_DEM_CLK,
|
||
|
|
CLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_HTU_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_POWERIP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_ATCLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_CLUSTER0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_T_BDU_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_DBGCORE_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_CSSYS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_DBGCORE_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_ETR_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_STM_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_LH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_CSSYS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_DBGCORE_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_ETR_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_STM_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_PMU_PCSM_PM_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_BUSIF_DDC_CPUCL0_0_IPCLKPORT_PCLK_S0,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_BUSIF_DDC_CPUCL0_1_IPCLKPORT_PCLK_S0,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCDSU_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_T_DDCG3D_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCLIT_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID2_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCBIG_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_CFM_CPUCL0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_FREE_OSCCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_OTP_DESERIAL_SECJTAG_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_BLK_CPUCL0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_GLB_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_GLB_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_FREE_OSCCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_CLK_CORE,
|
||
|
|
CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_CLK_CORE,
|
||
|
|
CLK_BLK_CPUCL1_UID_HTU_CPUCL1_0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_POWERIP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CPUCL1_UID_RSTNSYNC_SR_CLK_CPUCL1_HTU_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CPUCL1_UID_HTU_CPUCL1_0_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CH_CLK,
|
||
|
|
CPUCL1_CPM0,
|
||
|
|
CPUCL1_CPM1,
|
||
|
|
CPUCL1_CPM2,
|
||
|
|
CLK_BLK_CPUCL1_UID_HTU_CPUCL1_1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CPUCL1_UID_HTU_CPUCL1_1_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_CPUCL1_UID_HTU_CPUCL1_2_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CPUCL1_UID_HTU_CPUCL1_2_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_CPUCL1_UID_STR_CPUCL0_1_IPCLKPORT_DEM_CLK,
|
||
|
|
CLK_BLK_CPUCL1_UID_RSTNSYNC_SR_CLK_CPUCL1_POWERIP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_CLK_CORE,
|
||
|
|
CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_CLK_CORE,
|
||
|
|
CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_POWERIP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CPUCL2_UID_RSTNSYNC_SR_CLK_CPUCL2_HTU_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CH_CLK,
|
||
|
|
CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK,
|
||
|
|
CPUCL2_CPM,
|
||
|
|
CLK_BLK_CPUCL2_UID_STR_CPUCL0_2_IPCLKPORT_DEM_CLK,
|
||
|
|
CLK_BLK_CPUCL2_UID_RSTNSYNC_SR_CLK_CPUCL2_POWERIP_IPCLKPORT_CLK,
|
||
|
|
CLKCSIS_ALLCSIS_NOCD,
|
||
|
|
CLKCSIS_ALLCSIS_NOCP,
|
||
|
|
CLKCSIS_ALLCSIS_OIC_MCU,
|
||
|
|
CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS0,
|
||
|
|
CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS1,
|
||
|
|
CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS2,
|
||
|
|
CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS3,
|
||
|
|
CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS4,
|
||
|
|
CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS5,
|
||
|
|
CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS6,
|
||
|
|
CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_I_FD_ACLK,
|
||
|
|
CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS0,
|
||
|
|
CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS1,
|
||
|
|
CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS2,
|
||
|
|
CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS4,
|
||
|
|
CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS3,
|
||
|
|
CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS5,
|
||
|
|
CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS6,
|
||
|
|
CLK_BLK_CSIS_UID_XIU_P1_CSIS_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_CSIS_UID_AD_APB_MIPI_PHY_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_CSIS_UID_SLH_AXI_MI_LP_UFDCSIS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CSIS_UID_SLH_AST_SI_OTF_CSISUFD_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CSIS_UID_LH_AXI_MI_LP_INT_P0P1_CSIS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_DCPHY_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CSTAT_UID_CSTAT_CMU_CSTAT_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CSTAT_UID_D_TZPC_CSTAT_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CSTAT_UID_AD_APB_CSTAT0_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_CSTAT_UID_SLH_AXI_MI_P_CSTAT_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CSTAT_UID_PPMU_CSTAT_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_CSTAT_UID_PPMU_CSTAT_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CSTAT_UID_SYSMMU_D_CSTAT_IPCLKPORT_CLK_S1,
|
||
|
|
CLK_BLK_CSTAT_UID_LH_AXI_SI_D_CSTAT_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CSTAT_UID_SYSREG_CSTAT_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_CSTAT_UID_XIU_D_CSTAT_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_CSTAT_UID_RSTNSYNC_CLK_CSTAT_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CSTAT_UID_RSTNSYNC_CLK_CSTAT_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CSTAT_UID_LH_AST_MI_OTF0_CSISCSTAT_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CSTAT_UID_LH_AST_MI_OTF1_CSISCSTAT_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CSTAT_UID_LH_AST_MI_OTF2_CSISCSTAT_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CSTAT_UID_LH_AST_MI_OTF3_CSISCSTAT_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_C2RD,
|
||
|
|
CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_C2DS,
|
||
|
|
CLK_BLK_CSTAT_UID_SYSMMU_D_CSTAT_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_CSTAT_UID_VGEN_LITE_CSTAT0_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CSTAT_UID_VGEN_LITE_CSTAT1_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CSTAT_UID_SLH_AST_SI_G_PPMU_CSTAT_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_CSTAT_UID_RSTNSYNC_SR_CLK_CSTAT_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CSTAT_UID_RSTNSYNC_SR_CLK_CSTAT_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_CSTAT_UID_BLK_CSTAT_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DBGCORE_UID_AHB_BUSMATRIX_DBGCORE_IPCLKPORT_HCLK,
|
||
|
|
CLK_BLK_DBGCORE_UID_GREBEINTEGRATION_DBGCORE_IPCLKPORT_HCLK,
|
||
|
|
CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_NOC_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DBGCORE_UID_SLH_AXI_MI_IP_APM_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DBGCORE_UID_SLH_AXI_SI_G_DBGCORE_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DBGCORE_UID_SLH_AXI_SI_G_SCAN2DRAM_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DBGCORE_UID_SLH_AXI_SI_ID_DBGCORE_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DBGCORE_UID_SYSREG_DBGCORE_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DBGCORE_UID_WDT_DBGCORE_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DBGCORE_UID_XHB_DBGCORE_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DBGCORE_UID_DBGCORE_CMU_DBGCORE_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_GREBE_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DBGCORE_UID_MDIS_DBGCORE_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_DBGCORE_UID_SYSREG_DBGCORE_CORE_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DBGCORE_UID_D_TZPC_DBGCORE_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DBGCORE_UID_APBIF_S2D_DBGCORE_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_DBGCORE_UID_ASYNCAHBMASTER_DBGCORE_IPCLKPORT_HCLKM,
|
||
|
|
CLK_BLK_DBGCORE_UID_MDIS_DBGCORE_IPCLKPORT_I_OSCCLK,
|
||
|
|
CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_FREE_OSCCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DBGCORE_UID_RSTNSYNC_SR_CLK_DBGCORE_NOC_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DBGCORE_UID_SS_DBGCORE_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_LH_AXI_MI_LD_DSP0DNC_SHMEM_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_LH_AXI_MI_LD_GNPU0DNC_SHMEM_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_LH_AXI_MI_LD_GNPU1DNC_SHMEM_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_DNC_CMU_DNC_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DNC_UID_SLH_AXI_MI_LD_CMDQ_GNPU0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_LH_AXI_MI_LD_DSP0DNC_SFR_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_SLH_AXI_MI_LD_CMDQ_GNPU1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_SLH_AXI_MI_P_DNC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_LH_AXI_SI_LD1_GNPU0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_LH_AXI_MI_LP_IPDNC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_LH_AXI_SI_LD1_GNPU1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_LH_AXI_SI_LP_IPDNC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU3_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU2_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_ADM_DAP_DNC_IPCLKPORT_DAPCLKM,
|
||
|
|
CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_LH_AXI_MI_LD_RQ_GNPU0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_LH_AXI_MI_LD_RQ_GNPU1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_SLH_AXI_MI_LD_DSP0DNC_CACHE_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_LH_AXI_SI_LD0_GNPU0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_LH_AXI_SI_LD0_GNPU1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_IP_DNC_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DNC_UID_LH_AXI_SI_LD_DNCDSP0_DMA_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_SYSREG_DNC_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DNC_UID_LH_AXI_SI_LD_DNCDSP0_SFR_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_D_TZPC_DNC_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA3_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA2_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA7_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_LH_AXI_SI_LD_CTRL_GNPU1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA6_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_LH_AXI_SI_LD_CTRL_GNPU0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA5_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA4_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DNC_UID_PPMU_IPDNC_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_DNC_UID_PPMU_IPDNC_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DNC_UID_PPMU_SDMA0_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_DNC_UID_PPMU_SDMA0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DNC_UID_PPMU_SDMA1_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_DNC_UID_PPMU_SDMA1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DNC_UID_PPMU_SDMA2_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_DNC_UID_PPMU_SDMA2_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DNC_UID_PPMU_SDMA3_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_DNC_UID_PPMU_SDMA3_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DNC_UID_SYSMMU_IPDNC_IPCLKPORT_CLK_S1,
|
||
|
|
CLK_BLK_DNC_UID_SYSMMU_SDMA0_IPCLKPORT_CLK_S1,
|
||
|
|
CLK_BLK_DNC_UID_SYSMMU_SDMA0_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_DNC_UID_SYSMMU_IPDNC_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_DNC_UID_SYSMMU_SDMA1_IPCLKPORT_CLK_S1,
|
||
|
|
CLK_BLK_DNC_UID_SYSMMU_SDMA1_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_DNC_UID_SYSMMU_SDMA2_IPCLKPORT_CLK_S1,
|
||
|
|
CLK_BLK_DNC_UID_SYSMMU_SDMA2_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_DNC_UID_SYSMMU_SDMA3_IPCLKPORT_CLK_S1,
|
||
|
|
CLK_BLK_DNC_UID_SYSMMU_SDMA3_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_DNC_UID_TREX_D_DNC_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_DNC_UID_TREX_D_DNC_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DNC_UID_APBAS_S1_NS_SDMA0_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_DNC_UID_HTU_DNC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_HTU_DNC_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_DNC_UID_BUSIF_DDD_DNC_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DNC_UID_BUSIF_ADD_DNC_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DNC_UID_BUSIF_ADD_DNC_IPCLKPORT_CLK_CORE,
|
||
|
|
CLK_BLK_DNC_UID_ADD_DNC_IPCLKPORT_CH_CLK,
|
||
|
|
CLK_BLK_DNC_UID_SLH_AXI_SI_LP_DNCCHUBVTS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_BAAW_DNCCHUBVTS_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_POWERIP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DNC_UID_BUSIF_DDD_DNC_IPCLKPORT_ATCLK,
|
||
|
|
CLK_BLK_DNC_UID_ADD_DNC_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DNC_UID_DDD_DNC_IPCLKPORT_CK_IN,
|
||
|
|
CLK_BLK_DNC_UID_LH_AXI_SI_LP_DNCSDMA_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_SIU_G_PPMU_DNC_IPCLKPORT_I_ACLK,
|
||
|
|
CLK_BLK_DNC_UID_SLH_AST_SI_G_PPMU_DNC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_SLH_AXI_SI_LP_GNPU0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_SLH_AXI_SI_LP_GNPU1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_SLH_AXI_MI_LP_ALIVEDNC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_VGEN_DNC_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DNC_UID_VGEN_LITE_DNC_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DNC_UID_SLH_AXI_MI_LD_UFDDNC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_FREE_OSCCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DNC_UID_XIU_P_DNC_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_DNC_UID_LH_AST_MI_OTF_UFDDNC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_LH_AST_GLUE_OTF_UFDDNC_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DNC_UID_SLH_AXI_SI_LP_DSP0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_SLH_AXI_SI_LP_SDMA_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_BLK_DNC_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_POWERIP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_FREE_OSCCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_DDD_CTRL_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DNC_UID_IP_DNC_IPCLKPORT_DAPCLK,
|
||
|
|
CLK_BLK_DPUB_UID_DPUB_CMU_DPUB_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DPUB_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ACLK_DECON,
|
||
|
|
CLK_BLK_DPUB_UID_D_TZPC_DPUB_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DPUB_UID_SLH_AXI_MI_P_DPUB_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DPUB_UID_SYSREG_DPUB_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM1,
|
||
|
|
CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM2,
|
||
|
|
CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM0,
|
||
|
|
CLK_BLK_DPUB_UID_UPI_M0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DPUB_UID_RSTNSYNC_SR_CLK_DPUB_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DPUB_UID_RSTNSYNC_SR_CLK_DPUB_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM0,
|
||
|
|
CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM1,
|
||
|
|
CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM2,
|
||
|
|
CLK_BLK_DPUB_UID_BLK_DPUB_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DPUF_UID_DPUF_CMU_DPUF_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DPUF_UID_AD_APB_DPUF0_DMA_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_DPUF0,
|
||
|
|
CLK_BLK_DPUF_UID_D_TZPC_DPUF_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DPUF_UID_SLH_AXI_MI_P_DPUF_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DPUF_UID_LH_AXI_SI_D1_DPUF_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DPUF_UID_PPMU_D0_DPUF0_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_DPUF_UID_PPMU_D0_DPUF0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DPUF_UID_PPMU_D1_DPUF0_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_DPUF_UID_PPMU_D1_DPUF0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DPUF_UID_RSTNSYNC_CLK_DPUF_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DPUF_UID_RSTNSYNC_CLK_DPUF_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF0_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF0_IPCLKPORT_CLK_S1,
|
||
|
|
CLK_BLK_DPUF_UID_SYSREG_DPUF_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF0_IPCLKPORT_CLK_S1,
|
||
|
|
CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF0_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_VOTF0,
|
||
|
|
CLK_BLK_DPUF_UID_XIU_D0_DPUF_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_DPUF_UID_XIU_D1_DPUF_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_DPUF_UID_SIU_DPUF_IPCLKPORT_I_ACLK,
|
||
|
|
CLK_BLK_DPUF_UID_SLH_AST_SI_G_PPMU_DPUF_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DPUF_UID_SLH_AXI_SI_D0_DPUF_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DPUF_UID_RSTNSYNC_SR_CLK_DPUF_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DPUF_UID_AD_APB_DPUF1_DMA_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_DPUF1,
|
||
|
|
CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_VOTF1,
|
||
|
|
CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_SRAMC,
|
||
|
|
CLK_BLK_DPUF_UID_PPMU_D1_DPUF1_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_DPUF_UID_PPMU_D1_DPUF1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DPUF_UID_PPMU_D0_DPUF1_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_DPUF_UID_PPMU_D0_DPUF1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF1_IPCLKPORT_CLK_S1,
|
||
|
|
CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF1_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF1_IPCLKPORT_CLK_S1,
|
||
|
|
CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF1_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_DPUF_UID_D_TZPC_DPUF1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DPUF_UID_RSTNSYNC_SR_CLK_DPUF_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DPUF_UID_BLK_DPUF_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DPUF1_UID_DPUF1_CMU_DPUF1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DPUF,
|
||
|
|
CLK_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_VOTF,
|
||
|
|
CLK_BLK_DPUF1_UID_SLH_AXI_MI_P_DPUF1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S1,
|
||
|
|
CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S1,
|
||
|
|
CLK_BLK_DPUF1_UID_SYSREG_DPUF1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_DPUF1_UID_SIU_DPUF1_IPCLKPORT_I_ACLK,
|
||
|
|
CLK_BLK_DPUF1_UID_LH_AXI_SI_D0_DPUF1DPUF0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DPUF1_UID_LH_AXI_SI_D1_DPUF1DPUF0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DPUF1_UID_SLH_ASTL_SI_G_PPMU_DPUF1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DPUF1_UID_RSTNSYNC_SR_CLK_DPUF1_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DRCP_UID_DRCP_CMU_DRCP_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DRCP_UID_AD_APB_DRCP_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_DRCP_UID_DRCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DRCP_UID_PPMU_D_DRCP_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DRCP_UID_PPMU_D_DRCP_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_DRCP_UID_SYSMMU_D_DRCP_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_DRCP_UID_SYSMMU_D_DRCP_IPCLKPORT_CLK_S1,
|
||
|
|
CLK_BLK_DRCP_UID_D_TZPC_DRCP_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DRCP_UID_XIU_D_DRCP_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_DRCP_UID_RSTNSYNC_CLK_DRCP_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DRCP_UID_RSTNSYNC_CLK_DRCP_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DRCP_UID_SYSREG_DRCP_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DRCP_UID_SLH_AXI_MI_P_DRCP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DRCP_UID_LH_AST_MI_OTF_YUVPDRCP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DRCP_UID_LH_AST_SI_OTF_DRCPMCSC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DRCP_UID_LH_AXI_SI_D_DRCP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DRCP_UID_VGEN_LITE_D_DRCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DRCP_UID_SLH_ASTL_SI_G_PPMU_DRCP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DRCP_UID_RSTNSYNC_SR_CLK_DRCP_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DSP_UID_LH_AXI_SI_LD_DSPDNC_SHMEM_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DSP_UID_DSP_CMU_DSP_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DSP_UID_RSTNSYNC_CLK_DSP_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DSP_UID_RSTNSYNC_CLK_DSP_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DSP_UID_SYSREG_DSP_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DSP_UID_D_TZPC_DSP_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DSP_UID_SLH_AXI_MI_LP_DSP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DSP_UID_LH_AXI_MI_LD_DNCDSP_DMA_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DSP_UID_LH_AXI_MI_LD_DNCDSP_SFR_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DSP_UID_SLH_AXI_SI_LD_DSPDNC_CACHE_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DSP_UID_LH_AXI_SI_LD_DSPDNC_SFR_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DSP_UID_IP_DSP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DSP_UID_LH_AST_MI_LD_STRM_SDMADSP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DSP_UID_RSTNSYNC_SR_CLK_DSP_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DSP_UID_RSTNSYNC_SR_CLK_DSP_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DSP_UID_BLK_DSP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK,
|
||
|
|
CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK,
|
||
|
|
CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_CLK_CORE,
|
||
|
|
CLK_BLK_DSU_UID_LH_ATB_SI_IT_CLUSTER0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DSU_UID_RSTNSYNC_CLK_DSU_POWERIP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_DSU_UID_LH_CHI_SI_D0_CLUSTER0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DSU_UID_LH_CHI_SI_D1_CLUSTER0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DSU_UID_GRAY2BIN_CNTVALUEB_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_SCLK,
|
||
|
|
DSU_CPM,
|
||
|
|
CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DSU_UID_STR_CPUCL0_3_IPCLKPORT_DEM_CLK,
|
||
|
|
CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_DSU_HTU_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DSU_UID_SLH_AXI_MI_LP_PPU_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DSU_UID_U_SYNC_PPUWAKEUP_CLUSTER0_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DSU_UID_XIU_DP_UTILITY_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_DSU_UID_SLH_AXI_MI_IP_UTILITY_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DSU_UID_LH_AST_MI_LD_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DSU_UID_LH_AST_SI_LD_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK,
|
||
|
|
CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PPUCLK,
|
||
|
|
CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_GICCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PPUCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ACLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_GICCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PPUCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_SCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACPCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_MPCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ACPCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DSU_UID_XIU_DP_PERIPHERAL_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_DSU_UID_SLH_AXI_SI_IP_UTILITY_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DSU_UID_LH_ACEL_MI_D0_ACP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DSU_UID_LH_ACEL_MI_D1_ACP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DSU_UID_XIU_D_CPUCL0_ACP_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_DSU_UID_SLH_AXI_SI_P_CLUSTER0_NOCL0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ACPCLK,
|
||
|
|
CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_MPCLK,
|
||
|
|
CLK_BLK_DSU_UID_U_SYNC_ACPWAKEUP_CLUSTER0_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DSU_UID_MPACT_M0_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_DSU_UID_MPACT_M0_IPCLKPORT_DIVCLK,
|
||
|
|
CLK_BLK_DSU_UID_MPACT_M1_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_DSU_UID_MPACT_M1_IPCLKPORT_DIVCLK,
|
||
|
|
CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D2_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D3_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_MPACTCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_DSU_POWERIP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_MPACTCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DSU_UID_U_SYNC_IRITWAKEUP_CLUSTER0_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_MPCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_G3D_UID_SLH_AXI_SI_P_INT_G3D_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_G3D_UID_CFM_G3D_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_G3D_UID_BG3D_PWRCTL_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_FREE_OSCCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_FREE_OSCCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_G3DCORE_UID_ADD_G3D_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_G3DCORE_UID_ADD_G3D_IPCLKPORT_CH_CLK,
|
||
|
|
CLK_BLK_G3DCORE_UID_ADD_APBIF_G3D_IPCLKPORT_CLK_CORE,
|
||
|
|
CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3D_POWERIP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_G3DCORE_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_G3DCORE_UID_HTU_G3D_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_G3DCORE_UID_G3DCORE_CMU_G3DCORE_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_G3DCORE_UID_GPU_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_G3DCORE_UID_ADM_DAP_G_G3D_IPCLKPORT_DAPCLKM,
|
||
|
|
CLK_BLK_G3DCORE_UID_HTU_G3D_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3DCORE_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_G3DCORE_UID_BUSIF_DDC_G3D_IPCLKPORT_PCLK_S0,
|
||
|
|
G3DCORE_CPM,
|
||
|
|
CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3DCORE_FREE_OSCCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3DCORE_FREE_OSCCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3DCORE_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3D_POWERIP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_G3DCORE_UID_STR_MUX_G3D_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_G3DCORE_UID_STR_MUX_G3D_IPCLKPORT_CLK_CORE,
|
||
|
|
CLK_BLK_GNPU_UID_GNPU_CMU_GNPU_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_GNPU_UID_IP_NPUCORE_IPCLKPORT_CLK_CORE,
|
||
|
|
CLK_BLK_GNPU_UID_IP_NPUCORE_IPCLKPORT_CLK_SRAM,
|
||
|
|
CLK_BLK_GNPU_UID_LH_AXI_MI_LD_CTRL_GNPU_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_GNPU_UID_LH_AXI_SI_LD_RQ_GNPU_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_GNPU_UID_LH_AXI_MI_LD1_GNPU_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_GNPU_UID_D_TZPC_GNPU_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_GNPU_UID_SLH_AXI_MI_LP_GNPU_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_GNPU_UID_SLH_AXI_SI_LD_CMDQ_GNPU_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_GNPU_UID_SYSREG_GNPU_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_GNPU_UID_LH_AXI_MI_LD0_GNPU_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_GNPU_UID_LH_AXI_SI_LD_GNPUDNC_SHMEM_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_GNPU_UID_XIU_D_GNPU_0_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_GNPU_UID_XIU_D_GNPU_1_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_GNPU_UID_RSTNSYNC_CLK_GNPU_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_GNPU_UID_RSTNSYNC_CLK_GNPU_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_GNPU_UID_RSTNSYNC_SR_CLK_GNPU_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_GNPU_UID_RSTNSYNC_SR_CLK_GNPU_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_GNPU_UID_BLK_GNPU_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_GNSS_UID_GNSS_CMU_GNSS_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_HSI0_UID_SLH_AST_SI_G_PPMU_HSI0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_OSC_CLK,
|
||
|
|
CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK,
|
||
|
|
CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_HSI0_UID_SLH_AXI_MI_P_HSI0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_HSI0_UID_SLH_ACEL_SI_D_HSI0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_HSI0_UID_SLH_AXI_SI_LD_HSI0AUD_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_HSI0_UID_SYSMMU_D_HSI0_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBSUBCTL_APB_PCLK,
|
||
|
|
CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_CTRL_PCLK,
|
||
|
|
CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_TCA_APB_CLK,
|
||
|
|
CLK_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_HSI0_UID_XIU_D_HSI0_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBLINK_ACLK,
|
||
|
|
CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USB32DRD_REF_CLK_40,
|
||
|
|
CLK_BLK_HSI0_UID_SLH_AXI_MI_LD_AUDHSI0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_HSI0_UID_URAM_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_HSI0_UID_XIU_P0_HSI0_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_CTRL_PCLK,
|
||
|
|
CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_APB_CLK,
|
||
|
|
CLK_BLK_HSI0_UID_AS_APB_EUSBPHY_HSI0_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_EUSB_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_NOC_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_HSI0_UID_OTP_DESERIAL_DPLINK_HDCP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_HSI0_UID_SPC_HSI0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_HSI0_UID_BLK_HSI0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_FREE_OSCCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_A_G2X1_PHY_REFCLK_IN,
|
||
|
|
CLK_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_HSI1_UID_SLH_AXI_MI_P_HSI1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_HSI1_UID_LH_ACEL_SI_D_HSI1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG,
|
||
|
|
CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_PIPE_PAL_GEN2_X1_PCIE_INST_0_I_APB_PCLK,
|
||
|
|
CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
|
||
|
|
CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG,
|
||
|
|
CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG,
|
||
|
|
CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG,
|
||
|
|
CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG,
|
||
|
|
CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
|
||
|
|
CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_PHY_UDBG_I_APB_PCLK,
|
||
|
|
CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK,
|
||
|
|
CLK_BLK_HSI1_UID_PCIE_IA_GEN3_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S1,
|
||
|
|
CLK_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_HSI1_UID_VGEN_LITE_HSI1_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_HSI1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG,
|
||
|
|
CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_SUB_CTRL_A_G3X2_PHY_REFCLK_IN,
|
||
|
|
CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_SF_PCIEPHY_X1_QCH_TM_WRAPPER_INST_0_I_APB_PCLK,
|
||
|
|
CLK_BLK_HSI1_UID_SLH_AST_SI_G_PPMU_HSI1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_HSI1_UID_RSTNSYNC_SR_CLK_HSI1_NOC_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_SOC_CTRL_GEN3A_IPCLK,
|
||
|
|
CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_SF_PCIEPHY_X2_QCH_TM_WRAPPER_INST_0_I_APB_PCLK,
|
||
|
|
CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_PHY_UDBG_I_APB_PCLK,
|
||
|
|
CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_FREE_OSCCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_HSI1_UID_RSTNSYNC_SR_CLK_HSI1_FREE_OSCCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SOC_CTRL_GEN2_IPCLK,
|
||
|
|
CLK_BLK_HSI1_UID_BLK_HSI1_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_LME_UID_LME_CMU_LME_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_LME_UID_LH_ACEL_SI_D_LME_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_LME_UID_PPMU_D_LME_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_LME_UID_PPMU_D_LME_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_LME_UID_SLH_AXI_MI_P_LME_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_LME_UID_SYSREG_LME_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_LME_UID_D_TZPC_LME_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S1,
|
||
|
|
CLK_BLK_LME_UID_XIU_D_LME_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_LME_UID_QE_D1_LME_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_LME_UID_QE_D1_LME_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_LME_UID_SLH_AST_SI_G_PPMU_LME_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_LME_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_LME_UID_AD_APB_LME_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_LME_UID_AD_APB_GDC_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_LME_UID_LME_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_LME_UID_GDC_IPCLKPORT_C2CLK_M,
|
||
|
|
CLK_BLK_LME_UID_GDC_IPCLKPORT_C2CLK_S,
|
||
|
|
CLK_BLK_LME_UID_GDC_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_LME_UID_LH_AXI_MI_ID_LME_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_LME_UID_LH_AXI_SI_ID_LME_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_LME_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_LME_UID_VGEN_LITE_D_GDC_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_LME_UID_VGEN_LITE_D_LME_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_LME_UID_BLK_LME_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_M2M_UID_AS_APB_M2M_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_M2M_UID_SLH_AXI_MI_P_M2M_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_M2M_UID_LH_ACEL_SI_D_M2M_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1,
|
||
|
|
CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF,
|
||
|
|
CLK_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_M2M_UID_QE_M2M_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_M2M_UID_SYSMMU_D_M2M_PM_IPCLKPORT_CLK_S1,
|
||
|
|
CLK_BLK_M2M_UID_SYSMMU_D_M2M_PM_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_M2M_UID_QE_M2M_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK,
|
||
|
|
CLK_BLK_M2M_UID_JPEG1_IPCLKPORT_I_SMFC_CLK,
|
||
|
|
CLK_BLK_M2M_UID_JSQZ_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_M2M_UID_SLH_AST_SI_G_PPMU_M2M_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_M2M_UID_FRC_MC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_M2M_UID_QE_FRC_MC_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_M2M_UID_QE_FRC_MC_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_FRC_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_FRC_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_M2M_UID_AS_APB_FRC_MC_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_M2M_UID_BLK_M2M_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_M2M_UID_LH_AXI_MI_FRC_MC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_M2M_UID_LH_AXI_SI_FRC_MC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MCSC_UID_LH_AXI_SI_D1_MCSC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MCSC_UID_LH_AXI_SI_D2_MCSC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1,
|
||
|
|
CLK_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1,
|
||
|
|
CLK_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_MCSC_UID_XIU_D1_MCSC_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_MCSC_UID_XIU_D2_MCSC_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_MCSC_UID_VGEN_LITE_D1_MCSC_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MCSC_UID_SLH_AST_SI_G_PPMU_MCSC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MCSC_UID_SIU_G_PPMU_MCSC_IPCLKPORT_I_ACLK,
|
||
|
|
CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_MCSC_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MCSC_UID_AD_APB_MCFP_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_MCSC_UID_PPMU_D3_MCSC_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_MCSC_UID_PPMU_D3_MCSC_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_MCSC_UID_PPMU_D4_MCSC_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_MCSC_UID_PPMU_D4_MCSC_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1,
|
||
|
|
CLK_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_MCSC_UID_SYSMMU_D3_MCSC_IPCLKPORT_CLK_S1,
|
||
|
|
CLK_BLK_MCSC_UID_SYSMMU_D3_MCSC_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_MCSC_UID_SYSMMU_D4_MCSC_IPCLKPORT_CLK_S1,
|
||
|
|
CLK_BLK_MCSC_UID_SYSMMU_D4_MCSC_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_MCSC_UID_SLH_AXI_SI_D0_MCSC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MCSC_UID_LH_AXI_SI_D3_MCSC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MCSC_UID_LH_AXI_SI_D4_MCSC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MCSC_UID_XIU_D3_MCSC_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_MCSC_UID_XIU_D4_MCSC_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_MCSC_UID_VGEN_LITE_D0_MCSC_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MCSC_UID_VGEN_LITE_D2_MCSC_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_C2R_CLK,
|
||
|
|
CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_C2W_CLK,
|
||
|
|
CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MCSC_UID_MCFP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MCSC_UID_LH_AST_SI_OTF_MCSCYUVP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MCSC_UID_LH_AST_MI_OTF_BRPMCSC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC6_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC2_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC3_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC4_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC5_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC2_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC3_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC4_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC5_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC6_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MCSC_UID_BLK_MCSC_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MCSC_UID_LH_AST_MI_OTF0_YUVPMCSC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MCSC_UID_LH_AST_MI_OTF1_YUVPMCSC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MFC0_UID_MFC0_CMU_MFC0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_MFC0_UID_XIU_D_MFC0_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_MFC0_UID_WFD_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S1,
|
||
|
|
CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_WFD_SW_RESET_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_WFD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_MFC0_SW_RESET_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_SI_SW_RESET_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_MI_SW_RESET_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_MFC0_UID_MFC0_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_MFC0_UID_MFC0_IPCLKPORT_C2CLK,
|
||
|
|
CLK_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_SI,
|
||
|
|
CLK_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_MI,
|
||
|
|
CLK_BLK_MFC0_UID_LH_AXI_SI_D1_MFC0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MFC0_UID_LH_AXI_SI_D0_MFC0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MFC0_UID_LH_AST_SI_OTF2_MFC0MFC1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MFC0_UID_LH_AST_SI_OTF1_MFC0MFC1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MFC0_UID_LH_AST_SI_OTF0_MFC0MFC1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MFC0_UID_SLH_AXI_MI_P_MFC0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MFC0_UID_LH_AST_MI_OTF3_MFC1MFC0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MFC0_UID_LH_AST_MI_OTF2_MFC1MFC0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MFC0_UID_LH_AST_MI_OTF1_MFC1MFC0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MFC0_UID_LH_AST_MI_OTF0_MFC1MFC0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MFC0_UID_D_TZPC_MFC0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_MFC0_UID_ADS_APB_MFC0MFC1_IPCLKPORT_PCLKS,
|
||
|
|
CLK_BLK_MFC0_UID_AS_APB_MFC0_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_MFC0_UID_AS_APB_WFD_NS_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_MFC0_UID_SYSREG_MFC0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_MFC0_UID_LH_AST_SI_OTF3_MFC0MFC1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S1,
|
||
|
|
CLK_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_MFC0_UID_SLH_AST_SI_G_PPMU_MFC0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MFC0_UID_SIU_G_PPMU_MFC0_IPCLKPORT_I_ACLK,
|
||
|
|
CLK_BLK_MFC0_UID_VGEN_LITE_MFC0_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_MFC0_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MFC0_UID_LH_AXI_SI_ID_MFC0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MFC0_UID_LH_AXI_MI_ID_MFC0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MFC0_UID_BLK_MFC0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_SW_RESET_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_WFD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MFC1_UID_MFC1_CMU_MFC1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_MFC1_UID_SYSREG_MFC1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S1,
|
||
|
|
CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCD_MFC1_SW_RESET_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCD_MFC1_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MFC1_UID_LH_AST_MI_OTF0_MFC0MFC1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MFC1_UID_D_TZPC_MFC1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_MFC1_UID_AS_APB_MFC1_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_MFC1_UID_ADM_APB_MFC0MFC1_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_MFC1_UID_LH_AST_MI_OTF1_MFC0MFC1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MFC1_UID_LH_AST_MI_OTF2_MFC0MFC1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MFC1_UID_LH_AST_MI_OTF3_MFC0MFC1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MFC1_UID_SLH_AXI_MI_P_MFC1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MFC1_UID_LH_AST_SI_OTF0_MFC1MFC0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MFC1_UID_LH_AST_SI_OTF1_MFC1MFC0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MFC1_UID_LH_AST_SI_OTF2_MFC1MFC0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MFC1_UID_LH_AST_SI_OTF3_MFC1MFC0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MFC1_UID_LH_AXI_SI_D0_MFC1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MFC1_UID_LH_AXI_SI_D1_MFC1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MFC1_UID_MFC1_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S1,
|
||
|
|
CLK_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_MFC1_UID_VGEN_MFC1_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MFC1_UID_SLH_AST_SI_G_PPMU_MFC1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MFC1_UID_SIU_G_PPMU_MFC1_IPCLKPORT_I_ACLK,
|
||
|
|
CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MFC1_UID_BLK_MFC1_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_SW_RESET_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MIF_UID_QCH_ADAPTER_DDRPHY_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_MIF_UID_QCH_ADAPTER_DMC_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_MIF_UID_SPC_MIF_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_MIF_UID_SYSREG_PRIVATE_MIF_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_MIF_UID_SLH_AST_SI_G_PPMU_MIF_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_FREE_OSCCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MIF_UID_BUSIF_DDD_MIF_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_MIF_UID_BUSIF_DDD_MIF_IPCLKPORT_ATCLK,
|
||
|
|
CLK_BLK_MIF_UID_DDD_MIF_IPCLKPORT_CK_IN,
|
||
|
|
CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCD_DEBUG_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_DDD_CTRL_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_FREE_OSCCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_MIF_UID_BLK_MIF_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_NOCL0_CMU_NOCL0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_CCI_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SIU_G0_PPMU_NOCL0_IPCLKPORT_I_ACLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SIU_G1_PPMU_NOCL0_IPCLKPORT_I_ACLK,
|
||
|
|
CLK_BLK_NOCL0_UID_APB_ASYNC_SYSMMU_S2_G3D_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_NOCL0_UID_BAAW_CP_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_BDU_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_BDU_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_D_TZPC_NOCL0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SLH_AXI_MI_D2_MODEM_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_LH_CHI_MI_D0_CLUSTER0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_LH_ACEL_MI_D0_G3D_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_LH_CHI_MI_D1_CLUSTER0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_LH_ACEL_MI_D1_G3D_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_LH_ACEL_MI_D2_G3D_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_LH_ACEL_MI_D3_G3D_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SLH_AXI_MI_D0_MODEM_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SLH_AXI_MI_D1_MODEM_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_LH_QDI_MI_D_AUD_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_LH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_APM_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_AUD_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MODEM_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERISGIC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_MPACE2AXI_0_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_MPACE2AXI_1_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_PPC_DEBUG_CCI_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL0_UID_PPC_DEBUG_CCI_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_PPMU_CPUCL0_0_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL0_UID_PPMU_CPUCL0_0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_PPMU_CPUCL0_1_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL0_UID_PPMU_CPUCL0_1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_PPMU_G3D0_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL0_UID_PPMU_G3D0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_PPMU_G3D1_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL0_UID_PPMU_G3D1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_PPMU_G3D2_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL0_UID_PPMU_G3D2_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_PPMU_G3D3_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL0_UID_PPMU_G3D3_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_PPMU_MIF0_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL0_UID_PPMU_MIF1_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL0_UID_PPMU_MIF2_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL0_UID_PPMU_MIF3_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D0,
|
||
|
|
CLK_BLK_NOCL0_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_NOCL0_UID_SYSREG_NOCL0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_VGEN_LITE_MODEM_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_NOCL0,
|
||
|
|
CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF2_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF3_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SYSMMU_S2_APM_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_NOCL0_UID_LH_AXI_MI_D_APM_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MCW_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SLH_AXI_MI_P_CLUSTER0_NOCL0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D1,
|
||
|
|
CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D2,
|
||
|
|
CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D3,
|
||
|
|
CLK_BLK_NOCL0_UID_CACHEAID_NOCL0_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL0_UID_CACHEAID_NOCL0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK_NOCL0,
|
||
|
|
CLK_BLK_NOCL0_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S1,
|
||
|
|
CLK_BLK_NOCL0_UID_PPMU_APM_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL0_UID_PPMU_APM_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_UFD_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_SSP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1C_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_WOW_DVFS_D0_MIF_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL0_UID_WOW_DVFS_D0_MIF_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS0_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS1_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS2_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS2_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS3_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS3_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_WOW_DVFS_NOCL0_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_WOW_DVFS_NOCL0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_PPC_SCI_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL0_UID_WOW_DVFS_D0_CPUCL0_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL0_UID_WOW_DVFS_D0_CPUCL0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_WOW_DVFS_D0_G3D_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL0_UID_WOW_DVFS_D0_G3D_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_WOW_DVFS_D1_CPUCL0_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL0_UID_WOW_DVFS_D1_CPUCL0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_MPTW,
|
||
|
|
CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_AUD_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MODEM_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1A_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1B_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SIU_G2_PPMU_NOCL0_IPCLKPORT_I_ACLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SIU_G3_PPMU_NOCL0_IPCLKPORT_I_ACLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SIU_G4_PPMU_NOCL0_IPCLKPORT_I_ACLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SIU_G5_PPMU_NOCL0_IPCLKPORT_I_ACLK,
|
||
|
|
CLK_BLK_NOCL0_UID_APB_ASYNC_ETR_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_NOCL0_UID_ETR_64_NOCL0_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF2_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF3_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_PPMU_SYNC_GEN_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL0_UID_PPMU_SYNC_GEN_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_PBHA_GEN_D0_MODEM_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_PBHA_GEN_D1_MODEM_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_WOW_DVFS_D1_MIF_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL0_UID_WOW_DVFS_D1_MIF_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_WOW_DVFS_D2_MIF_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL0_UID_WOW_DVFS_D2_MIF_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_WOW_DVFS_D3_MIF_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL0_UID_WOW_DVFS_D3_MIF_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_VGEN_D0_G3D_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_VGEN_D1_G3D_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_VGEN_D2_G3D_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_VGEN_D3_G3D_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SLH_AST_SI_IG_PPMU_P_CLUSTER0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SLH_AST_MI_IG_PPMU_P_CLUSTER0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D0_G3D_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D1_G3D_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D2_G3D_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D3_G3D_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_NOCL0_UID_PPC_SCI_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_PPMU_MIF0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_PPMU_MIF1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_PPMU_MIF2_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_PPMU_MIF3_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_CCI_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_FREE_OSCCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_FREE_OSCCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_GNSS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_NOCIF_CMUTOPC_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_GNSS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1C_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_SSP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_UFD_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SLH_ACEL_MI_D_SSP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SLH_AXI_MI_D_UFD_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_LH_AXI_SI_IG_CSSYS_NOCL0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_LH_AXI_MI_IG_CSSYS_NOCL0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_LH_ACEL_SI_D0_ACP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_TREX_D0_ACP_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL0_UID_TREX_D0_ACP_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_TREX_D1_ACP_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL0_UID_TREX_D1_ACP_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL0_UID_LH_ACEL_SI_D1_ACP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_XIU_D0_ACP_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL0_UID_XIU_D1_ACP_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL0_UID_XIU_D2_ACP_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL0_UID_XIU_D3_ACP_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_CCI_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_CCI_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_CCI_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_NOCL0_UID_BLK_NOCL0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_NOCL1A_CMU_NOCL1A_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_SYSREG_NOCL1A_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_HSI1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_MFC1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_MFC1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_MFC0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_MFC0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_D_TZPC_NOCL1A_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_LME_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK_NOCL1A,
|
||
|
|
CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_MFC1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_LME_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_MFC0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_HSI1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_HSI1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_LME_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_MFC0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_MFC1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_SLH_AST_SI_G_PPMU_NOCL1A_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_SIU_2X1_P0_NOCL1A_IPCLKPORT_I_ACLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_SIU_4X1_P0_NOCL1A_IPCLKPORT_I_ACLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_SIU_8X1_P0_NOCL1A_IPCLKPORT_I_ACLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_PERIC0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_PERIC2_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_SLH_AST_MI_IG_PPMU_NOCL1A_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_SLH_AST_SI_IG_PPMU_NOCL1A_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1A_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1A_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_DPUF_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_DNC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_DPUF_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_SLH_AXI_MI_D0_DPUF_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DNC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DPUB_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DPUF_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_BAAW_P_DNC_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_M2M_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_M2M_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_M2M_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_RET_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_RET_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_NOCL1A_UID_BLK_NOCL1A_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_NOCL1B_CMU_NOCL1B_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_D_TZPC_NOCL1B_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_SLH_ACEL_MI_D_HSI0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_QE_PDMA_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_QE_SPDMA_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_SYSREG_NOCL1B_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK_NOCL1B,
|
||
|
|
CLK_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_UFS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_PPMU_D_TT_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_PPMU_DIT_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_SLH_AST_MI_G_PPMU_HSI0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_SLH_AST_SI_G_PPMU_NOCL1B_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD1_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_AD_APB_DIT_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_NOCL1B_UID_AD_APB_PDMA_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_NOCL1B_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_NOCL1B_UID_AD_APB_SYSMMU_DIT_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_NOCL1B_UID_AD_APB_SYSMMU_TT_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_NOCL1B_UID_PDMA_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_SPDMA_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_QE_PDMA_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_QE_SPDMA_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_DIT_IPCLKPORT_ICLKL2A,
|
||
|
|
CLK_BLK_NOCL1B_UID_XIU_D_TT_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_SYSMMU_S2_TT_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_NOCL1B_UID_SYSMMU_S2_DIT_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_NOCL1B_UID_VGEN_LITE_NOCL1B_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_VGEN_SPDMA_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_VGEN_PDMA_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_PPMU_DIT_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_PPMU_D_TT_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD1_RET_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_LH_ACEL_MI_ID_DIT_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_LH_ACEL_SI_ID_DIT_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_AD_APB_VGEN_LITE_NOCL1B_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_NOCL1B_UID_AD_APB_VGEN_PDMA_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_NOCL1B_UID_AD_APB_VGEN_SPDMA_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD0_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD1_RET_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_TREXP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_XIU_D_TT_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_DIT_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_TREXP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_XIU_D_TT_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_DIT_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1B_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1B_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_LH_ACEL_MI_D_UFS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_SLH_AST_MI_G_PPMU_UFS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_SIU_8X1_P0_NOCL1B_IPCLKPORT_I_ACLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_LH_AXI_MI_ID_TT_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_LH_AXI_SI_ID_TT_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD1_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_RET_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD0_RET_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_NOCL1B_UID_BLK_NOCL1B_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_NOCL1C_CMU_NOCL1C_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_MCSC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_SYSREG_NOCL1C_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_TREX_D_NOCL1C_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_TREX_D_NOCL1C_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_CSTAT_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_LH_AXI_MI_D_CSTAT_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_SLH_AXI_MI_D0_MCSC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_TREX_P_NOCL1C_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_TREX_P_NOCL1C_IPCLKPORT_PCLK_NOCL1C,
|
||
|
|
CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_YUVP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_LH_AST_SI_G_NOCL1C_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_MCSC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_D_TZPC_NOCL1C_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_CSIS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_RSTNSYNC_CLK_NOCL1C_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_CSIS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_CSTAT_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_MCSC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_YUVP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_SLH_AST_SI_G_PPMU_NOCL1C_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_RSTNSYNC_SR_CLK_NOCL1C_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_SLH_AST_MI_IG_PPMU_NOCL1C_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_SLH_AST_SI_IG_PPMU_NOCL1C_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1C_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1C_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_LH_AXI_MI_D3_MCSC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_LH_AXI_MI_D4_MCSC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_BRP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_BRP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_BRP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_YUVP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_SLH_AXI_MI_D1_YUVP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_BRP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_BRP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_SIU_8X1_P0_NOCL1C_IPCLKPORT_I_ACLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_RSTNSYNC_SR_CLK_NOCL1C_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_NOCL1C_UID_BLK_NOCL1C_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I2C_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIC0_UID_SLH_AXI_MI_P_PERIC0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_USI04_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_FREE_OSCCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIC0_UID_I3C00_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_PERIC0_UID_I3C00_IPCLKPORT_I_SCLK,
|
||
|
|
CLK_BLK_PERIC0_UID_I3C01_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_PERIC0_UID_I3C01_IPCLKPORT_I_SCLK,
|
||
|
|
CLK_BLK_PERIC0_UID_I3C02_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_PERIC0_UID_I3C02_IPCLKPORT_I_SCLK,
|
||
|
|
CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_I2C_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_UART_BT_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIC1_UID_SLH_AXI_MI_P_PERIC1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI07_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_PERIC1_UID_BT_UART_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIC1_UID_USI07_SPI_I2C_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI08_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI09_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI10_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIC1_UID_BT_UART_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_PERIC1_UID_USI08_SPI_I2C_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_PERIC1_UID_SPI_MULTI_SLV_Q_CTRL_PERIC1_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_SPI_MS_CTRL_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_FREE_OSCCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIC1_UID_USI07_SPI_I2C_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_PERIC1_UID_USI08_SPI_I2C_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI07_SPI_I2C_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI08_SPI_I2C_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_I2C_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIC2_UID_PERIC2_CMU_PERIC2_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_D_TZPC_PERIC2_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_GPIO_PERIC2_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_SLH_AXI_MI_P_PERIC2_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_I2C_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIC2_UID_SYSREG_PERIC2_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI00_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI01_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI02_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI03_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI05_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI06_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIC2_UID_USI00_SPI_I2C_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_USI01_SPI_I2C_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_USI02_I2C_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_USI02_I2C_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_USI03_I2C_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_USI03_I2C_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_USI05_I2C_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_USI05_I2C_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_USI06_I2C_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_USI06_I2C_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_USI00_USI_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_USI00_USI_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_USI01_USI_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_USI02_USI_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_USI02_USI_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_USI03_USI_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_USI03_USI_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_USI05_USI_OIS_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_USI06_USI_OIS_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_USI06_USI_OIS_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_USI01_USI_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_I3C06_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_I3C07_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_I3C08_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_I3C09_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_I3C10_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_I3C11_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_I3C06_IPCLKPORT_I_SCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_I3C07_IPCLKPORT_I_SCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_I3C08_IPCLKPORT_I_SCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_I3C09_IPCLKPORT_I_SCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_I3C10_IPCLKPORT_I_SCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_I3C11_IPCLKPORT_I_SCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_SPI_MULTI_SLV_Q_CTRL_PERIC2_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIC2_UID_USI05_USI_OIS_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI11_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIC2_UID_USI11_I2C_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_USI11_I2C_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_USI11_USI_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_USI11_USI_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_I3C03_OIS_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_I3C04_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_I3C05_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_I3C05_IPCLKPORT_I_SCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_I3C04_IPCLKPORT_I_SCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_I3C03_OIS_IPCLKPORT_I_SCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_UART_DBG_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIC2_UID_DBG_UART_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_DBG_UART_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_PWM_IPCLKPORT_I_PCLK_S0,
|
||
|
|
CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_SPI_MS_CTRL_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_FREE_OSCCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIC2_UID_USI00_SPI_I2C_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_USI01_SPI_I2C_IPCLKPORT_IPCLK,
|
||
|
|
CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI00_SPI_I2C_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI01_SPI_I2C_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIC2_UID_SLH_AXI_MI_LP_CSISPERIC2_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_PERIC2_UID_XIU_P_PERIC2_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_I2C_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIS_UID_GIC_IPCLKPORT_GICCLK,
|
||
|
|
CLK_BLK_PERIS_UID_LH_AST_MI_LD_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_PERIS_UID_SLH_AXI_MI_P_PERIS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_PERIS_UID_SLH_AXI_MI_P_PERISGIC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_PERIS_UID_LH_AST_SI_LD_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK,
|
||
|
|
CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK,
|
||
|
|
CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_FREE_OSCCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIS_UID_BUSIF_DDD_PERIS_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_PERIS_UID_BUSIF_DDD_PERIS_IPCLKPORT_ATCLK,
|
||
|
|
CLK_BLK_PERIS_UID_DDD_PERIS_IPCLKPORT_CK_IN,
|
||
|
|
CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_GIC_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_FREE_OSCCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_DDD_CTRL_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK,
|
||
|
|
CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_S2D_UID_SLH_AXI_MI_G_SCAN2DRAM_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_S2D_UID_RSTNSYNC_SR_CLK_S2D_CORE_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_SDMA_UID_SDMA_CMU_SDMA_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA3_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA2_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU1_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_SDMA_UID_SLH_AXI_MI_LP_SDMA_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_SDMA_UID_SYSREG_SDMA_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_SDMA_UID_D_TZPC_SDMA_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_SDMA_UID_RSTNSYNC_CLK_SDMA_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_SDMA_UID_RSTNSYNC_CLK_SDMA_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_SDMA_UID_LH_AST_SI_LD_STRM_SDMADSP0_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_SDMA_UID_IP_SDMA_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_SDMA_UID_LH_AXI_MI_LP_DNCSDMA_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_SDMA_UID_RSTNSYNC_SR_CLK_SDMA_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA4_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA5_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA6_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA7_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU2_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU3_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_SDMA_UID_RSTNSYNC_SR_CLK_SDMA_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_SDMA_UID_BLK_SDMA_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_SSP_UID_SSP_CMU_SSP_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_SSP_UID_BAAW_SSS_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_SSP_UID_D_TZPC_SSP_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_SSP_UID_LH_AXI_MI_L_STRONG_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_SSP_UID_SLH_AXI_MI_P_SSP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_SSP_UID_SLH_ACEL_SI_D_SSP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_SSP_UID_QE_STRONG_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_SSP_UID_QE_STRONG_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_SSP_UID_QE_SSS_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_SSP_UID_QE_SSS_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_SSP_UID_SSS_IPCLKPORT_I_ACLK,
|
||
|
|
CLK_BLK_SSP_UID_SYSREG_SSP_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_SSP_UID_VGEN_LITE_SSP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_SSP_UID_XIU_D_SSP_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_SSP_UID_SSS_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_SSP_UID_AD_APB_SYSMMU_SSP_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_SSP_UID_SYSMMU_SSP_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_SSP_UID_SLH_AST_SI_G_PPMU_SSP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_FREE_OSCCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_SSP_UID_OTP_DESERIAL_SSS_HIDE_SECKEY_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_SSP_UID_HW_APBSEMA_MEC_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_SSP_UID_BLK_SSP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_FREE_OSCCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_STRONG_UID_STRONG_CMU_STRONG_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_STRONG_UID_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_STRONG_UID_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_CPU_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_UFD_UID_UFD_CMU_UFD_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_UFD_UID_D_TZPC_UFD_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_UFD_UID_RSTNSYNC_CLK_UFD_NOC_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_UFD_UID_SLH_AXI_MI_LP_CMGPUFD_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_UFD_UID_SLH_AXI_MI_P_UFD_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_UFD_UID_PDMA_UFD_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_UFD_UID_SYSREG_UFD_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_UFD_UID_UFD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_UFD_UID_XIU_DP_UFD_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_UFD_UID_PPMU_D_UFD_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_UFD_UID_PPMU_D_UFD_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_UFD_UID_VGEN_LITE_D_UFD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_UFD_UID_SLH_AXI_SI_D_UFD_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_UFD_UID_XIU_D_UFD_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_UFD_UID_SLH_AXI_SI_LD_UFDDNC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_UFD_UID_SRAM_MIU_UFD_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_UFD_UID_I3C_UFD_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_UFD_UID_I3C_UFD_IPCLKPORT_I_SCLK,
|
||
|
|
CLK_BLK_UFD_UID_BAAW_D_UFDDNC_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_UFD_UID_SYSREG_UFD_SECURE_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_UFD_UID_ID_COMP_UFD_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_UFD_UID_SLH_AXI_SI_LP_UFDCSIS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_UFD_UID_SLH_AST_MI_OTF_CSISUFD_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_UFD_UID_SYSMMU_D_UFD_IPCLKPORT_CLK_S1,
|
||
|
|
CLK_BLK_UFD_UID_SYSMMU_D_UFD_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_UFD_UID_SLH_AST_SI_G_PPMU_UFD_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_UFD_UID_LH_AST_SI_OTF_UFDDNC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_UFD_UID_BLK_UFD_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_LH_AST_SI_OTF_UFDDNC_SW_RESET_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_SLH_AST_MI_OTF_CSISUFD_SW_RESET_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_UFD_UID_RSTNSYNC_CLK_UFD_NOC_UFD_SW_RESET_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_UFD_UID_AXI_US_32TO128_UFD_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_UFD_UID_AXI_DS_128TO32_UFD_IPCLKPORT_MAINCLK,
|
||
|
|
CLK_BLK_UFS_UID_UFS_CMU_UFS_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_UFS_UID_SLH_AXI_MI_P_UFS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_UFS_UID_SLH_AST_SI_G_PPMU_UFS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_UFS_UID_PPMU_UFS_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_UFS_UID_PPMU_UFS_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_UFS_UID_SYSREG_UFS_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_UFS_UID_XIU_P_UFS_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_UFS_UID_MMC_CARD_IPCLKPORT_SDCLKIN,
|
||
|
|
CLK_BLK_UFS_UID_MMC_CARD_IPCLKPORT_I_ACLK,
|
||
|
|
CLK_BLK_UFS_UID_LH_ACEL_SI_D_UFS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_UFS_UID_D_TZPC_UFS_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_UFS_UID_SPC_UFS_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_UFS_UID_GPIO_HSI1UFS_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_UFS_UID_GPIO_UFS_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_UFS_UID_SYSMMU_UFS_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO,
|
||
|
|
CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK,
|
||
|
|
CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_ACLK,
|
||
|
|
CLK_BLK_UFS_UID_VGEN_LITE_UFS_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_UFS_UID_XIU_D_UFS_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_MMC_CARD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_NOC_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_UFS_EMBD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_UFS_UID_RSTNSYNC_SR_CLK_UFS_FREE_OSCCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_FREE_OSCCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_UFS_UID_OTP_DESERIAL_UFS_EMBD_FMP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_UFS_UID_RSTNSYNC_SR_CLK_UFS_NOC_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_UFS_UID_BLK_UFS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK,
|
||
|
|
CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK,
|
||
|
|
CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_CLK,
|
||
|
|
CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_DIV2_CLK,
|
||
|
|
CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_VTS_UID_INTMEM_CODE_IPCLKPORT_I_ACLK,
|
||
|
|
CLK_BLK_VTS_UID_INTMEM_CODE_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_VTS_UID_INTMEM_DATA0_IPCLKPORT_I_ACLK,
|
||
|
|
CLK_BLK_VTS_UID_INTMEM_DATA0_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_VTS_UID_INTMEM_DATA1_IPCLKPORT_I_ACLK,
|
||
|
|
CLK_BLK_VTS_UID_INTMEM_DATA1_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_VTS_UID_INTMEM_PCM_IPCLKPORT_I_ACLK,
|
||
|
|
CLK_BLK_VTS_UID_INTMEM_PCM_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_NOC_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_BCLK,
|
||
|
|
CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_CCLK,
|
||
|
|
CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0,
|
||
|
|
CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1,
|
||
|
|
CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK2,
|
||
|
|
CLK_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK,
|
||
|
|
CLK_BLK_VTS_UID_XIU_DP0_VTS_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK,
|
||
|
|
CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_VTS_UID_TIMER1_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_VTS_UID_TIMER2_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_YAMIN_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_CLKIN,
|
||
|
|
CLK_BLK_VTS_UID_MAILBOX_DNC_VTS_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_IWICCLK,
|
||
|
|
CLK_BLK_VTS_UID_ASYNCINTERRUPT_VTS_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_DBGCLK,
|
||
|
|
CLKVTS_AUD_DMIC1,
|
||
|
|
CLKVTS_AUD_DMIC0,
|
||
|
|
CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_DIV2_CLK,
|
||
|
|
CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_NOC_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU,
|
||
|
|
CLK_BLK_VTS_UID_LH_AXI_MI_IP_VC2VTS_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_VTS_UID_LH_AXI_SI_ID_VTS2VC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_VTS_UID_SS_VTS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_VTS_UID_BAAW_VTS_IPCLKPORT_I_PCLK,
|
||
|
|
CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_DMIC_IF_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_YAMIN_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_FREE_OSCCLK_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_YUVP_UID_YUVP_CMU_YUVP_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_YUVP_UID_AD_APB_YUVP_IPCLKPORT_PCLKM,
|
||
|
|
CLK_BLK_YUVP_UID_SLH_AXI_MI_P_YUVP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_YUVP_UID_RSTNSYNC_CLK_YUVP_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_YUVP_UID_RSTNSYNC_CLK_YUVP_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_YUVP_UID_SYSREG_YUVP_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_YUVP_UID_PPMU_D0_YUVP_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_YUVP_UID_PPMU_D0_YUVP_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_YUVP_UID_SYSMMU_D0_YUVP_IPCLKPORT_CLK_S1,
|
||
|
|
CLK_BLK_YUVP_UID_XIU_D0_YUVP_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_YUVP_UID_LH_AST_MI_OTF_MCSCYUVP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_YUVP_UID_D_TZPC_YUVP_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_YUVP_UID_SYSMMU_D0_YUVP_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_YUVP_UID_LH_AST_SI_OTF0_YUVPMCSC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_YUVP_UID_BUSIF_DDD_YUVP_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_YUVP_UID_DDD_YUVP_IPCLKPORT_CK_IN,
|
||
|
|
CLK_BLK_YUVP_UID_VGEN_LITE_D0_YUVP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_YUVP_UID_BUSIF_DDD_YUVP_IPCLKPORT_ATCLK,
|
||
|
|
CLK_BLK_YUVP_UID_SLH_AST_SI_G_PPMU_YUVP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_NOCD_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_YUVP_UID_PPMU_D1_YUVP_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_YUVP_UID_PPMU_D1_YUVP_IPCLKPORT_PCLK,
|
||
|
|
CLK_BLK_YUVP_UID_LH_AXI_SI_D0_YUVP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_YUVP_UID_SLH_AXI_SI_D1_YUVP_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_YUVP_UID_XIU_D1_YUVP_IPCLKPORT_ACLK,
|
||
|
|
CLK_BLK_YUVP_UID_SYSMMU_D1_YUVP_IPCLKPORT_CLK_S1,
|
||
|
|
CLK_BLK_YUVP_UID_SYSMMU_D1_YUVP_IPCLKPORT_CLK_S2,
|
||
|
|
CLK_BLK_YUVP_UID_SIU_G_PPMU_YUVP_IPCLKPORT_I_ACLK,
|
||
|
|
CLK_BLK_YUVP_UID_VGEN_LITE_D1_YUVP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_VOTF0,
|
||
|
|
CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_VOTF1,
|
||
|
|
CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_NOCP_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_YUVP_UID_BLK_YUVP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_YUVP_UID_LH_AST_SI_OTF1_YUVPMCSC_IPCLKPORT_I_CLK,
|
||
|
|
CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_DDD_CTRL_IPCLKPORT_CLK,
|
||
|
|
CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_FREE_OSCCLK_IPCLKPORT_CLK,
|
||
|
|
end_of_gate,
|
||
|
|
num_of_gate = (end_of_gate - GATE_TYPE) & MASK_OF_ID,
|
||
|
|
|
||
|
|
};
|
||
|
|
#endif
|