296 lines
8 KiB
C
296 lines
8 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* (C) COPYRIGHT 2021 Samsung Electronics Inc. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms
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* of such GNU licence.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you can access it online at
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* http://www.gnu.org/licenses/gpl-2.0.html.
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*/
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#include <linux/version.h>
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#include <linux/device.h>
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#include <linux/spinlock.h>
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#include <linux/slab.h>
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#include <gpexbe_devicetree.h>
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#include <gpex_utils.h>
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#include <gpex_debug.h>
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#include <gpex_qos.h>
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#include <gpex_clock.h>
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#include <gpex_tsg.h>
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#include <gpexbe_qos.h>
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#include <gpexbe_bts.h>
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#include <gpex_clboost.h>
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#include <gpex_gts.h>
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#include <gpexbe_llc_coherency.h>
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#include <gpexwa_peak_notify.h>
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#define HCM_MODE_A (1 << 0)
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#define HCM_MODE_B (1 << 1)
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#define HCM_MODE_C (1 << 2)
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struct _qos_info {
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bool is_pm_qos_init;
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int mo_min_clock;
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unsigned int is_set_bts; // Check the pair of bts scenario.
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bool gpu_bts_support;
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spinlock_t bts_spinlock;
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int cpu_cluster_count; // is this worth keeping after init?
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int qos_table_size;
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int clqos_table_size;
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/* HCM Stuff */
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int gpu_heavy_compute_cpu0_min_clock;
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int gpu_heavy_compute_vk_cpu0_min_clock;
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};
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struct _qos_table {
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int gpu_clock;
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int mem_freq;
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int cpu_little_min_freq;
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int cpu_middle_min_freq;
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int cpu_big_max_freq;
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int llc_ways;
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};
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struct _clqos_table {
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int gpu_clock;
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int mif_min;
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int little_min;
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int middle_min;
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int big_max;
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};
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static struct _qos_info qos_info;
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static struct _qos_table *qos_table;
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static struct _clqos_table *clqos_table;
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static int gpex_qos_get_table_idx(int clock)
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{
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int idx;
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for (idx = 0; idx < qos_info.qos_table_size; idx++) {
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if (qos_table[idx].gpu_clock == clock)
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return idx;
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}
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return -EINVAL;
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}
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int gpex_qos_set(gpex_qos_flag flags, int val)
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{
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if (!qos_info.is_pm_qos_init) {
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GPU_LOG(MALI_EXYNOS_ERROR, "%s: PM QOS ERROR : pm_qos not initialized\n", __func__);
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return -ENOENT;
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}
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gpexbe_qos_request_update((mali_pmqos_flags)flags, val);
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/* TODO: record PMQOS state somewhere */
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return 0;
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}
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int gpex_qos_unset(gpex_qos_flag flags)
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{
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if (!qos_info.is_pm_qos_init) {
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GPU_LOG(MALI_EXYNOS_ERROR, "%s: PM QOS ERROR : pm_qos not initialized\n", __func__);
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return -ENOENT;
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}
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gpexbe_qos_request_unset((mali_pmqos_flags)flags);
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/* TODO: record PMQOS state somewhere */
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return 0;
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}
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int gpex_qos_init()
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{
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int i = 0;
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gpu_dt *dt = gpexbe_devicetree_get_gpu_dt();
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/* TODO: check dependent backends are initializaed */
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spin_lock_init(&qos_info.bts_spinlock);
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qos_info.gpu_bts_support = (bool)gpexbe_devicetree_get_int(gpu_bts_support);
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qos_info.mo_min_clock = gpexbe_devicetree_get_int(gpu_mo_min_clock);
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qos_info.qos_table_size = dt->gpu_dvfs_table_size.row;
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qos_table = kcalloc(qos_info.qos_table_size, sizeof(*qos_table), GFP_KERNEL);
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for (i = 0; i < qos_info.qos_table_size; i++) {
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qos_table[i].gpu_clock = dt->gpu_dvfs_table[i].clock;
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qos_table[i].mem_freq = dt->gpu_dvfs_table[i].mem_freq;
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qos_table[i].cpu_little_min_freq = dt->gpu_dvfs_table[i].cpu_little_min_freq;
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qos_table[i].cpu_middle_min_freq = dt->gpu_dvfs_table[i].cpu_middle_min_freq;
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qos_table[i].cpu_big_max_freq = dt->gpu_dvfs_table[i].cpu_big_max_freq;
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qos_table[i].llc_ways = dt->gpu_dvfs_table[i].llc_ways;
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}
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#if 0
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if (gpex_qos_get_table_idx(qos_info.mo_min_clock) < 0) {
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/* TODO: print error msg */
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BUG();
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return -1;
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}
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#endif
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qos_info.clqos_table_size = dt->gpu_cl_pmqos_table_size.row;
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clqos_table = kcalloc(qos_info.clqos_table_size, sizeof(*clqos_table), GFP_KERNEL);
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for (i = 0; i < qos_info.clqos_table_size; i++) {
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clqos_table[i].gpu_clock = dt->gpu_cl_pmqos_table[i].clock;
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clqos_table[i].mif_min = dt->gpu_cl_pmqos_table[i].mif_min;
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clqos_table[i].little_min = dt->gpu_cl_pmqos_table[i].little_min;
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clqos_table[i].middle_min = dt->gpu_cl_pmqos_table[i].middle_min;
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clqos_table[i].big_max = dt->gpu_cl_pmqos_table[i].big_max;
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}
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qos_info.gpu_heavy_compute_cpu0_min_clock =
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gpexbe_devicetree_get_int(gpu_heavy_compute_cpu0_min_clock);
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qos_info.gpu_heavy_compute_vk_cpu0_min_clock =
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gpexbe_devicetree_get_int(gpu_heavy_compute_vk_cpu0_min_clock);
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/* Request to set QOS of other IPs */
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gpexbe_qos_request_add(PMQOS_MIF | PMQOS_LITTLE | PMQOS_MIDDLE | PMQOS_BIG | PMQOS_MIN |
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PMQOS_MAX);
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qos_info.is_pm_qos_init = true;
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gpex_utils_get_exynos_context()->qos_info = &qos_info;
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gpex_utils_get_exynos_context()->qos_table = qos_table;
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gpex_utils_get_exynos_context()->clqos_table = clqos_table;
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return 0;
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}
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void gpex_qos_term()
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{
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gpexbe_qos_request_remove(PMQOS_MIF | PMQOS_LITTLE | PMQOS_MIDDLE | PMQOS_BIG | PMQOS_MIN |
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PMQOS_MAX);
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kfree(qos_table);
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kfree(clqos_table);
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qos_info.is_pm_qos_init = false;
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}
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int gpex_qos_set_bts_mo(int clock)
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{
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int ret = 0;
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unsigned long flags;
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if (!qos_info.gpu_bts_support) {
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if (qos_info.is_set_bts) {
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/* TODO: print error */
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return -1;
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}
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return 0;
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}
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spin_lock_irqsave(&qos_info.bts_spinlock, flags);
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if (clock >= qos_info.mo_min_clock && !qos_info.is_set_bts) {
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gpex_debug_new_record(HIST_BTS);
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ret = gpexbe_bts_set_bts_mo(1);
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gpex_debug_record(HIST_BTS, qos_info.is_set_bts, 1, ret);
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if (ret) {
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GPU_LOG(MALI_EXYNOS_WARNING, "BTS MO could not be set to gpu performance");
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gpex_debug_incr_error_cnt(HIST_BTS);
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} else
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qos_info.is_set_bts = 1;
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} else if ((clock == 0 || clock < qos_info.mo_min_clock) && qos_info.is_set_bts) {
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gpex_debug_new_record(HIST_BTS);
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ret = gpexbe_bts_set_bts_mo(0);
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gpex_debug_record(HIST_BTS, qos_info.is_set_bts, 0, ret);
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if (ret) {
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GPU_LOG(MALI_EXYNOS_WARNING, "BTS MO could not be unset from gpu performance");
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gpex_debug_incr_error_cnt(HIST_BTS);
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} else
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qos_info.is_set_bts = 0;
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}
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spin_unlock_irqrestore(&qos_info.bts_spinlock, flags);
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return ret;
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}
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int gpex_qos_set_from_clock(int gpu_clock)
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{
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int idx = 0;
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if (gpu_clock == 0) {
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gpex_qos_unset(QOS_MIF | QOS_LITTLE | QOS_MIDDLE | QOS_MIN);
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gpex_qos_set_bts_mo(gpu_clock);
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gpexbe_llc_coherency_set_ways(0);
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return 0;
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}
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idx = gpex_qos_get_table_idx(gpu_clock);
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if (idx < 0) {
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/* TODO: print error msg */
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return -EINVAL;
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}
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if (gpex_clboost_check_activation_condition()) {
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gpex_qos_set(QOS_MIF | QOS_MIN, clqos_table[idx].mif_min);
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gpex_qos_set(QOS_LITTLE | QOS_MIN, clqos_table[idx].little_min);
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gpex_qos_set(QOS_MIDDLE | QOS_MIN, clqos_table[idx].middle_min);
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gpex_qos_set(QOS_BIG | QOS_MAX, INT_MAX);
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/* TODO: revamp the qos interface so default max min can be set without knowing the clock */
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//gpex_qos_set(QOS_BIG | QOS_MAX, BIG_MAX);
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} else {
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if (gpex_tsg_get_pmqos() == true) {
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gpex_qos_set(QOS_MIF | QOS_MIN, 0);
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gpex_qos_set(QOS_LITTLE | QOS_MIN, 0);
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gpex_qos_set(QOS_MIDDLE | QOS_MIN, 0);
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gpex_qos_set(QOS_BIG | QOS_MAX, INT_MAX);
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} else {
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gpex_qos_set(QOS_MIF | QOS_MIN, qos_table[idx].mem_freq);
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if (!(gpex_gts_get_hcm_mode() & (HCM_MODE_A | HCM_MODE_C))) {
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gpex_qos_set(QOS_LITTLE | QOS_MIN,
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qos_table[idx].cpu_little_min_freq);
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} else if (gpex_gts_get_hcm_mode() & HCM_MODE_A) {
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gpex_qos_set(QOS_LITTLE | QOS_MIN,
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qos_info.gpu_heavy_compute_cpu0_min_clock);
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//pr_info("HCM: mode A QOS");
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} else if (gpex_gts_get_hcm_mode() & HCM_MODE_C) {
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gpex_qos_set(QOS_LITTLE | QOS_MIN,
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qos_info.gpu_heavy_compute_vk_cpu0_min_clock);
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//pr_info("HCM: mode B QOS");
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}
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gpex_qos_set(QOS_MIDDLE | QOS_MIN, qos_table[idx].cpu_middle_min_freq);
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gpex_qos_set(QOS_BIG | QOS_MAX, qos_table[idx].cpu_big_max_freq);
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}
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gpexwa_peak_notify_update();
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}
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gpex_qos_set_bts_mo(gpu_clock);
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gpexbe_llc_coherency_set_ways(qos_table[idx].llc_ways);
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return 0;
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}
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