154 lines
4.8 KiB
C
154 lines
4.8 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/**
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* dwc3-exynos.h - Samsung EXYNOS DWC3 Specific Glue layer header
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*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Author: Anton Tikhomirov <av.tikhomirov@samsung.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 of
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* the License as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __LINUX_USB_DWC3_EXYNOS_H
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#define __LINUX_USB_DWC3_EXYNOS_H
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/* Exynos Specific Register Definition */
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/* LINK Registers */
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#define DWC3_LU3LFPSRXTIM 0xd010
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#define DWC3_LSKIPFREQ 0xd020
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#define DWC3_LLUCTL 0xd024
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#define DWC3_BU31RHBDBG 0xd800
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/* Link Register - LLUCTL */
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#define DWC3_PENDING_HP_TIMER_US(n) ((n) << 16)
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#define DWC3_LLUCTL_LTSSM_TIMER_OVRRD BIT(23)
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#define DWC3_EN_US_HP_TIMER BIT(15)
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#define DWC3_LLUCTL_PIPE_RESET BIT(7)
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#define DWC3_FORCE_GEN1 BIT(10)
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#define DWC3_LLUCTL_TX_TS1_CNT(n) ((n) << 0)
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#define DWC3_LLUCTL_TX_TS1_CNT_MASK DWC3_LLUCTL_TX_TS1_CNT(0x1f)
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/* Link Register - LSKIPFREQ */
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#define DWC3_PM_ENTRY_TIMER_US(n) ((n) << 20)
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#define DWC3_PM_ENTRY_TIMER_US_MASK DWC3_PM_ENTRY_TIMER_US(0xf)
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#define DWC3_PM_LC_TIMER_US(n) ((n) << 24)
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#define DWC3_PM_LC_TIMER_US_MASK DWC3_PM_LC_TIMER_US(0x7)
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#define DWC3_EN_PM_TIMER_US BIT(27)
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/* Global User Control 1 Register */
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#define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17)
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#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28)
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#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
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#define DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT BIT(31)
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#define DWC3_GUCTL1_IP_GAP_ADD_ON(n) ((n) << 21)
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#define DWC3_GUCTL1_IP_GAP_ADD_ON_MASK (DWC3_GUCTL1_IP_GAP_ADD_ON(0x7))
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/* Debug Register */
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#define DWC3_BU31RHBDBG_TOUTCTL (0x1 << 3)
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#define DWC3_EXYNOS_IGNORE_CORE_OPS 0xff
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#define USB_BUS_CLOCK_DELAY_MS 3000
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/* USB Suspend State related to System Sleep */
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#define USB_NORMAL 0
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#define USB_SUSPEND_PREPARE 1
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#define USB_POST_SUSPEND 2
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struct dwc3_exynos_rsw {
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struct otg_fsm *fsm;
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struct work_struct work;
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};
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struct dwc3_exynos_config { /* Exynos Specific Configuations */
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bool adj_sof_accuracy;
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bool sparse_transfer_control;
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bool no_extra_delay;
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bool ux_exit_in_px_quirk;
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bool elastic_buf_mode_quirk;
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bool force_gen1;
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bool u1u2_exitfail_to_recov_quirk;
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u32 usb_host_device_timeout;
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u32 suspend_clk_freq;
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bool usb20_pkt_retry_disable;
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};
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struct dwc3_exynos {
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struct platform_device *usb2_phy;
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struct platform_device *usb3_phy;
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struct device *dev;
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struct dwc3 *dwc;
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struct clk **clocks;
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struct clk *bus_clock;
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struct clk *sclk_clock;
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struct regulator *vdd33;
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struct regulator *vdd10;
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int idle_ip_index;
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unsigned long bus_clock_rate;
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struct dwc3_exynos_rsw rsw;
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struct dwc3_otg *dotg;
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/* To check USB connection */
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int vbus_state;
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struct dwc3_exynos_config config;
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int usb_host_ready;
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struct delayed_work usb_qos_lock_delayed_work;
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struct workqueue_struct *int_qos_lock_wq;
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struct work_struct int_qos_work;
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struct work_struct int_kprobe_work;
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int is_perf;
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int lazy_vbus_up;
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};
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struct usb_xhci_pre_alloc {
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u8 *pre_dma_alloc;
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u64 offset;
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dma_addr_t dma;
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};
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bool dwc3_exynos_rsw_available(struct device *dev);
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int dwc3_exynos_rsw_setup(struct device *dev, struct otg_fsm *fsm);
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void dwc3_exynos_rsw_exit(struct device *dev);
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int dwc3_exynos_rsw_start(struct device *dev);
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void dwc3_exynos_rsw_stop(struct device *dev);
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int dwc3_exynos_id_event(struct device *dev, int state);
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int dwc3_exynos_vbus_event(struct device *dev, bool vbus_active);
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int dwc3_exynos_start_ldo(struct device *dev, bool on);
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int dwc3_exynos_phy_enable(int owner, bool on);
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int dwc3_otg_is_usb_ready(void);
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int dwc3_exynos_get_idle_ip_index(struct device *dev);
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int dwc3_exynos_set_bus_clock(struct device *dev, int clk_level);
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int dwc3_exynos_set_sclk_clock(struct device *dev);
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unsigned int of_usb_get_suspend_clk_freq(struct device *dev);
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int dwc3_probe(struct platform_device *pdev,
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struct dwc3_exynos *exynos);
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void dwc3_core_exit_mode(struct dwc3 *dwc);
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void dwc3_free_event_buffers(struct dwc3 *dwc);
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void dwc3_free_scratch_buffers(struct dwc3 *dwc);
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int dwc3_gadget_vbus_session(struct dwc3_exynos *exynos, int is_active);
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int dwc3_exynos_core_init(struct dwc3 *dwc, struct dwc3_exynos *exynos);
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void dwc3_exynos_gadget_disconnect_proc(struct dwc3 *dwc);
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int dwc3_core_susphy_set(struct dwc3 *dwc, int on);
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extern void exynos_usbdrd_shutdown_notice(int shutdown);
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extern void exynos_usbdrd_dp_use_notice(int lane);
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#if defined(CONFIG_OTG_CDP_SUPPORT)
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void exynos_usbdrd_cdp_set(struct phy *phy, int val);
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#endif
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#endif /* __LINUX_USB_DWC3_EXYNOS_H */
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