2024-06-15 16:02:09 -03:00
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# SPDX-License-Identifier: GPL-2.0-only
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#
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# For a description of the syntax of this configuration file,
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# see Documentation/kbuild/kconfig-language.rst.
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#
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config 64BIT
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bool
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config 32BIT
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bool
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config RISCV
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def_bool y
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select ARCH_CLOCKSOURCE_INIT
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select ARCH_SUPPORTS_ATOMIC_RMW
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select ARCH_HAS_BINFMT_FLAT
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select ARCH_HAS_DEBUG_VM_PGTABLE
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select ARCH_HAS_DEBUG_VIRTUAL if MMU
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select ARCH_HAS_DEBUG_WX
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select ARCH_HAS_GCOV_PROFILE_ALL
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select ARCH_HAS_GIGANTIC_PAGE
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select ARCH_HAS_KCOV
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select ARCH_HAS_MMIOWB
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select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
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select ARCH_HAS_PTE_SPECIAL
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select ARCH_HAS_SET_DIRECT_MAP
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select ARCH_HAS_SET_MEMORY
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select ARCH_HAS_STRICT_KERNEL_RWX if MMU
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select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
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select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT
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select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
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select ARCH_WANT_FRAME_POINTERS
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select ARCH_WANT_HUGE_PMD_SHARE if 64BIT
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select CLONE_BACKWARDS
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select CLINT_TIMER if !MMU
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select COMMON_CLK
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select EDAC_SUPPORT
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select GENERIC_ARCH_TOPOLOGY
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select GENERIC_ATOMIC64 if !64BIT
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select GENERIC_CLOCKEVENTS
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select GENERIC_EARLY_IOREMAP
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select GENERIC_GETTIMEOFDAY if HAVE_GENERIC_VDSO
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select GENERIC_IOREMAP
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select GENERIC_IRQ_MULTI_HANDLER
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select GENERIC_IRQ_SHOW
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select GENERIC_PCI_IOMAP
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select GENERIC_PTDUMP if MMU
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select GENERIC_SCHED_CLOCK
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select GENERIC_SMP_IDLE_THREAD
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select GENERIC_STRNCPY_FROM_USER if MMU
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select GENERIC_STRNLEN_USER if MMU
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select GENERIC_TIME_VSYSCALL if MMU && 64BIT
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select HANDLE_DOMAIN_IRQ
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select HAVE_ARCH_AUDITSYSCALL
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select HAVE_ARCH_JUMP_LABEL
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select HAVE_ARCH_JUMP_LABEL_RELATIVE
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select HAVE_ARCH_KASAN if MMU && 64BIT
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select HAVE_ARCH_KGDB
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select HAVE_ARCH_KGDB_QXFER_PKT
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select HAVE_ARCH_MMAP_RND_BITS if MMU
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select HAVE_ARCH_SECCOMP_FILTER
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select HAVE_ARCH_TRACEHOOK
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select HAVE_ASM_MODVERSIONS
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select HAVE_CONTEXT_TRACKING
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select HAVE_DEBUG_KMEMLEAK
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select HAVE_DMA_CONTIGUOUS if MMU
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select HAVE_EBPF_JIT if MMU
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select HAVE_FUTEX_CMPXCHG if FUTEX
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select HAVE_GCC_PLUGINS
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select HAVE_GENERIC_VDSO if MMU && 64BIT
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select HAVE_PCI
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select HAVE_PERF_EVENTS
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select HAVE_PERF_REGS
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select HAVE_PERF_USER_STACK_DUMP
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select HAVE_STACKPROTECTOR
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select HAVE_SYSCALL_TRACEPOINTS
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select IRQ_DOMAIN
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select MODULES_USE_ELF_RELA if MODULES
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select MODULE_SECTIONS if MODULES
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select OF
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select OF_EARLY_FLATTREE
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select OF_IRQ
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select PCI_DOMAINS_GENERIC if PCI
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select PCI_MSI if PCI
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select RISCV_INTC
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select RISCV_TIMER if RISCV_SBI
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select SPARSE_IRQ
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select SYSCTL_EXCEPTION_TRACE
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select THREAD_INFO_IN_TASK
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select UACCESS_MEMCPY if !MMU
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config ARCH_MMAP_RND_BITS_MIN
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default 18 if 64BIT
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default 8
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# max bits determined by the following formula:
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# VA_BITS - PAGE_SHIFT - 3
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config ARCH_MMAP_RND_BITS_MAX
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default 24 if 64BIT # SV39 based
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default 17
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# set if we run in machine mode, cleared if we run in supervisor mode
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config RISCV_M_MODE
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bool
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default !MMU
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# set if we are running in S-mode and can use SBI calls
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config RISCV_SBI
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bool
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depends on !RISCV_M_MODE
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default y
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config MMU
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bool "MMU-based Paged Memory Management Support"
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default y
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help
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Select if you want MMU-based virtualised addressing space
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support by paged memory management. If unsure, say 'Y'.
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config ZONE_DMA32
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bool
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default y if 64BIT
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config VA_BITS
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int
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default 32 if 32BIT
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default 39 if 64BIT
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config PA_BITS
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int
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default 34 if 32BIT
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default 56 if 64BIT
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config PAGE_OFFSET
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hex
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default 0xC0000000 if 32BIT && MAXPHYSMEM_1GB
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default 0x80000000 if 64BIT && !MMU
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default 0xffffffff80000000 if 64BIT && MAXPHYSMEM_2GB
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default 0xffffffe000000000 if 64BIT && MAXPHYSMEM_128GB
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config KASAN_SHADOW_OFFSET
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hex
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depends on KASAN_GENERIC
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default 0xdfffffc800000000 if 64BIT
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default 0xffffffff if 32BIT
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config ARCH_FLATMEM_ENABLE
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def_bool y
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config ARCH_SPARSEMEM_ENABLE
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def_bool y
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depends on MMU
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select SPARSEMEM_STATIC if 32BIT && SPARSEMEM
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select SPARSEMEM_VMEMMAP_ENABLE if 64BIT
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config ARCH_SELECT_MEMORY_MODEL
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def_bool ARCH_SPARSEMEM_ENABLE
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config ARCH_WANT_GENERAL_HUGETLB
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def_bool y
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config ARCH_SUPPORTS_DEBUG_PAGEALLOC
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def_bool y
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config SYS_SUPPORTS_HUGETLBFS
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depends on MMU
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def_bool y
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config STACKTRACE_SUPPORT
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def_bool y
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config TRACE_IRQFLAGS_SUPPORT
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def_bool y
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config GENERIC_BUG
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def_bool y
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depends on BUG
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select GENERIC_BUG_RELATIVE_POINTERS if 64BIT
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config GENERIC_BUG_RELATIVE_POINTERS
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bool
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config GENERIC_CALIBRATE_DELAY
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def_bool y
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config GENERIC_CSUM
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def_bool y
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config GENERIC_HWEIGHT
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def_bool y
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config FIX_EARLYCON_MEM
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def_bool MMU
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config PGTABLE_LEVELS
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int
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default 3 if 64BIT
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default 2
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config LOCKDEP_SUPPORT
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def_bool y
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source "arch/riscv/Kconfig.socs"
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menu "Platform type"
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choice
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prompt "Base ISA"
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default ARCH_RV64I
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help
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This selects the base ISA that this kernel will target and must match
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the target platform.
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config ARCH_RV32I
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bool "RV32I"
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select 32BIT
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select GENERIC_LIB_ASHLDI3
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select GENERIC_LIB_ASHRDI3
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select GENERIC_LIB_LSHRDI3
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select GENERIC_LIB_UCMPDI2
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select MMU
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config ARCH_RV64I
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bool "RV64I"
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select 64BIT
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select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 && GCC_VERSION >= 50000
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select HAVE_DYNAMIC_FTRACE if MMU
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select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
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select HAVE_FTRACE_MCOUNT_RECORD
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select HAVE_FUNCTION_GRAPH_TRACER
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select HAVE_FUNCTION_TRACER
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select SWIOTLB if MMU
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endchoice
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# We must be able to map all physical memory into the kernel, but the compiler
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# is still a bit more efficient when generating code if it's setup in a manner
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# such that it can only map 2GiB of memory.
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choice
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prompt "Kernel Code Model"
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default CMODEL_MEDLOW if 32BIT
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default CMODEL_MEDANY if 64BIT
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config CMODEL_MEDLOW
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bool "medium low code model"
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config CMODEL_MEDANY
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bool "medium any code model"
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endchoice
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config MODULE_SECTIONS
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bool
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select HAVE_MOD_ARCH_SPECIFIC
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choice
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prompt "Maximum Physical Memory"
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default MAXPHYSMEM_1GB if 32BIT
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default MAXPHYSMEM_2GB if 64BIT && CMODEL_MEDLOW
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default MAXPHYSMEM_128GB if 64BIT && CMODEL_MEDANY
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config MAXPHYSMEM_1GB
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depends on 32BIT
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bool "1GiB"
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config MAXPHYSMEM_2GB
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depends on 64BIT && CMODEL_MEDLOW
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bool "2GiB"
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config MAXPHYSMEM_128GB
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depends on 64BIT && CMODEL_MEDANY
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bool "128GiB"
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endchoice
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config SMP
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bool "Symmetric Multi-Processing"
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help
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This enables support for systems with more than one CPU. If
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you say N here, the kernel will run on single and
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multiprocessor machines, but will use only one CPU of a
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multiprocessor machine. If you say Y here, the kernel will run
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on many, but not all, single processor machines. On a single
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processor machine, the kernel will run faster if you say N
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here.
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If you don't know what to do here, say N.
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config NR_CPUS
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int "Maximum number of CPUs (2-32)"
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range 2 32
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depends on SMP
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default "8"
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config HOTPLUG_CPU
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bool "Support for hot-pluggable CPUs"
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depends on SMP
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select GENERIC_IRQ_MIGRATION
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help
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Say Y here to experiment with turning CPUs off and on. CPUs
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can be controlled through /sys/devices/system/cpu.
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Say N if you want to disable CPU hotplug.
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choice
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prompt "CPU Tuning"
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default TUNE_GENERIC
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config TUNE_GENERIC
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bool "generic"
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endchoice
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config RISCV_ISA_C
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bool "Emit compressed instructions when building Linux"
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default y
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help
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Adds "C" to the ISA subsets that the toolchain is allowed to emit
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when building Linux, which results in compressed instructions in the
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Linux binary.
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If you don't know what to do here, say Y.
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menu "supported PMU type"
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depends on PERF_EVENTS
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config RISCV_BASE_PMU
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bool "Base Performance Monitoring Unit"
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def_bool y
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help
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A base PMU that serves as a reference implementation and has limited
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feature of perf. It can run on any RISC-V machines so serves as the
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fallback, but this option can also be disable to reduce kernel size.
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endmenu
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config TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI
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def_bool y
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# https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=aed44286efa8ae8717a77d94b51ac3614e2ca6dc
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depends on AS_IS_GNU && AS_VERSION >= 23800
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help
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Newer binutils versions default to ISA spec version 20191213 which
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moves some instructions from the I extension to the Zicsr and Zifencei
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extensions.
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config TOOLCHAIN_NEEDS_OLD_ISA_SPEC
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def_bool y
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depends on TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI
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# https://github.com/llvm/llvm-project/commit/22e199e6afb1263c943c0c0d4498694e15bf8a16
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depends on CC_IS_CLANG && CLANG_VERSION < 170000
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help
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Certain versions of clang do not support zicsr and zifencei via -march
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but newer versions of binutils require it for the reasons noted in the
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help text of CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI. This
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option causes an older ISA spec compatible with these older versions
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of clang to be passed to GAS, which has the same result as passing zicsr
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and zifencei to -march.
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config FPU
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bool "FPU support"
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default y
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help
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Say N here if you want to disable all floating-point related procedure
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in the kernel.
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If you don't know what to do here, say Y.
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endmenu
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menu "Kernel features"
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source "kernel/Kconfig.hz"
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config RISCV_SBI_V01
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bool "SBI v0.1 support"
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default y
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depends on RISCV_SBI
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help
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This config allows kernel to use SBI v0.1 APIs. This will be
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deprecated in future once legacy M-mode software are no longer in use.
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endmenu
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menu "Boot options"
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config CMDLINE
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string "Built-in kernel command line"
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help
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For most platforms, the arguments for the kernel's command line
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are provided at run-time, during boot. However, there are cases
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where either no arguments are being provided or the provided
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|
|
arguments are insufficient or even invalid.
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|
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|
When that occurs, it is possible to define a built-in command
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|
|
line here and choose how the kernel should use it later on.
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|
|
choice
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|
prompt "Built-in command line usage" if CMDLINE != ""
|
|
|
|
default CMDLINE_FALLBACK
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|
|
|
help
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|
|
|
Choose how the kernel will handle the provided built-in command
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|
|
line.
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|
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|
|
|
|
config CMDLINE_FALLBACK
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|
bool "Use bootloader kernel arguments if available"
|
|
|
|
help
|
|
|
|
Use the built-in command line as fallback in case we get nothing
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|
|
|
during boot. This is the default behaviour.
|
|
|
|
|
|
|
|
config CMDLINE_EXTEND
|
|
|
|
bool "Extend bootloader kernel arguments"
|
|
|
|
help
|
|
|
|
The command-line arguments provided during boot will be
|
|
|
|
appended to the built-in command line. This is useful in
|
|
|
|
cases where the provided arguments are insufficient and
|
|
|
|
you don't want to or cannot modify them.
|
|
|
|
|
|
|
|
|
|
|
|
config CMDLINE_FORCE
|
|
|
|
bool "Always use the default kernel command string"
|
|
|
|
help
|
|
|
|
Always use the built-in command line, even if we get one during
|
|
|
|
boot. This is useful in case you need to override the provided
|
|
|
|
command line on systems where you don't have or want control
|
|
|
|
over it.
|
|
|
|
|
|
|
|
endchoice
|
|
|
|
|
|
|
|
config EFI_STUB
|
|
|
|
bool
|
|
|
|
|
|
|
|
config EFI
|
|
|
|
bool "UEFI runtime support"
|
|
|
|
depends on OF
|
|
|
|
select LIBFDT
|
|
|
|
select UCS2_STRING
|
|
|
|
select EFI_PARAMS_FROM_FDT
|
|
|
|
select EFI_STUB
|
|
|
|
select EFI_GENERIC_STUB
|
|
|
|
select EFI_RUNTIME_WRAPPERS
|
|
|
|
select RISCV_ISA_C
|
|
|
|
depends on MMU
|
|
|
|
default y
|
|
|
|
help
|
|
|
|
This option provides support for runtime services provided
|
|
|
|
by UEFI firmware (such as non-volatile variables, realtime
|
|
|
|
clock, and platform reset). A UEFI stub is also provided to
|
|
|
|
allow the kernel to be booted as an EFI application. This
|
|
|
|
is only useful on systems that have UEFI firmware.
|
|
|
|
|
riscv: Enable per-task stack canaries
[ Upstream commit fea2fed201ee5647699018a56fbb6a5e8cc053a5 ]
This enables the use of per-task stack canary values if GCC has
support for emitting the stack canary reference relative to the
value of tp, which holds the task struct pointer in the riscv
kernel.
After compare arm64 and x86 implementations, seems arm64's is more
flexible and readable. The key point is how gcc get the offset of
stack_canary from gs/el0_sp.
x86: Use a fix offset from gs, not flexible.
struct fixed_percpu_data {
/*
* GCC hardcodes the stack canary as %gs:40. Since the
* irq_stack is the object at %gs:0, we reserve the bottom
* 48 bytes of the irq stack for the canary.
*/
char gs_base[40]; // :(
unsigned long stack_canary;
};
arm64: Use -mstack-protector-guard-offset & guard-reg
gcc options:
-mstack-protector-guard=sysreg
-mstack-protector-guard-reg=sp_el0
-mstack-protector-guard-offset=xxx
riscv: Use -mstack-protector-guard-offset & guard-reg
gcc options:
-mstack-protector-guard=tls
-mstack-protector-guard-reg=tp
-mstack-protector-guard-offset=xxx
GCC's implementation has been merged:
commit c931e8d5a96463427040b0d11f9c4352ac22b2b0
Author: Cooper Qu <cooper.qu@linux.alibaba.com>
Date: Mon Jul 13 16:15:08 2020 +0800
RISC-V: Add support for TLS stack protector canary access
In the end, these codes are inserted by gcc before return:
* 0xffffffe00020b396 <+120>: ld a5,1008(tp) # 0x3f0
* 0xffffffe00020b39a <+124>: xor a5,a5,a4
* 0xffffffe00020b39c <+126>: mv a0,s5
* 0xffffffe00020b39e <+128>: bnez a5,0xffffffe00020b61c <_do_fork+766>
0xffffffe00020b3a2 <+132>: ld ra,136(sp)
0xffffffe00020b3a4 <+134>: ld s0,128(sp)
0xffffffe00020b3a6 <+136>: ld s1,120(sp)
0xffffffe00020b3a8 <+138>: ld s2,112(sp)
0xffffffe00020b3aa <+140>: ld s3,104(sp)
0xffffffe00020b3ac <+142>: ld s4,96(sp)
0xffffffe00020b3ae <+144>: ld s5,88(sp)
0xffffffe00020b3b0 <+146>: ld s6,80(sp)
0xffffffe00020b3b2 <+148>: ld s7,72(sp)
0xffffffe00020b3b4 <+150>: addi sp,sp,144
0xffffffe00020b3b6 <+152>: ret
...
* 0xffffffe00020b61c <+766>: auipc ra,0x7f8
* 0xffffffe00020b620 <+770>: jalr -1764(ra) # 0xffffffe000a02f38 <__stack_chk_fail>
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Cooper Qu <cooper.qu@linux.alibaba.com>
Reviewed-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Stable-dep-of: d14fa1fcf69d ("riscv: process: Fix kernel gp leakage")
Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-12-17 16:29:18 +00:00
|
|
|
config CC_HAVE_STACKPROTECTOR_TLS
|
|
|
|
def_bool $(cc-option,-mstack-protector-guard=tls -mstack-protector-guard-reg=tp -mstack-protector-guard-offset=0)
|
|
|
|
|
|
|
|
config STACKPROTECTOR_PER_TASK
|
|
|
|
def_bool y
|
2021-07-06 09:26:21 -07:00
|
|
|
depends on !GCC_PLUGIN_RANDSTRUCT
|
riscv: Enable per-task stack canaries
[ Upstream commit fea2fed201ee5647699018a56fbb6a5e8cc053a5 ]
This enables the use of per-task stack canary values if GCC has
support for emitting the stack canary reference relative to the
value of tp, which holds the task struct pointer in the riscv
kernel.
After compare arm64 and x86 implementations, seems arm64's is more
flexible and readable. The key point is how gcc get the offset of
stack_canary from gs/el0_sp.
x86: Use a fix offset from gs, not flexible.
struct fixed_percpu_data {
/*
* GCC hardcodes the stack canary as %gs:40. Since the
* irq_stack is the object at %gs:0, we reserve the bottom
* 48 bytes of the irq stack for the canary.
*/
char gs_base[40]; // :(
unsigned long stack_canary;
};
arm64: Use -mstack-protector-guard-offset & guard-reg
gcc options:
-mstack-protector-guard=sysreg
-mstack-protector-guard-reg=sp_el0
-mstack-protector-guard-offset=xxx
riscv: Use -mstack-protector-guard-offset & guard-reg
gcc options:
-mstack-protector-guard=tls
-mstack-protector-guard-reg=tp
-mstack-protector-guard-offset=xxx
GCC's implementation has been merged:
commit c931e8d5a96463427040b0d11f9c4352ac22b2b0
Author: Cooper Qu <cooper.qu@linux.alibaba.com>
Date: Mon Jul 13 16:15:08 2020 +0800
RISC-V: Add support for TLS stack protector canary access
In the end, these codes are inserted by gcc before return:
* 0xffffffe00020b396 <+120>: ld a5,1008(tp) # 0x3f0
* 0xffffffe00020b39a <+124>: xor a5,a5,a4
* 0xffffffe00020b39c <+126>: mv a0,s5
* 0xffffffe00020b39e <+128>: bnez a5,0xffffffe00020b61c <_do_fork+766>
0xffffffe00020b3a2 <+132>: ld ra,136(sp)
0xffffffe00020b3a4 <+134>: ld s0,128(sp)
0xffffffe00020b3a6 <+136>: ld s1,120(sp)
0xffffffe00020b3a8 <+138>: ld s2,112(sp)
0xffffffe00020b3aa <+140>: ld s3,104(sp)
0xffffffe00020b3ac <+142>: ld s4,96(sp)
0xffffffe00020b3ae <+144>: ld s5,88(sp)
0xffffffe00020b3b0 <+146>: ld s6,80(sp)
0xffffffe00020b3b2 <+148>: ld s7,72(sp)
0xffffffe00020b3b4 <+150>: addi sp,sp,144
0xffffffe00020b3b6 <+152>: ret
...
* 0xffffffe00020b61c <+766>: auipc ra,0x7f8
* 0xffffffe00020b620 <+770>: jalr -1764(ra) # 0xffffffe000a02f38 <__stack_chk_fail>
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Cooper Qu <cooper.qu@linux.alibaba.com>
Reviewed-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Stable-dep-of: d14fa1fcf69d ("riscv: process: Fix kernel gp leakage")
Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-12-17 16:29:18 +00:00
|
|
|
depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_TLS
|
|
|
|
|
2024-06-15 16:02:09 -03:00
|
|
|
endmenu
|
|
|
|
|
|
|
|
config BUILTIN_DTB
|
|
|
|
def_bool n
|
|
|
|
depends on RISCV_M_MODE
|
|
|
|
depends on OF
|
|
|
|
|
|
|
|
menu "Power management options"
|
|
|
|
|
|
|
|
source "kernel/power/Kconfig"
|
|
|
|
|
|
|
|
endmenu
|
|
|
|
|
|
|
|
source "drivers/firmware/Kconfig"
|